Index: llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp +++ llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp @@ -3939,7 +3939,8 @@ uint32_t AMDGPUTargetLowering::getImplicitParameterOffset( const MachineFunction &MF, const ImplicitParameter Param) const { const AMDGPUMachineFunction *MFI = MF.getInfo(); - const AMDGPUSubtarget &ST = MF.getSubtarget(); + const AMDGPUCommonSubtarget &ST = + AMDGPUCommonSubtarget::get(getTargetMachine(), MF.getFunction()); unsigned ExplicitArgOffset = ST.getExplicitKernelArgOffset(MF.getFunction()); unsigned Alignment = ST.getAlignmentForImplicitArgPtr(); uint64_t ArgOffset = alignTo(MFI->getExplicitKernArgSize(), Alignment) + Index: llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h =================================================================== --- llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h +++ llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h @@ -114,6 +114,18 @@ return TargetTriple.getOS() == Triple::AMDPAL; } + bool isMesa3DOS() const { + return TargetTriple.getOS() == Triple::Mesa3D; + } + + bool isMesaKernel(const Function &F) const { + return isMesa3DOS() && !AMDGPU::isShader(F.getCallingConv()); + } + + bool isAmdCodeObjectV2(const Function &F) const { + return isAmdHsaOS() || isMesaKernel(F); + } + bool has16BitInsts() const { return Has16BitInsts; } @@ -166,6 +178,12 @@ return isAmdHsaOS() ? 8 : 4; } + /// Returns the offset in bytes from the start of the input buffer + /// of the first explicit kernel argument. + unsigned getExplicitKernelArgOffset(const Function &F) const { + return isAmdCodeObjectV2(F) ? 0 : 36; + } + /// \returns Maximum number of work groups per compute unit supported by the /// subtarget and limited by given \p FlatWorkGroupSize. unsigned getMaxWorkGroupsPerCU(unsigned FlatWorkGroupSize) const { @@ -384,10 +402,6 @@ void ParseSubtargetFeatures(StringRef CPU, StringRef FS); - bool isMesa3DOS() const { - return TargetTriple.getOS() == Triple::Mesa3D; - } - Generation getGeneration() const { return (Generation)Gen; } @@ -603,19 +617,11 @@ return HasUnpackedD16VMem; } - bool isMesaKernel(const Function &F) const { - return isMesa3DOS() && !AMDGPU::isShader(F.getCallingConv()); - } - // Covers VS/PS/CS graphics shaders bool isMesaGfxShader(const Function &F) const { return isMesa3DOS() && AMDGPU::isShader(F.getCallingConv()); } - bool isAmdCodeObjectV2(const Function &F) const { - return isAmdHsaOS() || isMesaKernel(F); - } - bool hasMad64_32() const { return getGeneration() >= SEA_ISLANDS; } @@ -652,12 +658,6 @@ return D16PreservesUnusedBits; } - /// Returns the offset in bytes from the start of the input buffer - /// of the first explicit kernel argument. - unsigned getExplicitKernelArgOffset(const Function &F) const { - return isAmdCodeObjectV2(F) ? 0 : 36; - } - /// \returns Number of bytes of arguments that are passed to a shader or /// kernel in addition to the explicit ones declared for the function. unsigned getImplicitArgNumBytes(const Function &F) const { @@ -1088,10 +1088,6 @@ bool hasFMA() const { return FMA; } - unsigned getExplicitKernelArgOffset(const MachineFunction &MF) const { - return 36; - } - bool hasCFAluBug() const { return CFALUBug; } bool hasVertexCache() const { return HasVertexCache; } Index: llvm/trunk/lib/Target/AMDGPU/R600ISelLowering.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/R600ISelLowering.cpp +++ llvm/trunk/lib/Target/AMDGPU/R600ISelLowering.cpp @@ -1658,7 +1658,7 @@ unsigned ValBase = ArgLocs[In.getOrigArgIndex()].getLocMemOffset(); unsigned PartOffset = VA.getLocMemOffset(); - unsigned Offset = Subtarget->getExplicitKernelArgOffset(MF) + + unsigned Offset = Subtarget->getExplicitKernelArgOffset(MF.getFunction()) + VA.getLocMemOffset(); MachinePointerInfo PtrInfo(UndefValue::get(PtrTy), PartOffset - ValBase);