Index: lib/Target/AArch64/AArch64SystemOperands.td =================================================================== --- lib/Target/AArch64/AArch64SystemOperands.td +++ lib/Target/AArch64/AArch64SystemOperands.td @@ -330,6 +330,7 @@ let Encoding{6-3} = crm; let Encoding{2-0} = op2; bit NeedsReg = needsreg; + code Requires = [{ {} }]; } def : TLBI<"IPAS2E1IS", 0b100, 0b1000, 0b0000, 0b001>; @@ -365,6 +366,59 @@ def : TLBI<"VMALLS12E1", 0b100, 0b1000, 0b0111, 0b110, 0>; def : TLBI<"VAALE1", 0b000, 0b1000, 0b0111, 0b111>; +// Armv8.4-A Outer Sharable TLB Maintenance instructions: +let Requires = [{ {AArch64::HasV8_4aOps} }] in { +// op1 CRn CRm op2 +def : TLBI<"VMALLE1OS", 0b000, 0b1000, 0b0001, 0b000, 0>; +def : TLBI<"VAE1OS", 0b000, 0b1000, 0b0001, 0b001>; +def : TLBI<"ASIDE1OS", 0b000, 0b1000, 0b0001, 0b010>; +def : TLBI<"VAAE1OS", 0b000, 0b1000, 0b0001, 0b011>; +def : TLBI<"VALE1OS", 0b000, 0b1000, 0b0001, 0b101>; +def : TLBI<"VAALE1OS", 0b000, 0b1000, 0b0001, 0b111>; +def : TLBI<"IPAS2E1OS", 0b100, 0b1000, 0b0100, 0b000>; +def : TLBI<"IPAS2LE1OS", 0b100, 0b1000, 0b0100, 0b100>; +def : TLBI<"VAE2OS", 0b100, 0b1000, 0b0001, 0b001>; +def : TLBI<"VALE2OS", 0b100, 0b1000, 0b0001, 0b101>; +def : TLBI<"VMALLS12E1OS", 0b100, 0b1000, 0b0001, 0b110, 0>; +def : TLBI<"VAE3OS", 0b110, 0b1000, 0b0001, 0b001>; +def : TLBI<"VALE3OS", 0b110, 0b1000, 0b0001, 0b101>; +def : TLBI<"ALLE2OS", 0b100, 0b1000, 0b0001, 0b000, 0>; +def : TLBI<"ALLE1OS", 0b100, 0b1000, 0b0001, 0b100, 0>; +def : TLBI<"ALLE3OS", 0b110, 0b1000, 0b0001, 0b000, 0>; + +// Armv8.4-A TLB Range Maintenance instructions: +// op1 CRn CRm op2 +def : TLBI<"RVAE1", 0b000, 0b1000, 0b0110, 0b001>; +def : TLBI<"RVAAE1", 0b000, 0b1000, 0b0110, 0b011>; +def : TLBI<"RVALE1", 0b000, 0b1000, 0b0110, 0b101>; +def : TLBI<"RVAALE1", 0b000, 0b1000, 0b0110, 0b111>; +def : TLBI<"RVAE1IS", 0b000, 0b1000, 0b0010, 0b001>; +def : TLBI<"RVAAE1IS", 0b000, 0b1000, 0b0010, 0b011>; +def : TLBI<"RVALE1IS", 0b000, 0b1000, 0b0010, 0b101>; +def : TLBI<"RVAALE1IS", 0b000, 0b1000, 0b0010, 0b111>; +def : TLBI<"RVAE1OS", 0b000, 0b1000, 0b0101, 0b001>; +def : TLBI<"RVAAE1OS", 0b000, 0b1000, 0b0101, 0b011>; +def : TLBI<"RVALE1OS", 0b000, 0b1000, 0b0101, 0b101>; +def : TLBI<"RVAALE1OS", 0b000, 0b1000, 0b0101, 0b111>; +def : TLBI<"RIPAS2E1IS", 0b100, 0b1000, 0b0000, 0b010>; +def : TLBI<"RIPAS2LE1IS", 0b100, 0b1000, 0b0000, 0b110>; +def : TLBI<"RIPAS2E1", 0b100, 0b1000, 0b0100, 0b010>; +def : TLBI<"RIPAS2LE1", 0b100, 0b1000, 0b0100, 0b110>; +def : TLBI<"RIPAS2E1OS", 0b100, 0b1000, 0b0100, 0b011>; +def : TLBI<"RIPAS2LE1OS", 0b100, 0b1000, 0b0100, 0b111>; +def : TLBI<"RVAE2", 0b100, 0b1000, 0b0110, 0b001>; +def : TLBI<"RVALE2", 0b100, 0b1000, 0b0110, 0b101>; +def : TLBI<"RVAE2IS", 0b100, 0b1000, 0b0010, 0b001>; +def : TLBI<"RVALE2IS", 0b100, 0b1000, 0b0010, 0b101>; +def : TLBI<"RVAE2OS", 0b100, 0b1000, 0b0101, 0b001>; +def : TLBI<"RVALE2OS", 0b100, 0b1000, 0b0101, 0b101>; +def : TLBI<"RVAE3", 0b110, 0b1000, 0b0110, 0b001>; +def : TLBI<"RVALE3", 0b110, 0b1000, 0b0110, 0b101>; +def : TLBI<"RVAE3IS", 0b110, 0b1000, 0b0010, 0b001>; +def : TLBI<"RVALE3IS", 0b110, 0b1000, 0b0010, 0b101>; +def : TLBI<"RVAE3OS", 0b110, 0b1000, 0b0101, 0b001>; +def : TLBI<"RVALE3OS", 0b110, 0b1000, 0b0101, 0b101>; +} //===----------------------------------------------------------------------===// // MRS/MSR (system register read/write) instruction options. Index: lib/Target/AArch64/Utils/AArch64BaseInfo.h =================================================================== --- lib/Target/AArch64/Utils/AArch64BaseInfo.h +++ lib/Target/AArch64/Utils/AArch64BaseInfo.h @@ -285,6 +285,8 @@ struct SysAliasReg : SysAlias { bool NeedsReg; SysAliasReg(const char *N, uint16_t E, bool R) : SysAlias(N, E), NeedsReg(R) {}; + SysAliasReg(const char *N, uint16_t E, bool R, FeatureBitset F) : SysAlias(N, E, F), + NeedsReg(R) {}; }; namespace AArch64AT{ Index: test/MC/AArch64/armv8.4a-tlb.s =================================================================== --- /dev/null +++ test/MC/AArch64/armv8.4a-tlb.s @@ -0,0 +1,263 @@ +// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.4a < %s 2> %t | FileCheck %s --check-prefix=CHECK +// RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s +// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.4a < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-V84 + +// Outer shareable TLB maintenance instructions: +tlbi vmalle1os +tlbi vae1os, xzr +tlbi vae1os, x0 +tlbi aside1os, x1 +tlbi vaae1os, x2 +tlbi vale1os, x3 +tlbi vaale1os, x4 +tlbi ipas2e1os, x5 +tlbi ipas2le1os, x6 +tlbi vae2os, x7 +tlbi vale2os, x8 +tlbi vmalls12e1os +tlbi vae3os, x9 +tlbi vale3os, x10 +tlbi alle2os +tlbi alle1os +tlbi alle3os + +//CHECK: tlbi vmalle1os // encoding: [0x1f,0x81,0x08,0xd5] +//CHECK-NEXT: tlbi vae1os, xzr // encoding: [0x3f,0x81,0x08,0xd5] +//CHECK-NEXT: tlbi vae1os, x0 // encoding: [0x20,0x81,0x08,0xd5] +//CHECK-NEXT: tlbi aside1os, x1 // encoding: [0x41,0x81,0x08,0xd5] +//CHECK-NEXT: tlbi vaae1os, x2 // encoding: [0x62,0x81,0x08,0xd5] +//CHECK-NEXT: tlbi vale1os, x3 // encoding: [0xa3,0x81,0x08,0xd5] +//CHECK-NEXT: tlbi vaale1os, x4 // encoding: [0xe4,0x81,0x08,0xd5] +//CHECK-NEXT: tlbi ipas2e1os, x5 // encoding: [0x05,0x84,0x0c,0xd5] +//CHECK-NEXT: tlbi ipas2le1os, x6 // encoding: [0x86,0x84,0x0c,0xd5] +//CHECK-NEXT: tlbi vae2os, x7 // encoding: [0x27,0x81,0x0c,0xd5] +//CHECK-NEXT: tlbi vale2os, x8 // encoding: [0xa8,0x81,0x0c,0xd5] +//CHECK-NEXT: tlbi vmalls12e1os // encoding: [0xdf,0x81,0x0c,0xd5] +//CHECK-NEXT: tlbi vae3os, x9 // encoding: [0x29,0x81,0x0e,0xd5] +//CHECK-NEXT: tlbi vale3os, x10 // encoding: [0xaa,0x81,0x0e,0xd5] +//CHECK-NEXT: tlbi alle2os // encoding: [0x1f,0x81,0x0c,0xd5] +//CHECK-NEXT: tlbi alle1os // encoding: [0x9f,0x81,0x0c,0xd5] +//CHECK-NEXT: tlbi alle3os // encoding: [0x1f,0x81,0x0e,0xd5] + +tlbi vae1os, sp + +//CHECK-ERROR: error: invalid operand for instruction +//CHECK-ERROR-NEXT: tlbi vae1os, sp +//CHECK-ERROR-NEXT: ^ + +//CHECK-NO-V84: error: TLBI VMALLE1OS requires ARMv8.4a +//CHECK-NO-V84-NEXT: tlbi vmalle1os +//CHECK-NO-V84-NEXT: ^ +//CHECK-NO-V84-NEXT: error: TLBI VAE1OS requires ARMv8.4a +//CHECK-NO-V84-NEXT: tlbi vae1os, xzr +//CHECK-NO-V84-NEXT: ^ +//CHECK-NO-V84-NEXT: error: TLBI VAE1OS requires ARMv8.4a +//CHECK-NO-V84-NEXT: tlbi vae1os, x0 +//CHECK-NO-V84-NEXT: ^ +//CHECK-NO-V84-NEXT: error: TLBI ASIDE1OS requires ARMv8.4a +//CHECK-NO-V84-NEXT: tlbi aside1os, x1 +//CHECK-NO-V84-NEXT: ^ +//CHECK-NO-V84-NEXT: error: TLBI VAAE1OS requires ARMv8.4a +//CHECK-NO-V84-NEXT: tlbi vaae1os, x2 +//CHECK-NO-V84-NEXT: ^ +//CHECK-NO-V84-NEXT: error: TLBI VALE1OS requires ARMv8.4a +//CHECK-NO-V84-NEXT: tlbi vale1os, x3 +//CHECK-NO-V84-NEXT: ^ +//CHECK-NO-V84-NEXT: error: TLBI VAALE1OS requires ARMv8.4a +//CHECK-NO-V84-NEXT: tlbi vaale1os, x4 +//CHECK-NO-V84-NEXT: ^ +//CHECK-NO-V84-NEXT: error: TLBI IPAS2E1OS requires ARMv8.4a +//CHECK-NO-V84-NEXT: tlbi ipas2e1os, x5 +//CHECK-NO-V84-NEXT: ^ +//CHECK-NO-V84-NEXT: error: TLBI IPAS2LE1OS requires ARMv8.4a +//CHECK-NO-V84-NEXT: tlbi ipas2le1os, x6 +//CHECK-NO-V84-NEXT: ^ +//CHECK-NO-V84-NEXT: error: TLBI VAE2OS requires ARMv8.4a +//CHECK-NO-V84-NEXT: tlbi vae2os, x7 +//CHECK-NO-V84-NEXT: ^ +//CHECK-NO-V84-NEXT: error: TLBI VALE2OS requires ARMv8.4a +//CHECK-NO-V84-NEXT: tlbi vale2os, x8 +//CHECK-NO-V84-NEXT: ^ +//CHECK-NO-V84-NEXT: error: TLBI VMALLS12E1OS requires ARMv8.4a +//CHECK-NO-V84-NEXT: tlbi vmalls12e1os +//CHECK-NO-V84-NEXT: ^ +//CHECK-NO-V84-NEXT: error: TLBI VAE3OS requires ARMv8.4a +//CHECK-NO-V84-NEXT: tlbi vae3os, x9 +//CHECK-NO-V84-NEXT: ^ +//CHECK-NO-V84-NEXT: error: TLBI VALE3OS requires ARMv8.4a +//CHECK-NO-V84-NEXT: tlbi vale3os, x10 +//CHECK-NO-V84-NEXT: ^ +//CHECK-NO-V84-NEXT: error: TLBI ALLE2OS requires ARMv8.4a +//CHECK-NO-V84-NEXT: tlbi alle2os +//CHECK-NO-V84-NEXT: ^ +//CHECK-NO-V84-NEXT: error: TLBI ALLE1OS requires ARMv8.4a +//CHECK-NO-V84-NEXT: tlbi alle1os +//CHECK-NO-V84-NEXT: ^ +//CHECK-NO-V84-NEXT: error: TLBI ALLE3OS requires ARMv8.4a +//CHECK-NO-V84-NEXT: tlbi alle3os +//CHECK-NO-V84-NEXT: ^ + +// TLB Range maintenance instructions: +tlbi rvae1, x3 +tlbi rvaae1, x3 +tlbi rvale1, x3 +tlbi rvaale1, x3 +tlbi rvae1is, x3 +tlbi rvaae1is, x3 +tlbi rvale1is, x3 +tlbi rvaale1is, x3 +tlbi rvae1os, x3 +tlbi rvaae1os, x3 +tlbi rvale1os, x3 +tlbi rvaale1os, x3 +tlbi ripas2e1is, x3 +tlbi ripas2le1is, x3 +tlbi ripas2e1, X3 +tlbi ripas2le1, X3 +tlbi ripas2e1os, X3 +tlbi ripas2le1os, X3 +tlbi rvae2, X3 +tlbi rvale2, X3 +tlbi rvae2is, X3 +tlbi rvale2is, X3 +tlbi rvae2os, X3 +tlbi rvale2os, X3 +tlbi rvae3, X3 +tlbi rvale3, X3 +tlbi rvae3is, X3 +tlbi rvale3is, X3 +tlbi rvae3os, X3 +tlbi rvale3os, X3 +tlbi rvale3os, XZR + +//CHECK: tlbi rvae1, x3 // encoding: [0x23,0x86,0x08,0xd5] +//CHECK-NEXT: tlbi rvaae1, x3 // encoding: [0x63,0x86,0x08,0xd5] +//CHECK-NEXT: tlbi rvale1, x3 // encoding: [0xa3,0x86,0x08,0xd5] +//CHECK-NEXT: tlbi rvaale1, x3 // encoding: [0xe3,0x86,0x08,0xd5] +//CHECK-NEXT: tlbi rvae1is, x3 // encoding: [0x23,0x82,0x08,0xd5] +//CHECK-NEXT: tlbi rvaae1is, x3 // encoding: [0x63,0x82,0x08,0xd5] +//CHECK-NEXT: tlbi rvale1is, x3 // encoding: [0xa3,0x82,0x08,0xd5] +//CHECK-NEXT: tlbi rvaale1is, x3 // encoding: [0xe3,0x82,0x08,0xd5] +//CHECK-NEXT: tlbi rvae1os, x3 // encoding: [0x23,0x85,0x08,0xd5] +//CHECK-NEXT: tlbi rvaae1os, x3 // encoding: [0x63,0x85,0x08,0xd5] +//CHECK-NEXT: tlbi rvale1os, x3 // encoding: [0xa3,0x85,0x08,0xd5] +//CHECK-NEXT: tlbi rvaale1os, x3 // encoding: [0xe3,0x85,0x08,0xd5] +//CHECK-NEXT: tlbi ripas2e1is, x3 // encoding: [0x43,0x80,0x0c,0xd5] +//CHECK-NEXT: tlbi ripas2le1is, x3 // encoding: [0xc3,0x80,0x0c,0xd5] +//CHECK-NEXT: tlbi ripas2e1, x3 // encoding: [0x43,0x84,0x0c,0xd5] +//CHECK-NEXT: tlbi ripas2le1, x3 // encoding: [0xc3,0x84,0x0c,0xd5] +//CHECK-NEXT: tlbi ripas2e1os, x3 // encoding: [0x63,0x84,0x0c,0xd5] +//CHECK-NEXT: tlbi ripas2le1os, x3 // encoding: [0xe3,0x84,0x0c,0xd5] +//CHECK-NEXT: tlbi rvae2, x3 // encoding: [0x23,0x86,0x0c,0xd5] +//CHECK-NEXT: tlbi rvale2, x3 // encoding: [0xa3,0x86,0x0c,0xd5] +//CHECK-NEXT: tlbi rvae2is, x3 // encoding: [0x23,0x82,0x0c,0xd5] +//CHECK-NEXT: tlbi rvale2is, x3 // encoding: [0xa3,0x82,0x0c,0xd5] +//CHECK-NEXT: tlbi rvae2os, x3 // encoding: [0x23,0x85,0x0c,0xd5] +//CHECK-NEXT: tlbi rvale2os, x3 // encoding: [0xa3,0x85,0x0c,0xd5] +//CHECK-NEXT: tlbi rvae3, x3 // encoding: [0x23,0x86,0x0e,0xd5] +//CHECK-NEXT: tlbi rvale3, x3 // encoding: [0xa3,0x86,0x0e,0xd5] +//CHECK-NEXT: tlbi rvae3is, x3 // encoding: [0x23,0x82,0x0e,0xd5] +//CHECK-NEXT: tlbi rvale3is, x3 // encoding: [0xa3,0x82,0x0e,0xd5] +//CHECK-NEXT: tlbi rvae3os, x3 // encoding: [0x23,0x85,0x0e,0xd5] +//CHECK-NEXT: tlbi rvale3os, x3 // encoding: [0xa3,0x85,0x0e,0xd5] +//CHECK-NEXT: tlbi rvale3os, xzr // encoding: [0xbf,0x85,0x0e,0xd5] + +tlbi rvae1, sp + +//CHECK-ERROR: error: invalid operand for instruction +//CHECK-ERROR-NEXT: tlbi rvae1, sp +//CHECK-ERROR-NEXT: ^ + +//CHECK-NO-V84: error: TLBI RVAE1 requires ARMv8.4a +//CHECK-NO-V84-NEXT: tlbi rvae1, x3 +//CHECK-NO-V84-NEXT: ^ +//CHECK-NO-V84-NEXT: error: TLBI RVAAE1 requires ARMv8.4a +//CHECK-NO-V84-NEXT: tlbi rvaae1, x3 +//CHECK-NO-V84-NEXT: ^ +//CHECK-NO-V84-NEXT: error: TLBI RVALE1 requires ARMv8.4a +//CHECK-NO-V84-NEXT: tlbi rvale1, x3 +//CHECK-NO-V84-NEXT: ^ +//CHECK-NO-V84-NEXT: error: TLBI RVAALE1 requires ARMv8.4a +//CHECK-NO-V84-NEXT: tlbi rvaale1, x3 +//CHECK-NO-V84-NEXT: ^ +//CHECK-NO-V84-NEXT: error: TLBI RVAE1IS requires ARMv8.4a +//CHECK-NO-V84-NEXT: tlbi rvae1is, x3 +//CHECK-NO-V84-NEXT: ^ +//CHECK-NO-V84-NEXT: error: TLBI RVAAE1IS requires ARMv8.4a +//CHECK-NO-V84-NEXT: tlbi rvaae1is, x3 +//CHECK-NO-V84-NEXT: ^ +//CHECK-NO-V84-NEXT: error: TLBI RVALE1IS requires ARMv8.4a +//CHECK-NO-V84-NEXT: tlbi rvale1is, x3 +//CHECK-NO-V84-NEXT: ^ +//CHECK-NO-V84-NEXT: error: TLBI RVAALE1IS requires ARMv8.4a +//CHECK-NO-V84-NEXT: tlbi rvaale1is, x3 +//CHECK-NO-V84-NEXT: ^ +//CHECK-NO-V84-NEXT: error: TLBI RVAE1OS requires ARMv8.4a +//CHECK-NO-V84-NEXT: tlbi rvae1os, x3 +//CHECK-NO-V84-NEXT: ^ +//CHECK-NO-V84-NEXT: error: TLBI RVAAE1OS requires ARMv8.4a +//CHECK-NO-V84-NEXT: tlbi rvaae1os, x3 +//CHECK-NO-V84-NEXT: ^ +//CHECK-NO-V84-NEXT: error: TLBI RVALE1OS requires ARMv8.4a +//CHECK-NO-V84-NEXT: tlbi rvale1os, x3 +//CHECK-NO-V84-NEXT: ^ +//CHECK-NO-V84-NEXT: error: TLBI RVAALE1OS requires ARMv8.4a +//CHECK-NO-V84-NEXT: tlbi rvaale1os, x3 +//CHECK-NO-V84-NEXT: ^ +//CHECK-NO-V84-NEXT: error: TLBI RIPAS2E1IS requires ARMv8.4a +//CHECK-NO-V84-NEXT: tlbi ripas2e1is, x3 +//CHECK-NO-V84-NEXT: ^ +//CHECK-NO-V84-NEXT: error: TLBI RIPAS2LE1IS requires ARMv8.4a +//CHECK-NO-V84-NEXT: tlbi ripas2le1is, x3 +//CHECK-NO-V84-NEXT: ^ +//CHECK-NO-V84-NEXT: error: TLBI RIPAS2E1 requires ARMv8.4a +//CHECK-NO-V84-NEXT: tlbi ripas2e1, X3 +//CHECK-NO-V84-NEXT: ^ +//CHECK-NO-V84-NEXT: error: TLBI RIPAS2LE1 requires ARMv8.4a +//CHECK-NO-V84-NEXT: tlbi ripas2le1, X3 +//CHECK-NO-V84-NEXT: ^ +//CHECK-NO-V84-NEXT: error: TLBI RIPAS2E1OS requires ARMv8.4a +//CHECK-NO-V84-NEXT: tlbi ripas2e1os, X3 +//CHECK-NO-V84-NEXT: ^ +//CHECK-NO-V84-NEXT: error: TLBI RIPAS2LE1OS requires ARMv8.4a +//CHECK-NO-V84-NEXT: tlbi ripas2le1os, X3 +//CHECK-NO-V84-NEXT: ^ +//CHECK-NO-V84-NEXT: error: TLBI RVAE2 requires ARMv8.4a +//CHECK-NO-V84-NEXT: tlbi rvae2, X3 +//CHECK-NO-V84-NEXT: ^ +//CHECK-NO-V84-NEXT: error: TLBI RVALE2 requires ARMv8.4a +//CHECK-NO-V84-NEXT: tlbi rvale2, X3 +//CHECK-NO-V84-NEXT: ^ +//CHECK-NO-V84-NEXT: error: TLBI RVAE2IS requires ARMv8.4a +//CHECK-NO-V84-NEXT: tlbi rvae2is, X3 +//CHECK-NO-V84-NEXT: ^ +//CHECK-NO-V84-NEXT: error: TLBI RVALE2IS requires ARMv8.4a +//CHECK-NO-V84-NEXT: tlbi rvale2is, X3 +//CHECK-NO-V84-NEXT: ^ +//CHECK-NO-V84-NEXT: error: TLBI RVAE2OS requires ARMv8.4a +//CHECK-NO-V84-NEXT: tlbi rvae2os, X3 +//CHECK-NO-V84-NEXT: ^ +//CHECK-NO-V84-NEXT: error: TLBI RVALE2OS requires ARMv8.4a +//CHECK-NO-V84-NEXT: tlbi rvale2os, X3 +//CHECK-NO-V84-NEXT: ^ +//CHECK-NO-V84-NEXT: error: TLBI RVAE3 requires ARMv8.4a +//CHECK-NO-V84-NEXT: tlbi rvae3, X3 +//CHECK-NO-V84-NEXT: ^ +//CHECK-NO-V84-NEXT: error: TLBI RVALE3 requires ARMv8.4a +//CHECK-NO-V84-NEXT: tlbi rvale3, X3 +//CHECK-NO-V84-NEXT: ^ +//CHECK-NO-V84-NEXT: error: TLBI RVAE3IS requires ARMv8.4a +//CHECK-NO-V84-NEXT: tlbi rvae3is, X3 +//CHECK-NO-V84-NEXT: ^ +//CHECK-NO-V84-NEXT: error: TLBI RVALE3IS requires ARMv8.4a +//CHECK-NO-V84-NEXT: tlbi rvale3is, X3 +//CHECK-NO-V84-NEXT: ^ +//CHECK-NO-V84-NEXT: error: TLBI RVAE3OS requires ARMv8.4a +//CHECK-NO-V84-NEXT: tlbi rvae3os, X3 +//CHECK-NO-V84-NEXT: ^ +//CHECK-NO-V84-NEXT: error: TLBI RVALE3OS requires ARMv8.4a +//CHECK-NO-V84-NEXT: tlbi rvale3os, X3 +//CHECK-NO-V84-NEXT: ^ +//CHECK-NO-V84-NEXT: error: TLBI RVALE3OS requires ARMv8.4a +//CHECK-NO-V84-NEXT: tlbi rvale3os, XZR +//CHECK-NO-V84-NEXT: ^ Index: test/MC/Disassembler/AArch64/armv8.4a-tlb.txt =================================================================== --- /dev/null +++ test/MC/Disassembler/AArch64/armv8.4a-tlb.txt @@ -0,0 +1,151 @@ +# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.4a --disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=-v8.4a --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NOV84 + +# Outer shareable TLB Maintenance instructions: + +0x1f,0x81,0x08,0xd5 +0x20,0x81,0x08,0xd5 +0x40,0x81,0x08,0xd5 +0x60,0x81,0x08,0xd5 +0xa0,0x81,0x08,0xd5 +0xe0,0x81,0x08,0xd5 +0x00,0x84,0x0c,0xd5 +0x80,0x84,0x0c,0xd5 +0x20,0x81,0x0c,0xd5 +0xa0,0x81,0x0c,0xd5 +0xdf,0x81,0x0c,0xd5 +0x20,0x81,0x0e,0xd5 +0xa0,0x81,0x0e,0xd5 +0x1f,0x81,0x0c,0xd5 +0x9f,0x81,0x0c,0xd5 +0x1f,0x81,0x0e,0xd5 + +#CHECK: tlbi vmalle1os +#CHECK: tlbi vae1os, x0 +#CHECK: tlbi aside1os, x0 +#CHECK: tlbi vaae1os, x0 +#CHECK: tlbi vale1os, x0 +#CHECK: tlbi vaale1os, x0 +#CHECK: tlbi ipas2e1os, x0 +#CHECK: tlbi ipas2le1os, x0 +#CHECK: tlbi vae2os, x0 +#CHECK: tlbi vale2os, x0 +#CHECK: tlbi vmalls12e1os +#CHECK: tlbi vae3os, x0 +#CHECK: tlbi vale3os, x0 +#CHECK: tlbi alle2os +#CHECK: tlbi alle1os +#CHECK: tlbi alle3os + +#CHECK-NOV84: sys #0, c8, c1, #0 +#CHECK-NOV84: sys #0, c8, c1, #1, x0 +#CHECK-NOV84: sys #0, c8, c1, #2, x0 +#CHECK-NOV84: sys #0, c8, c1, #3, x0 +#CHECK-NOV84: sys #0, c8, c1, #5, x0 +#CHECK-NOV84: sys #0, c8, c1, #7, x0 +#CHECK-NOV84: sys #4, c8, c4, #0, x0 +#CHECK-NOV84: sys #4, c8, c4, #4, x0 +#CHECK-NOV84: sys #4, c8, c1, #1, x0 +#CHECK-NOV84: sys #4, c8, c1, #5, x0 +#CHECK-NOV84: sys #4, c8, c1, #6 +#CHECK-NOV84: sys #6, c8, c1, #1, x0 +#CHECK-NOV84: sys #6, c8, c1, #5, x0 +#CHECK-NOV84: sys #4, c8, c1, #0 +#CHECK-NOV84: sys #4, c8, c1, #4 +#CHECK-NOV84: sys #6, c8, c1, #0 +#CHECK-NOV84: sys #0, c8, c6, #1, x3 + +# TLB range maintenance instructions: + +0x23,0x86,0x08,0xd5 +0x63,0x86,0x08,0xd5 +0xa3,0x86,0x08,0xd5 +0xe3,0x86,0x08,0xd5 +0x23,0x82,0x08,0xd5 +0x63,0x82,0x08,0xd5 +0xa3,0x82,0x08,0xd5 +0xe3,0x82,0x08,0xd5 +0x23,0x85,0x08,0xd5 +0x63,0x85,0x08,0xd5 +0xa3,0x85,0x08,0xd5 +0xe3,0x85,0x08,0xd5 +0x43,0x80,0x0c,0xd5 +0xc3,0x80,0x0c,0xd5 +0x43,0x84,0x0c,0xd5 +0xc3,0x84,0x0c,0xd5 +0x63,0x84,0x0c,0xd5 +0xe3,0x84,0x0c,0xd5 +0x23,0x86,0x0c,0xd5 +0xa3,0x86,0x0c,0xd5 +0x23,0x82,0x0c,0xd5 +0xa3,0x82,0x0c,0xd5 +0x23,0x85,0x0c,0xd5 +0xa3,0x85,0x0c,0xd5 +0x23,0x86,0x0e,0xd5 +0xa3,0x86,0x0e,0xd5 +0x23,0x82,0x0e,0xd5 +0xa3,0x82,0x0e,0xd5 +0x23,0x85,0x0e,0xd5 +0xa3,0x85,0x0e,0xd5 + +#CHECK: tlbi rvae1, x3 +#CHECK: tlbi rvaae1, x3 +#CHECK: tlbi rvale1, x3 +#CHECK: tlbi rvaale1, x3 +#CHECK: tlbi rvae1is, x3 +#CHECK: tlbi rvaae1is, x3 +#CHECK: tlbi rvale1is, x3 +#CHECK: tlbi rvaale1is, x3 +#CHECK: tlbi rvae1os, x3 +#CHECK: tlbi rvaae1os, x3 +#CHECK: tlbi rvale1os, x3 +#CHECK: tlbi rvaale1os, x3 +#CHECK: tlbi ripas2e1is, x3 +#CHECK: tlbi ripas2le1is, x3 +#CHECK: tlbi ripas2e1, x3 +#CHECK: tlbi ripas2le1, x3 +#CHECK: tlbi ripas2e1os, x3 +#CHECK: tlbi ripas2le1os, x3 +#CHECK: tlbi rvae2, x3 +#CHECK: tlbi rvale2, x3 +#CHECK: tlbi rvae2is, x3 +#CHECK: tlbi rvale2is, x3 +#CHECK: tlbi rvae2os, x3 +#CHECK: tlbi rvale2os, x3 +#CHECK: tlbi rvae3, x3 +#CHECK: tlbi rvale3, x3 +#CHECK: tlbi rvae3is, x3 +#CHECK: tlbi rvale3is, x3 +#CHECK: tlbi rvae3os, x3 +#CHECK: tlbi rvale3os, x3 + +#CHECK-NOV84: sys #0, c8, c6, #3, x3 +#CHECK-NOV84: sys #0, c8, c6, #5, x3 +#CHECK-NOV84: sys #0, c8, c6, #7, x3 +#CHECK-NOV84: sys #0, c8, c2, #1, x3 +#CHECK-NOV84: sys #0, c8, c2, #3, x3 +#CHECK-NOV84: sys #0, c8, c2, #5, x3 +#CHECK-NOV84: sys #0, c8, c2, #7, x3 +#CHECK-NOV84: sys #0, c8, c5, #1, x3 +#CHECK-NOV84: sys #0, c8, c5, #3, x3 +#CHECK-NOV84: sys #0, c8, c5, #5, x3 +#CHECK-NOV84: sys #0, c8, c5, #7, x3 +#CHECK-NOV84: sys #4, c8, c0, #2, x3 +#CHECK-NOV84: sys #4, c8, c0, #6, x3 +#CHECK-NOV84: sys #4, c8, c4, #2, x3 +#CHECK-NOV84: sys #4, c8, c4, #6, x3 +#CHECK-NOV84: sys #4, c8, c4, #3, x3 +#CHECK-NOV84: sys #4, c8, c4, #7, x3 +#CHECK-NOV84: sys #4, c8, c6, #1, x3 +#CHECK-NOV84: sys #4, c8, c6, #5, x3 +#CHECK-NOV84: sys #4, c8, c2, #1, x3 +#CHECK-NOV84: sys #4, c8, c2, #5, x3 +#CHECK-NOV84: sys #4, c8, c5, #1, x3 +#CHECK-NOV84: sys #4, c8, c5, #5, x3 +#CHECK-NOV84: sys #6, c8, c6, #1, x3 +#CHECK-NOV84: sys #6, c8, c6, #5, x3 +#CHECK-NOV84: sys #6, c8, c2, #1, x3 +#CHECK-NOV84: sys #6, c8, c2, #5, x3 +#CHECK-NOV84: sys #6, c8, c5, #1, x3 +#CHECK-NOV84: sys #6, c8, c5, #5, x3 +