Index: lib/Target/ARM/ARMISelLowering.cpp
===================================================================
--- lib/Target/ARM/ARMISelLowering.cpp
+++ lib/Target/ARM/ARMISelLowering.cpp
@@ -3857,8 +3857,8 @@
                                      const SDLoc &dl) const {
   if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
     unsigned C = RHSC->getZExtValue();
-    if (!isLegalICmpImmediate(C)) {
-      // Constant does not fit, try adjusting it by one?
+    if (!isLegalICmpImmediate((int32_t)C)) {
+      // Constant does not fit, try adjusting it by one.
       switch (CC) {
       default: break;
       case ISD::SETLT:
@@ -13195,9 +13195,11 @@
 bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
   // Thumb2 and ARM modes can use cmn for negative immediates.
   if (!Subtarget->isThumb())
-    return ARM_AM::getSOImmVal(std::abs(Imm)) != -1;
+    return ARM_AM::getSOImmVal((uint32_t)Imm) != -1 ||
+           ARM_AM::getSOImmVal(-(uint32_t)Imm) != -1;
   if (Subtarget->isThumb2())
-    return ARM_AM::getT2SOImmVal(std::abs(Imm)) != -1;
+    return ARM_AM::getT2SOImmVal((uint32_t)Imm) != -1 ||
+           ARM_AM::getT2SOImmVal(-(uint32_t)Imm) != -1;
   // Thumb1 doesn't have cmn, and only 8-bit immediates.
   return Imm >= 0 && Imm <= 255;
 }
Index: test/CodeGen/ARM/arm-shrink-wrapping-linux.ll
===================================================================
--- test/CodeGen/ARM/arm-shrink-wrapping-linux.ll
+++ test/CodeGen/ARM/arm-shrink-wrapping-linux.ll
@@ -19,13 +19,13 @@
 ; without shrink-wrapping.
 ; DISABLE: push
 ;
-; CHECK: cmp r1, #0
+; CHECK: cmn r1, #1
 ;
 ; With shrink-wrapping, we branch to a pre-header, where the prologue
 ; is located.
-; ENABLE-NEXT: blt [[LOOP_PREHEADER:[.a-zA-Z0-9_]+]]
+; ENABLE-NEXT: ble [[LOOP_PREHEADER:[.a-zA-Z0-9_]+]]
 ; Without shrink-wrapping, we go straight into the loop.
-; DISABLE-NEXT: blt [[LOOP_HEADER:[.a-zA-Z0-9_]+]]
+; DISABLE-NEXT: ble [[LOOP_HEADER:[.a-zA-Z0-9_]+]]
 ;
 ; CHECK: @ %if.end29
 ; DISABLE-NEXT: pop
Index: test/CodeGen/ARM/sub-cmp-peephole.ll
===================================================================
--- test/CodeGen/ARM/sub-cmp-peephole.ll
+++ test/CodeGen/ARM/sub-cmp-peephole.ll
@@ -167,8 +167,8 @@
 entry:
 ; CHECK-LABEL: cmp_slt0
 ; CHECK: sub
-; CHECK: cmp
-; CHECK: bge
+; CHECK: cmn
+; CHECK: bgt
   %load = load i32, i32* @t, align 4
   %sub = sub i32 %load, 17
   %cmp = icmp slt i32 %sub, 0
Index: test/CodeGen/Thumb2/thumb2-cmp.ll
===================================================================
--- test/CodeGen/Thumb2/thumb2-cmp.ll
+++ test/CodeGen/Thumb2/thumb2-cmp.ll
@@ -169,7 +169,7 @@
 
 define i32 @slt_neg_soimm(i32 %a) {
 ; CHECK-LABEL: slt_neg_soimm:
-; CHECK: mvn     r1, #7929856
+; CHECK: cmn.w r0, #7929856
   %b = icmp slt i32 %a, -7929856
   br i1 %b, label %true, label %false
 
@@ -208,8 +208,7 @@
 
 define i32 @sgt_neg_soimm(i32 %a) {
 ; CHECK-LABEL: sgt_neg_soimm:
-; CHECK: movs    r1, #1
-; CHECK: movt    r1, #65415
+; CHECK: cmn.w r0, #7929856
   %b = icmp sgt i32 %a, -7929856
   br i1 %b, label %true, label %false