Index: lib/Analysis/InstructionSimplify.cpp =================================================================== --- lib/Analysis/InstructionSimplify.cpp +++ lib/Analysis/InstructionSimplify.cpp @@ -1283,6 +1283,19 @@ if (match(Op0, m_NUWShl(m_Value(X), m_Specific(Op1)))) return X; + // ((X << A) | Y) >> A -> X if effective width of Y is not larger than A. + // We can return X as we do in the above case since OR alters no bits in X. + Value *Y; + if (isa(Op1) && + match(Op0, m_c_Or(m_NUWShl(m_Value(X), m_Specific(Op1)), m_Value(Y)))) { + const KnownBits YKnown = computeKnownBits(Y, Q.DL, 0, Q.AC, Q.CxtI, Q.DT); + const unsigned ShiftCnt = cast(Op1)->getZExtValue(); + const unsigned Width = Op0->getType()->getScalarSizeInBits(); + const unsigned EffWidthY = Width - YKnown.countMinLeadingZeros(); + if (EffWidthY <= ShiftCnt) + return X; + } + return nullptr; } @@ -1804,6 +1817,41 @@ MaxRecurse)) return V; + // Assuming the effective width of Y is not larger than A, i.e. all bits + // from X and Y are disjoint in (X << A) | Y, + // if the mask of this AND op covers all bits of X or Y, while it covers + // no bits from the other, we can bypass this AND op. E.g., + // ((X << A) | Y) & Mask -> Y, + // if Mask = ((1 << effective_width_of(Y)) - 1) + // ((X << A) | Y) & Mask -> X << A, + // if Mask = ((1 << effective_width_of(X)) - 1) << A + Value *Y; + if (isa(Op1) && + match(Op0, m_c_Or(m_NUWShl(m_Value(X), m_APInt(ShAmt)), m_Value(Y)))) { + const APInt Mask = cast(Op1)->getValue(); + const unsigned ShiftCnt = ShAmt->getZExtValue(); + const KnownBits YKnown = computeKnownBits(Y, Q.DL, 0, Q.AC, Q.CxtI, Q.DT); + const unsigned Width = Op0->getType()->getScalarSizeInBits(); + const unsigned EffWidthY = Width - YKnown.countMinLeadingZeros(); + if (EffWidthY <= ShiftCnt) { + const KnownBits XKnown = computeKnownBits(X, Q.DL, 0, Q.AC, Q.CxtI, + Q.DT); + const unsigned EffWidthX = Width - XKnown.countMinLeadingZeros(); + const APInt EffBitsY = (APInt(Width, 1) << EffWidthY) - 1; + const APInt EffBitsX = ((APInt(Width, 1) << EffWidthX) - 1) << ShiftCnt; + // If the mask is extracting all bits from X or Y as is, we can skip + // this AND op. + if ((Mask & EffBitsY) == EffBitsY && (Mask & EffBitsX) == 0) + return Y; + if ((Mask & EffBitsX) == EffBitsX && (Mask & EffBitsY) == 0) { + if (cast(Op0)->getOperand(0) == Y) + return cast(Op0)->getOperand(1); + else + return cast(Op0)->getOperand(0); + } + } + } + return nullptr; } Index: test/Transforms/InstSimplify/AndOrXor.ll =================================================================== --- test/Transforms/InstSimplify/AndOrXor.ll +++ test/Transforms/InstSimplify/AndOrXor.ll @@ -964,3 +964,128 @@ %or = or i32 %a, %nega ret i32 %or } + +define i64 @shl_or_and1(i32 %a, i1 %b) { +; CHECK-LABEL: @shl_or_and1( +; CHECK-NEXT: [[TMP1:%.*]] = zext i1 [[B:%.*]] to i64 +; CHECK-NEXT: ret i64 [[TMP1]] +; + %1 = zext i32 %a to i64 + %2 = zext i1 %b to i64 + %3 = shl nuw i64 %1, 32 + %4 = or i64 %2, %3 + %5 = and i64 %4, 1 + ret i64 %5 +} + +define i64 @shl_or_and2(i32 %a, i1 %b) { +; CHECK-LABEL: @shl_or_and2( +; CHECK-NEXT: [[TMP1:%.*]] = zext i1 [[B:%.*]] to i64 +; CHECK-NEXT: [[TMP2:%.*]] = shl nuw i64 [[TMP1]], 32 +; CHECK-NEXT: ret i64 [[TMP2]] +; + %1 = zext i1 %b to i64 + %2 = zext i32 %a to i64 + %3 = shl nuw i64 %1, 32 + %4 = or i64 %2, %3 + %5 = and i64 %4, 4294967296 + ret i64 %5 +} + +define i32 @shl_or_and3(i32 %a, i32 %b) { +; concatinate two 32-bit integers and extract lower 32-bit +; CHECK-LABEL: @shl_or_and3( +; CHECK-NEXT: ret i32 [[B:%.*]] +; + %1 = zext i32 %a to i64 + %2 = zext i32 %b to i64 + %3 = shl nuw i64 %1, 32 + %4 = or i64 %2, %3 + %5 = and i64 %4, 4294967295 + %6 = trunc i64 %5 to i32 + ret i32 %6 +} + +define i32 @shl_or_and4(i16 %a, i16 %b) { +; concatinate two 16-bit integers and extract higher 16-bit +; CHECK-LABEL: @shl_or_and4( +; CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32 +; CHECK-NEXT: [[TMP2:%.*]] = shl nuw i32 [[TMP1]], 16 +; CHECK-NEXT: ret i32 [[TMP2]] +; + %1 = zext i16 %a to i32 + %2 = zext i16 %b to i32 + %3 = shl nuw i32 %1, 16 + %4 = or i32 %2, %3 + %5 = and i32 %4, 4294901760 ; mask with 0xFFFF0000 + ret i32 %5 +} + +define i32 @shl_or_and5(i16 %a, i16 %b) { +; A variation of above test case, but fails due to the mask value +; CHECK-LABEL: @shl_or_and5( +; CHECK-DAG: [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32 +; CHECK-DAG: [[TMP2:%.*]] = zext i16 [[B:%.*]] to i32 +; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i32 [[TMP1]], 16 +; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[TMP2]], [[TMP3]] +; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP4]], -65535 +; CHECK-NEXT: ret i32 [[TMP5]] +; + %1 = zext i16 %a to i32 + %2 = zext i16 %b to i32 + %3 = shl nuw i32 %1, 16 + %4 = or i32 %2, %3 + %5 = and i32 %4, 4294901761 ; mask with 0xFFFF0001 + ret i32 %5 +} + +define i32 @shl_or_and6(i16 %a, i16 %b) { +; A variation of above test case, but fails due to the mask value +; CHECK-LABEL: @shl_or_and6( +; CHECK-DAG: [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32 +; CHECK-DAG: [[TMP2:%.*]] = zext i16 [[B:%.*]] to i32 +; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i32 [[TMP1]], 16 +; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[TMP2]], [[TMP3]] +; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP4]], -131072 +; CHECK-NEXT: ret i32 [[TMP5]] +; + %1 = zext i16 %a to i32 + %2 = zext i16 %b to i32 + %3 = shl nuw i32 %1, 16 + %4 = or i32 %2, %3 + %5 = and i32 %4, 4294836224 ; mask with 0xFFFE0000 + ret i32 %5 +} + +define i32 @shl_or_and7(i16 %a, i16 %b) { +; A variation of above test case, but fails due to the mask value +; CHECK-LABEL: @shl_or_and7( +; CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32 +; CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[B:%.*]] to i32 +; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i32 [[TMP1]], 16 +; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[TMP2]], [[TMP3]] +; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP4]], 131071 +; CHECK-NEXT: ret i32 [[TMP5]] +; + %1 = zext i16 %a to i32 + %2 = zext i16 %b to i32 + %3 = shl nuw i32 %1, 16 + %4 = or i32 %2, %3 + %5 = and i32 %4, 131071 ; mask with 0x1FFFF + ret i32 %5 +} + +define i64 @shl_or_and8(i64 %a, i1 %b) { +; CHECK-LABEL: @shl_or_and8( +; CHECK-NEXT: [[TMP1:%.*]] = zext i1 [[B:%.*]] to i128 +; CHECK-NEXT: [[TMP2:%.*]] = trunc i128 [[TMP1]] to i64 +; CHECK-NEXT: ret i64 [[TMP2]] +; + %1 = zext i64 %a to i128 + %2 = zext i1 %b to i128 + %3 = shl nuw i128 %1, 64 + %4 = or i128 %2, %3 + %5 = and i128 %4, 1 + %6 = trunc i128 %5 to i64 + ret i64 %6 +} Index: test/Transforms/InstSimplify/shift.ll =================================================================== --- test/Transforms/InstSimplify/shift.ll +++ test/Transforms/InstSimplify/shift.ll @@ -175,3 +175,35 @@ ret <2 x i8> %r } +define i32 @shl_or_shr(i32 %a, i32 %b) { +; CHECK-LABEL: @shl_or_shr( +; CHECK-NEXT: ret i32 [[A:%.*]] +; + %1 = zext i32 %a to i64 + %2 = zext i32 %b to i64 + %3 = shl nuw i64 %1, 32 + %4 = or i64 %2, %3 + %5 = lshr i64 %4, 32 + %6 = trunc i64 %5 to i32 + ret i32 %6 +} + +define i32 @shl_or_shr2(i32 %a, i32 %b) { +; Since shift count of shl is smaller than the size of %b, OR cannot be eliminated. +; CHECK-LABEL: @shl_or_shr2( +; CHECK-DAG: [[TMP1:%.*]] = zext i32 [[A:%.*]] to i64 +; CHECK-DAG: [[TMP2:%.*]] = zext i32 [[B:%.*]] to i64 +; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i64 [[TMP1]], 31 +; CHECK-NEXT: [[TMP4:%.*]] = or i64 [[TMP2]], [[TMP3]] +; CHECK-NEXT: [[TMP5:%.*]] = lshr i64 [[TMP4]], 31 +; CHECK-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i32 +; CHECK-NEXT: ret i32 [[TMP6]] +; + %1 = zext i32 %a to i64 + %2 = zext i32 %b to i64 + %3 = shl nuw i64 %1, 31 + %4 = or i64 %2, %3 + %5 = lshr i64 %4, 31 + %6 = trunc i64 %5 to i32 + ret i32 %6 +} Index: test/Transforms/NewGVN/pair_jumpthread.ll =================================================================== --- /dev/null +++ test/Transforms/NewGVN/pair_jumpthread.ll @@ -0,0 +1,120 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt < %s -newgvn -S | FileCheck %s +; RUN: opt < %s -newgvn -jump-threading -S | FileCheck --check-prefix=CHECK-JT %s + +define signext i32 @testBI(i32 signext %v) { +; Test with std::pair +; based on the following C++ code +; std::pair callee(int v) { +; int a = dummy(v); +; if (a) return std::make_pair(true, dummy(a)); +; else return std::make_pair(v < 0, v); +; } +; int func(int v) { +; std::pair rc = callee(v); +; if (rc.first) dummy(0); +; return rc.second; +; } +; CHECK-LABEL: @testBI( +; CHECK: _ZL6calleei.exit: +; CHECK: [[PHIOFOPS:%.*]] = phi i64 [ 1, %if.then.i ], [ {{%.*}}, %if.else.i ] +; CHECK: [[TOBOOL:%.*]] = icmp eq i64 [[PHIOFOPS]], 0 +; +; CHECK-JT-LABEL: @testBI( +; CHECK-JT: _ZL6calleei.exit.thread: +; + +entry: + %call.i = call signext i32 @dummy(i32 signext %v) + %tobool.i = icmp eq i32 %call.i, 0 + br i1 %tobool.i, label %if.else.i, label %if.then.i + +if.then.i: ; preds = %entry + %call2.i = call signext i32 @dummy(i32 signext %call.i) + %retval.sroa.22.0.insert.ext.i.i = zext i32 %call2.i to i64 + %retval.sroa.22.0.insert.shift.i.i = shl nuw i64 %retval.sroa.22.0.insert.ext.i.i, 32 + %retval.sroa.0.0.insert.insert.i.i = or i64 %retval.sroa.22.0.insert.shift.i.i, 1 + br label %_ZL6calleei.exit + +if.else.i: ; preds = %entry + %.lobit.i = lshr i32 %v, 31 + %0 = zext i32 %.lobit.i to i64 + %retval.sroa.22.0.insert.ext.i8.i = zext i32 %v to i64 + %retval.sroa.22.0.insert.shift.i9.i = shl nuw i64 %retval.sroa.22.0.insert.ext.i8.i, 32 + %retval.sroa.0.0.insert.insert.i11.i = or i64 %retval.sroa.22.0.insert.shift.i9.i, %0 + br label %_ZL6calleei.exit + +_ZL6calleei.exit: ; preds = %if.then.i, %if.else.i + %retval.sroa.0.0.i = phi i64 [ %retval.sroa.0.0.insert.insert.i.i, %if.then.i ], [ %retval.sroa.0.0.insert.insert.i11.i, %if.else.i ] + %rc.sroa.43.0.extract.shift = lshr i64 %retval.sroa.0.0.i, 32 + %rc.sroa.43.0.extract.trunc = trunc i64 %rc.sroa.43.0.extract.shift to i32 + %1 = and i64 %retval.sroa.0.0.i, 1 + %tobool = icmp eq i64 %1, 0 + br i1 %tobool, label %if.end, label %if.then + +if.then: ; preds = %_ZL6calleei.exit + %call1 = call signext i32 @dummy(i32 signext 0) + br label %if.end + +if.end: ; preds = %_ZL6calleei.exit, %if.then + ret i32 %rc.sroa.43.0.extract.trunc +} + + +define signext i32 @testIB(i32 signext %v) { +; Test with std::pair +; based on the following C++ code +; std::pair callee(int v) { +; int a = dummy(v); +; if (a) return std::make_pair(dummy(v), true); +; else return std::make_pair(v, v < 0); +; } +; int func(int v) { +; std::pair rc = callee(v); +; if (rc.second) dummy(0); +; return rc.first; +; } +; CHECK-LABEL: @testIB( +; CHECK: _ZL6calleei.exit: +; CHECK: [[PHIOFOPS:%.*]] = phi i64 [ 4294967296, %if.then.i ], [ {{%.*}}, %if.else.i ] +; CHECK: [[TOBOOL:%.*]] = icmp eq i64 [[PHIOFOPS]], 0 +; +; CHECK-JT-LABEL: @testIB( +; CHECK-JT: _ZL6calleei.exit.thread: +; + +entry: + %call.i = call signext i32 @dummy(i32 signext %v) + %tobool.i = icmp eq i32 %call.i, 0 + br i1 %tobool.i, label %if.else.i, label %if.then.i + +if.then.i: ; preds = %entry + %call1.i = call signext i32 @dummy(i32 signext %v) + %retval.sroa.0.0.insert.ext.i.i = zext i32 %call1.i to i64 + %retval.sroa.0.0.insert.insert.i.i = or i64 %retval.sroa.0.0.insert.ext.i.i, 4294967296 + br label %_ZL6calleei.exit + +if.else.i: ; preds = %entry + %.lobit.i = lshr i32 %v, 31 + %0 = zext i32 %.lobit.i to i64 + %retval.sroa.2.0.insert.shift.i8.i = shl nuw nsw i64 %0, 32 + %retval.sroa.0.0.insert.ext.i9.i = zext i32 %v to i64 + %retval.sroa.0.0.insert.insert.i10.i = or i64 %retval.sroa.2.0.insert.shift.i8.i, %retval.sroa.0.0.insert.ext.i9.i + br label %_ZL6calleei.exit + +_ZL6calleei.exit: ; preds = %if.then.i, %if.else.i + %retval.sroa.0.0.i = phi i64 [ %retval.sroa.0.0.insert.insert.i.i, %if.then.i ], [ %retval.sroa.0.0.insert.insert.i10.i, %if.else.i ] + %rc.sroa.0.0.extract.trunc = trunc i64 %retval.sroa.0.0.i to i32 + %1 = and i64 %retval.sroa.0.0.i, 4294967296 + %tobool = icmp eq i64 %1, 0 + br i1 %tobool, label %if.end, label %if.then + +if.then: ; preds = %_ZL6calleei.exit + %call1 = call signext i32 @dummy(i32 signext 0) + br label %if.end + +if.end: ; preds = %_ZL6calleei.exit, %if.then + ret i32 %rc.sroa.0.0.extract.trunc +} + +declare signext i32 @dummy(i32 signext %v)