Index: compiler-rt/trunk/cmake/config-ix.cmake =================================================================== --- compiler-rt/trunk/cmake/config-ix.cmake +++ compiler-rt/trunk/cmake/config-ix.cmake @@ -134,7 +134,7 @@ filter_available_targets(MSAN_SUPPORTED_ARCH x86_64) filter_available_targets(PROFILE_SUPPORTED_ARCH x86_64 i386 arm aarch64) filter_available_targets(TSAN_SUPPORTED_ARCH x86_64) -filter_available_targets(UBSAN_SUPPORTED_ARCH x86_64 i386 arm aarch64) +filter_available_targets(UBSAN_SUPPORTED_ARCH x86_64 i386 arm aarch64 mips) if(ANDROID) set(OS_NAME "Android") Index: compiler-rt/trunk/lib/sanitizer_common/sanitizer_stacktrace.cc =================================================================== --- compiler-rt/trunk/lib/sanitizer_common/sanitizer_stacktrace.cc +++ compiler-rt/trunk/lib/sanitizer_common/sanitizer_stacktrace.cc @@ -25,7 +25,7 @@ #if defined(__powerpc__) || defined(__powerpc64__) // PCs are always 4 byte aligned. return pc - 4; -#elif defined(__sparc__) +#elif defined(__sparc__) || defined(__mips__) return pc - 8; #else return pc - 1; Index: compiler-rt/trunk/test/ubsan/TestCases/Float/cast-overflow.cpp =================================================================== --- compiler-rt/trunk/test/ubsan/TestCases/Float/cast-overflow.cpp +++ compiler-rt/trunk/test/ubsan/TestCases/Float/cast-overflow.cpp @@ -14,6 +14,7 @@ // This test assumes float and double are IEEE-754 single- and double-precision. +#include #include #include #include @@ -41,12 +42,20 @@ unsigned Zero = NearlyMinusOne; // ok // Build a '+Inf'. +#if __BYTE_ORDER == __LITTLE_ENDIAN char InfVal[] = { 0x00, 0x00, 0x80, 0x7f }; +#else + char InfVal[] = { 0x7f, 0x80, 0x00, 0x00 }; +#endif float Inf; memcpy(&Inf, InfVal, 4); // Build a 'NaN'. +#if __BYTE_ORDER == __LITTLE_ENDIAN char NaNVal[] = { 0x01, 0x00, 0x80, 0x7f }; +#else + char NaNVal[] = { 0x7f, 0x80, 0x00, 0x01 }; +#endif float NaN; memcpy(&NaN, NaNVal, 4);