Index: lib/Target/AMDGPU/SIInstructions.td
===================================================================
--- lib/Target/AMDGPU/SIInstructions.td
+++ lib/Target/AMDGPU/SIInstructions.td
@@ -49,19 +49,19 @@
                                                (i32 imm:$attr)))]
 >;
 
-let OtherPredicates = [has32BankLDS] in {
+let OtherPredicates = [has32BankLDS], VALU=1 in {
 
 defm V_INTERP_P1_F32 : V_INTERP_P1_F32_m;
 
-} // End OtherPredicates = [has32BankLDS]
+} // End OtherPredicates = [has32BankLDS], VALU=1
 
-let OtherPredicates = [has16BankLDS], Constraints = "@earlyclobber $vdst", isAsmParserOnly=1 in {
+let OtherPredicates = [has16BankLDS], Constraints = "@earlyclobber $vdst", isAsmParserOnly=1, VALU=1 in {
 
 defm V_INTERP_P1_F32_16bank : V_INTERP_P1_F32_m;
 
-} // End OtherPredicates = [has32BankLDS], Constraints = "@earlyclobber $vdst", isAsmParserOnly=1
+} // End OtherPredicates = [has32BankLDS], Constraints = "@earlyclobber $vdst", isAsmParserOnly=1, VALU=1
 
-let DisableEncoding = "$src0", Constraints = "$src0 = $vdst" in {
+let DisableEncoding = "$src0", Constraints = "$src0 = $vdst", VALU=1 in {
 
 defm V_INTERP_P2_F32 : VINTRP_m <
   0x00000001,
@@ -71,8 +71,9 @@
   [(set f32:$vdst, (AMDGPUinterp_p2 f32:$src0, f32:$vsrc, (i32 imm:$attrchan),
                                                           (i32 imm:$attr)))]>;
 
-} // End DisableEncoding = "$src0", Constraints = "$src0 = $vdst"
+} // End DisableEncoding = "$src0", Constraints = "$src0 = $vdst", VALU=1
 
+let VALU=1 in {
 defm V_INTERP_MOV_F32 : VINTRP_m <
   0x00000002,
   (outs VINTRPDst:$vdst),
@@ -81,6 +82,8 @@
   [(set f32:$vdst, (AMDGPUinterp_mov (i32 imm:$vsrc), (i32 imm:$attrchan),
                                      (i32 imm:$attr)))]>;
 
+} // End VALU=1
+
 } // End Uses = [M0, EXEC]
 
 //===----------------------------------------------------------------------===//
Index: test/CodeGen/AMDGPU/hazard-buffer-store-v-interp.mir
===================================================================
--- /dev/null
+++ test/CodeGen/AMDGPU/hazard-buffer-store-v-interp.mir
@@ -0,0 +1,19 @@
+# RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=GCN -check-prefix=VI %s
+# RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s
+
+# GCN-LABEL: name: hazard_buffer_store_v_interp
+# GCN:    bb.0.entry:
+# GCN:    BUFFER_STORE_DWORDX4_OFFSET_exact
+# GCN:    S_NOP
+# GCN:    V_INTERP_P1_F32
+
+name:            hazard_buffer_store_v_interp
+body:             |
+  bb.0.entry:
+    liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr7, $vgpr8, $vgpr9, $vgpr10
+  
+    BUFFER_STORE_DWORDX4_OFFSET_exact killed $vgpr7_vgpr8_vgpr9_vgpr10, $sgpr4_sgpr5_sgpr6_sgpr7, 0, 96, 0, 0, 0, implicit $exec
+    $vgpr7 = V_INTERP_P1_F32 $vgpr0, 0, 0, implicit $m0, implicit $exec
+    S_ENDPGM
+
+...