Index: llvm/trunk/lib/Target/AArch64/AArch64SystemOperands.td =================================================================== --- llvm/trunk/lib/Target/AArch64/AArch64SystemOperands.td +++ llvm/trunk/lib/Target/AArch64/AArch64SystemOperands.td @@ -1118,6 +1118,28 @@ def : RWSysReg<"APGAKeyHi_EL1", 0b11, 0b000, 0b0010, 0b0011, 0b001>; } +let Requires = [{ {AArch64::HasV8_4aOps} }] in { + +// v8.4a "Virtualization secure second stage translation" registers +// Op0 Op1 CRn CRm Op2 +def : RWSysReg<"VSTCR_EL2" , 0b11, 0b100, 0b0010, 0b0110, 0b010>; +def : RWSysReg<"VSTTBR_EL2", 0b11, 0b100, 0b0010, 0b0110, 0b000>; + +// v8.4a "Virtualization timer" registers +// Op0 Op1 CRn CRm Op2 +def : RWSysReg<"CNTHVS_TVAL_EL2", 0b11, 0b100, 0b1110, 0b0100, 0b000>; +def : RWSysReg<"CNTHVS_CVAL_EL2", 0b11, 0b100, 0b1110, 0b0100, 0b010>; +def : RWSysReg<"CNTHVS_CTL_EL2", 0b11, 0b100, 0b1110, 0b0100, 0b001>; +def : RWSysReg<"CNTHPS_TVAL_EL2", 0b11, 0b100, 0b1110, 0b0101, 0b000>; +def : RWSysReg<"CNTHPS_CVAL_EL2", 0b11, 0b100, 0b1110, 0b0101, 0b010>; +def : RWSysReg<"CNTHPS_CTL_EL2", 0b11, 0b100, 0b1110, 0b0101, 0b001>; + +// v8.4a "Virtualization debug state" registers +// Op0 Op1 CRn CRm Op2 +def : RWSysReg<"SDER32_EL2", 0b11, 0b100, 0b0001, 0b0011, 0b001>; + +} // HasV8_4aOps + // Cyclone specific system registers // Op0 Op1 CRn CRm Op2 let Requires = [{ {AArch64::ProcCyclone} }] in Index: llvm/trunk/test/MC/AArch64/armv8.4a-virt.s =================================================================== --- llvm/trunk/test/MC/AArch64/armv8.4a-virt.s +++ llvm/trunk/test/MC/AArch64/armv8.4a-virt.s @@ -0,0 +1,36 @@ +// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.4a < %s | FileCheck %s +// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.4a < %s 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR + +//------------------------------------------------------------------------------ +// Virtualization Enhancements +//------------------------------------------------------------------------------ + + msr VSTCR_EL2, x0 + msr VSTTBR_EL2, x0 + msr SDER32_EL2, x12 + msr CNTHVS_TVAL_EL2, x0 + msr CNTHVS_CVAL_EL2, x0 + msr CNTHVS_CTL_EL2, x0 + msr CNTHPS_TVAL_EL2, x0 + msr CNTHPS_CVAL_EL2, x0 + msr CNTHPS_CTL_EL2, x0 + +//CHECK: msr VSTCR_EL2, x0 // encoding: [0x40,0x26,0x1c,0xd5] +//CHECK: msr VSTTBR_EL2, x0 // encoding: [0x00,0x26,0x1c,0xd5] +//CHECK: msr SDER32_EL2, x12 // encoding: [0x2c,0x13,0x1c,0xd5] +//CHECK: msr CNTHVS_TVAL_EL2, x0 // encoding: [0x00,0xe4,0x1c,0xd5] +//CHECK: msr CNTHVS_CVAL_EL2, x0 // encoding: [0x40,0xe4,0x1c,0xd5] +//CHECK: msr CNTHVS_CTL_EL2, x0 // encoding: [0x20,0xe4,0x1c,0xd5] +//CHECK: msr CNTHPS_TVAL_EL2, x0 // encoding: [0x00,0xe5,0x1c,0xd5] +//CHECK: msr CNTHPS_CVAL_EL2, x0 // encoding: [0x40,0xe5,0x1c,0xd5] +//CHECK: msr CNTHPS_CTL_EL2, x0 // encoding: [0x20,0xe5,0x1c,0xd5] + +//CHECK-ERROR: error: expected writable system register or pstate +//CHECK-ERROR: error: expected writable system register or pstate +//CHECK-ERROR: error: expected writable system register or pstate +//CHECK-ERROR: error: expected writable system register or pstate +//CHECK-ERROR: error: expected writable system register or pstate +//CHECK-ERROR: error: expected writable system register or pstate +//CHECK-ERROR: error: expected writable system register or pstate +//CHECK-ERROR: error: expected writable system register or pstate +//CHECK-ERROR: error: expected writable system register or pstate Index: llvm/trunk/test/MC/Disassembler/AArch64/armv8.4a-virt.txt =================================================================== --- llvm/trunk/test/MC/Disassembler/AArch64/armv8.4a-virt.txt +++ llvm/trunk/test/MC/Disassembler/AArch64/armv8.4a-virt.txt @@ -0,0 +1,39 @@ +# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.4a --disassemble < %s | FileCheck %s + +0x40,0x26,0x1c,0xd5 +0x40,0x26,0x3c,0xd5 +0x00,0x26,0x1c,0xd5 +0x00,0x26,0x3c,0xd5 +0x2c,0x13,0x1c,0xd5 +0x2c,0x13,0x3c,0xd5 +0x00,0xe4,0x1c,0xd5 +0x00,0xe4,0x3c,0xd5 +0x40,0xe4,0x1c,0xd5 +0x40,0xe4,0x3c,0xd5 +0x20,0xe4,0x1c,0xd5 +0x20,0xe4,0x3c,0xd5 +0x00,0xe5,0x1c,0xd5 +0x00,0xe5,0x3c,0xd5 +0x40,0xe5,0x1c,0xd5 +0x40,0xe5,0x3c,0xd5 +0x20,0xe5,0x1c,0xd5 +0x20,0xe5,0x3c,0xd5 + +#CHECK: msr VSTCR_EL2, x0 +#CHECK: mrs x0, VSTCR_EL2 +#CHECK: msr VSTTBR_EL2, x0 +#CHECK: mrs x0, VSTTBR_EL2 +#CHECK: msr SDER32_EL2, x12 +#CHECK: mrs x12, SDER32_EL2 +#CHECK: msr CNTHVS_TVAL_EL2, x0 +#CHECK: mrs x0, CNTHVS_TVAL_EL2 +#CHECK: msr CNTHVS_CVAL_EL2, x0 +#CHECK: mrs x0, CNTHVS_CVAL_EL2 +#CHECK: msr CNTHVS_CTL_EL2, x0 +#CHECK: mrs x0, CNTHVS_CTL_EL2 +#CHECK: msr CNTHPS_TVAL_EL2, x0 +#CHECK: mrs x0, CNTHPS_TVAL_EL2 +#CHECK: msr CNTHPS_CVAL_EL2, x0 +#CHECK: mrs x0, CNTHPS_CVAL_EL2 +#CHECK: msr CNTHPS_CTL_EL2, x0 +#CHECK: mrs x0, CNTHPS_CTL_EL2