Index: lib/Target/Sparc/Sparc.td =================================================================== --- lib/Target/Sparc/Sparc.td +++ lib/Target/Sparc/Sparc.td @@ -49,6 +49,9 @@ def FeatureLeon : SubtargetFeature<"leon", "IsLeon", "true", "Enable LEON extensions">; +def FeaturePWRPSR + : SubtargetFeature<"leonpwrpsr", "HasPWRPSR", "true", + "Enable the PWRPSR instruction">; def FeatureHardQuad : SubtargetFeature<"hard-quad-float", "HasHardQuad", "true", @@ -159,7 +162,7 @@ // LEON 4 FT (GR740) // TO DO: Place-holder: Processor specific features will be added *very* soon here. def : Processor<"gr740", LEON4Itineraries, - [FeatureLeon, UMACSMACSupport, LeonCASA]>; + [FeatureLeon, UMACSMACSupport, LeonCASA, FeaturePWRPSR]>; //===----------------------------------------------------------------------===// // Declare the target which we are implementing Index: lib/Target/Sparc/SparcInstrAliases.td =================================================================== --- lib/Target/Sparc/SparcInstrAliases.td +++ lib/Target/Sparc/SparcInstrAliases.td @@ -470,6 +470,8 @@ def : InstAlias<"wr $rs2, %tbr", (WRTBRrr G0, IntRegs:$rs2), 0>; def : InstAlias<"wr $simm13, %tbr", (WRTBRri G0, i32imm:$simm13), 0>; +def : InstAlias<"pwr $rs2, %psr", (PWRPSRrr G0, IntRegs:$rs2), 0>; +def : InstAlias<"pwr $simm13, %psr", (PWRPSRri G0, i32imm:$simm13), 0>; // flush -> flush %g0 def : InstAlias<"flush", (FLUSH), 0>; Index: lib/Target/Sparc/SparcInstrInfo.td =================================================================== --- lib/Target/Sparc/SparcInstrInfo.td +++ lib/Target/Sparc/SparcInstrInfo.td @@ -56,6 +56,11 @@ // instruction def HasLeonCASA : Predicate<"Subtarget->hasLeonCasa()">; +// HasPWRPSR - This is true when the target processor supports partial +// writes to the PSR register that only affects the ET field. +def HasPWRPSR : Predicate<"Subtarget->hasPWRPSR()">, + AssemblerPredicate<"FeaturePWRPSR">; + // HasUMAC_SMAC - This is true when the target processor supports the // UMAC and SMAC instructions def HasUMAC_SMAC : Predicate<"Subtarget->hasUmacSmac()">; @@ -1566,6 +1571,17 @@ [], IIC_smac_umac>; } +// The partial write WRPSR instruction has a non-zero destination +// register value to separate it from the standard instruction. +let Predicates = [HasPWRPSR], Defs = [PSR], rd=1 in { + def PWRPSRrr : F3_1<2, 0b110001, + (outs), (ins IntRegs:$rs1, IntRegs:$rs2), + "pwr $rs1, $rs2, %psr", []>; + def PWRPSRri : F3_2<2, 0b110001, + (outs), (ins IntRegs:$rs1, simm13Op:$simm13), + "pwr $rs1, $simm13, %psr", []>; +} + let Defs = [ICC] in { defm TADDCC : F3_12np<"taddcc", 0b100000>; defm TSUBCC : F3_12np<"tsubcc", 0b100001>; Index: lib/Target/Sparc/SparcSubtarget.h =================================================================== --- lib/Target/Sparc/SparcSubtarget.h +++ lib/Target/Sparc/SparcSubtarget.h @@ -47,6 +47,7 @@ // LEON features bool HasUmacSmac; bool HasLeonCasa; + bool HasPWRPSR; bool InsertNOPLoad; bool FixAllFDIVSQRT; bool DetectRoundChange; @@ -92,6 +93,7 @@ // Leon options bool hasUmacSmac() const { return HasUmacSmac; } bool hasLeonCasa() const { return HasLeonCasa; } + bool hasPWRPSR() const { return HasPWRPSR; } bool insertNOPLoad() const { return InsertNOPLoad; } bool fixAllFDIVSQRT() const { return FixAllFDIVSQRT; } bool detectRoundChange() const { return DetectRoundChange; } Index: lib/Target/Sparc/SparcSubtarget.cpp =================================================================== --- lib/Target/Sparc/SparcSubtarget.cpp +++ lib/Target/Sparc/SparcSubtarget.cpp @@ -44,6 +44,7 @@ // Leon features HasLeonCasa = false; HasUmacSmac = false; + HasPWRPSR = false; InsertNOPLoad = false; FixAllFDIVSQRT = false; DetectRoundChange = false; Index: test/MC/Sparc/leon-pwrpsr-instruction.s =================================================================== --- /dev/null +++ test/MC/Sparc/leon-pwrpsr-instruction.s @@ -0,0 +1,10 @@ +! RUN: llvm-mc %s -arch=sparc -mcpu=gr740 -show-encoding | FileCheck %s + + ! CHECK: pwr %g0, 0, %psr ! encoding: [0x83,0x88,0x20,0x00] + pwr 0, %psr + + ! CHECK: pwr %g0, %l7, %psr ! encoding: [0x83,0x88,0x00,0x17] + pwr %l7, %psr + + ! CHECK: pwr %g0, 32, %psr ! encoding: [0x83,0x88,0x20,0x20] + pwr 32, %psr