Index: llvm/trunk/include/llvm/ADT/Triple.h =================================================================== --- llvm/trunk/include/llvm/ADT/Triple.h +++ llvm/trunk/include/llvm/ADT/Triple.h @@ -101,6 +101,7 @@ enum SubArchType { NoSubArch, + ARMSubArch_v8_4a, ARMSubArch_v8_3a, ARMSubArch_v8_2a, ARMSubArch_v8_1a, Index: llvm/trunk/include/llvm/Support/AArch64TargetParser.def =================================================================== --- llvm/trunk/include/llvm/Support/AArch64TargetParser.def +++ llvm/trunk/include/llvm/Support/AArch64TargetParser.def @@ -35,6 +35,11 @@ (AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP | AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE | AArch64::AEK_RDM | AArch64::AEK_RCPC)) +AARCH64_ARCH("armv8.4-a", ARMV8_4A, "8.4-A", "v8.4a", + ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8, + (AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP | + AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE | + AArch64::AEK_RDM | AArch64::AEK_RCPC)) #undef AARCH64_ARCH #ifndef AARCH64_ARCH_EXT_NAME @@ -47,6 +52,10 @@ AARCH64_ARCH_EXT_NAME("lse", AArch64::AEK_LSE, "+lse", "-lse") AARCH64_ARCH_EXT_NAME("rdm", AArch64::AEK_RDM, "+rdm", "-rdm") AARCH64_ARCH_EXT_NAME("crypto", AArch64::AEK_CRYPTO, "+crypto","-crypto") +AARCH64_ARCH_EXT_NAME("sm4", AArch64::AEK_SM4, "+sm4", "-sm4") +AARCH64_ARCH_EXT_NAME("sha3", AArch64::AEK_SHA3, "+sha3", "-sha3") +AARCH64_ARCH_EXT_NAME("sha2", AArch64::AEK_SHA2, "+sha2", "-sha2") +AARCH64_ARCH_EXT_NAME("aes", AArch64::AEK_AES, "+aes", "-aes") AARCH64_ARCH_EXT_NAME("dotprod", AArch64::AEK_DOTPROD, "+dotprod","-dotprod") AARCH64_ARCH_EXT_NAME("fp", AArch64::AEK_FP, "+fp-armv8", "-fp-armv8") AARCH64_ARCH_EXT_NAME("simd", AArch64::AEK_SIMD, "+neon", "-neon") Index: llvm/trunk/include/llvm/Support/ARMTargetParser.def =================================================================== --- llvm/trunk/include/llvm/Support/ARMTargetParser.def +++ llvm/trunk/include/llvm/Support/ARMTargetParser.def @@ -101,6 +101,10 @@ ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8, (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS)) +ARM_ARCH("armv8.4-a", ARMV8_4A, "8.4-A", "v8.4a", + ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8, + (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | + ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS)) ARM_ARCH("armv8-r", ARMV8R, "8-R", "v8r", ARMBuildAttrs::CPUArch::v8_R, FK_NEON_FP_ARMV8, (ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | @@ -130,6 +134,8 @@ ARM_ARCH_EXT_NAME("none", ARM::AEK_NONE, nullptr, nullptr) ARM_ARCH_EXT_NAME("crc", ARM::AEK_CRC, "+crc", "-crc") ARM_ARCH_EXT_NAME("crypto", ARM::AEK_CRYPTO, "+crypto","-crypto") +ARM_ARCH_EXT_NAME("sha2", ARM::AEK_SHA2, "+sha2", "-sha2") +ARM_ARCH_EXT_NAME("aes", ARM::AEK_AES, "+aes", "-aes") ARM_ARCH_EXT_NAME("dotprod", ARM::AEK_DOTPROD, "+dotprod","-dotprod") ARM_ARCH_EXT_NAME("dsp", ARM::AEK_DSP, "+dsp", "-dsp") ARM_ARCH_EXT_NAME("fp", ARM::AEK_FP, nullptr, nullptr) Index: llvm/trunk/include/llvm/Support/TargetParser.h =================================================================== --- llvm/trunk/include/llvm/Support/TargetParser.h +++ llvm/trunk/include/llvm/Support/TargetParser.h @@ -86,6 +86,8 @@ AEK_RAS = 1 << 12, AEK_SVE = 1 << 13, AEK_DOTPROD = 1 << 14, + AEK_SHA2 = 1 << 15, + AEK_AES = 1 << 16, // Unsupported extensions. AEK_OS = 0x8000000, AEK_IWMMXT = 0x10000000, @@ -171,7 +173,11 @@ AEK_SVE = 1 << 9, AEK_DOTPROD = 1 << 10, AEK_RCPC = 1 << 11, - AEK_RDM = 1 << 12 + AEK_RDM = 1 << 12, + AEK_SM4 = 1 << 13, + AEK_SHA3 = 1 << 14, + AEK_SHA2 = 1 << 15, + AEK_AES = 1 << 16, }; StringRef getCanonicalArchName(StringRef Arch); Index: llvm/trunk/lib/Support/TargetParser.cpp =================================================================== --- llvm/trunk/lib/Support/TargetParser.cpp +++ llvm/trunk/lib/Support/TargetParser.cpp @@ -480,6 +480,8 @@ Features.push_back("+v8.2a"); if (AK == AArch64::ArchKind::ARMV8_3A) Features.push_back("+v8.3a"); + if (AK == AArch64::ArchKind::ARMV8_4A) + Features.push_back("+v8.4a"); return AK != AArch64::ArchKind::INVALID; } @@ -585,6 +587,7 @@ .Case("v8.1a", "v8.1-a") .Case("v8.2a", "v8.2-a") .Case("v8.3a", "v8.3-a") + .Case("v8.4a", "v8.4-a") .Case("v8r", "v8-r") .Case("v8m.base", "v8-m.base") .Case("v8m.main", "v8-m.main") @@ -752,6 +755,7 @@ case ARM::ArchKind::ARMV8_1A: case ARM::ArchKind::ARMV8_2A: case ARM::ArchKind::ARMV8_3A: + case ARM::ArchKind::ARMV8_4A: return ARM::ProfileKind::A; case ARM::ArchKind::ARMV2: case ARM::ArchKind::ARMV2A: @@ -814,6 +818,7 @@ case ARM::ArchKind::ARMV8_1A: case ARM::ArchKind::ARMV8_2A: case ARM::ArchKind::ARMV8_3A: + case ARM::ArchKind::ARMV8_4A: case ARM::ArchKind::ARMV8R: case ARM::ArchKind::ARMV8MBaseline: case ARM::ArchKind::ARMV8MMainline: Index: llvm/trunk/lib/Support/Triple.cpp =================================================================== --- llvm/trunk/lib/Support/Triple.cpp +++ llvm/trunk/lib/Support/Triple.cpp @@ -590,6 +590,8 @@ return Triple::ARMSubArch_v8_2a; case ARM::ArchKind::ARMV8_3A: return Triple::ARMSubArch_v8_3a; + case ARM::ArchKind::ARMV8_4A: + return Triple::ARMSubArch_v8_4a; case ARM::ArchKind::ARMV8R: return Triple::ARMSubArch_v8r; case ARM::ArchKind::ARMV8MBaseline: Index: llvm/trunk/lib/Target/AArch64/AArch64.td =================================================================== --- llvm/trunk/lib/Target/AArch64/AArch64.td +++ llvm/trunk/lib/Target/AArch64/AArch64.td @@ -26,8 +26,32 @@ def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true", "Enable Advanced SIMD instructions", [FeatureFPARMv8]>; +def FeatureSM4 : SubtargetFeature< + "sm4", "HasSM4", "true", + "Enable SM3 and SM4 support", [FeatureNEON]>; + +def FeatureSHA2 : SubtargetFeature< + "sha2", "HasSHA2", "true", + "Enable SHA1 and SHA256 support", [FeatureNEON]>; + +def FeatureSHA3 : SubtargetFeature< + "sha3", "HasSHA3", "true", + "Enable SHA512 and SHA3 support", [FeatureNEON, FeatureSHA2]>; + +def FeatureAES : SubtargetFeature< + "aes", "HasAES", "true", + "Enable AES support", [FeatureNEON]>; + +// Crypto has been split up and any combination is now valid (see the +// crypto defintions above). Also, crypto is now context sensitive: +// it has a different meaning for e.g. Armv8.4 than it has for Armv8.2. +// Therefore, we rely on Clang, the user interacing tool, to pass on the +// appropriate crypto options. But here in the backend, crypto has very little +// meaning anymore. We kept the Crypto defintion here for backward +// compatibility, and now imply features SHA2 and AES, which was the +// "traditional" meaning of Crypto. def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true", - "Enable cryptographic instructions", [FeatureNEON]>; + "Enable cryptographic instructions", [FeatureNEON, FeatureSHA2, FeatureAES]>; def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true", "Enable ARMv8 CRC-32 checksum instructions">; @@ -185,6 +209,9 @@ def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true", "Support ARM v8.3a instructions", [HasV8_2aOps, FeatureRCPC]>; +def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true", + "Support ARM v8.4a instructions", [HasV8_3aOps, FeatureDotProd]>; + //===----------------------------------------------------------------------===// // Register File Description //===----------------------------------------------------------------------===// Index: llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h =================================================================== --- llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h +++ llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h @@ -66,6 +66,7 @@ bool HasV8_1aOps = false; bool HasV8_2aOps = false; bool HasV8_3aOps = false; + bool HasV8_4aOps = false; bool HasFPARMv8 = false; bool HasNEON = false; @@ -78,6 +79,14 @@ bool HasPerfMon = false; bool HasFullFP16 = false; bool HasSPE = false; + + // ARMv8.4 Crypto extensions + bool HasSM4 = true; + bool HasSHA3 = true; + + bool HasSHA2 = true; + bool HasAES = true; + bool HasLSLFast = false; bool HasSVE = false; bool HasRCPC = false; @@ -201,6 +210,7 @@ bool hasV8_1aOps() const { return HasV8_1aOps; } bool hasV8_2aOps() const { return HasV8_2aOps; } bool hasV8_3aOps() const { return HasV8_3aOps; } + bool hasV8_4aOps() const { return HasV8_4aOps; } bool hasZeroCycleRegMove() const { return HasZeroCycleRegMove; } @@ -228,6 +238,10 @@ bool hasLSE() const { return HasLSE; } bool hasRAS() const { return HasRAS; } bool hasRDM() const { return HasRDM; } + bool hasSM4() const { return HasSM4; } + bool hasSHA3() const { return HasSHA3; } + bool hasSHA2() const { return HasSHA2; } + bool hasAES() const { return HasAES; } bool balanceFPOps() const { return BalanceFPOps; } bool predictableSelectIsExpensive() const { return PredictableSelectIsExpensive; Index: llvm/trunk/lib/Target/ARM/ARM.td =================================================================== --- llvm/trunk/lib/Target/ARM/ARM.td +++ llvm/trunk/lib/Target/ARM/ARM.td @@ -109,10 +109,16 @@ "Enable support for ARMv8-M " "Security Extensions">; +def FeatureSHA2 : SubtargetFeature<"sha2", "HasSHA2", "true", + "Enable SHA1 and SHA256 support", [FeatureNEON]>; + +def FeatureAES : SubtargetFeature<"aes", "HasAES", "true", + "Enable AES support", [FeatureNEON]>; + def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true", "Enable support for " "Cryptography extensions", - [FeatureNEON]>; + [FeatureNEON, FeatureSHA2, FeatureAES]>; def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true", "Enable support for CRC instructions">; @@ -419,6 +425,10 @@ "Support ARM v8.3a instructions", [HasV8_2aOps]>; +def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true", + "Support ARM v8.4a instructions", + [HasV8_3aOps, FeatureDotProd]>; + //===----------------------------------------------------------------------===// // ARM Processor subtarget features. // @@ -624,6 +634,20 @@ FeatureCRC, FeatureRAS]>; +def ARMv84a : Architecture<"armv8.4-a", "ARMv84a", [HasV8_4aOps, + FeatureAClass, + FeatureDB, + FeatureFPARMv8, + FeatureNEON, + FeatureDSP, + FeatureTrustZone, + FeatureMP, + FeatureVirtualization, + FeatureCrypto, + FeatureCRC, + FeatureRAS, + FeatureDotProd]>; + def ARMv8r : Architecture<"armv8-r", "ARMv8r", [HasV8Ops, FeatureRClass, FeatureDB, Index: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td =================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td @@ -253,6 +253,8 @@ AssemblerPredicate<"HasV8_2aOps", "armv8.2a">; def HasV8_3a : Predicate<"Subtarget->hasV8_3aOps()">, AssemblerPredicate<"HasV8_3aOps", "armv8.3a">; +def HasV8_4a : Predicate<"Subtarget->hasV8_4aOps()">, + AssemblerPredicate<"HasV8_4aOps", "armv8.4a">; def NoVFP : Predicate<"!Subtarget->hasVFP2()">; def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, AssemblerPredicate<"FeatureVFP2", "VFP2">; @@ -267,6 +269,10 @@ AssemblerPredicate<"FeatureFPARMv8", "FPARMv8">; def HasNEON : Predicate<"Subtarget->hasNEON()">, AssemblerPredicate<"FeatureNEON", "NEON">; +def HasSHA2 : Predicate<"Subtarget->hasSHA2()">, + AssemblerPredicate<"FeatureSHA2", "sha2">; +def HasAES : Predicate<"Subtarget->hasAES()">, + AssemblerPredicate<"FeatureAES", "aes">; def HasCrypto : Predicate<"Subtarget->hasCrypto()">, AssemblerPredicate<"FeatureCrypto", "crypto">; def HasDotProd : Predicate<"Subtarget->hasDotProd()">, Index: llvm/trunk/lib/Target/ARM/ARMSubtarget.h =================================================================== --- llvm/trunk/lib/Target/ARM/ARMSubtarget.h +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h @@ -105,6 +105,7 @@ ARMv81a, ARMv82a, ARMv83a, + ARMv84a, ARMv8a, ARMv8mBaseline, ARMv8mMainline, @@ -151,6 +152,7 @@ bool HasV8_1aOps = false; bool HasV8_2aOps = false; bool HasV8_3aOps = false; + bool HasV8_4aOps = false; bool HasV8MBaselineOps = false; bool HasV8MMainlineOps = false; @@ -299,6 +301,12 @@ /// Has8MSecExt - if true, processor supports ARMv8-M Security Extensions bool Has8MSecExt = false; + /// HasSHA2 - if true, processor supports SHA1 and SHA256 + bool HasSHA2 = false; + + /// HasAES - if true, processor supports AES + bool HasAES = false; + /// HasCrypto - if true, processor supports Cryptography extensions bool HasCrypto = false; @@ -513,6 +521,7 @@ bool hasV8_1aOps() const { return HasV8_1aOps; } bool hasV8_2aOps() const { return HasV8_2aOps; } bool hasV8_3aOps() const { return HasV8_3aOps; } + bool hasV8_4aOps() const { return HasV8_4aOps; } bool hasV8MBaselineOps() const { return HasV8MBaselineOps; } bool hasV8MMainlineOps() const { return HasV8MMainlineOps; } @@ -538,6 +547,8 @@ bool hasVFP4() const { return HasVFPv4; } bool hasFPARMv8() const { return HasFPARMv8; } bool hasNEON() const { return HasNEON; } + bool hasSHA2() const { return HasSHA2; } + bool hasAES() const { return HasAES; } bool hasCrypto() const { return HasCrypto; } bool hasDotProd() const { return HasDotProd; } bool hasCRC() const { return HasCRC; } Index: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp =================================================================== --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp @@ -859,6 +859,8 @@ case ARM::ArchKind::ARMV8A: case ARM::ArchKind::ARMV8_1A: case ARM::ArchKind::ARMV8_2A: + case ARM::ArchKind::ARMV8_3A: + case ARM::ArchKind::ARMV8_4A: setAttributeItem(CPU_arch_profile, ApplicationProfile, false); setAttributeItem(ARM_ISA_use, Allowed, false); setAttributeItem(THUMB_ISA_use, AllowThumb32, false);