Index: lib/Target/X86/AsmParser/X86AsmParser.cpp
===================================================================
--- lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -974,6 +974,13 @@
 static bool CheckBaseRegAndIndexRegAndScale(unsigned BaseReg, unsigned IndexReg,
                                             unsigned Scale, bool Is64BitMode,
                                             StringRef &ErrMsg) {
+  // RIP/EIP-relative addressing is only supported in 64-bit mode.
+  if (!Is64BitMode && BaseReg != 0 &&
+      (BaseReg == X86::RIP || BaseReg == X86::EIP)) {
+    ErrMsg = "RIP-relative addressing requires 64-bit mode";
+    return true;
+  }
+
   // If we have both a base register and an index register make sure they are
   // both 64-bit or 32-bit registers.
   // To support VSIB, IndexReg can be 128-bit or 256-bit registers.
Index: test/CodeGen/X86/eip-addressing-i386.ll
===================================================================
--- /dev/null
+++ test/CodeGen/X86/eip-addressing-i386.ll
@@ -0,0 +1,13 @@
+; RUN: not llc -mtriple i386-apple-- -o /dev/null < %s 2>&1| FileCheck %s
+; CHECK: <inline asm>:1:13: error: RIP-relative addressing requires 64-bit mode
+; CHECK-NEXT: jmpl *_foo(%eip)
+
+; Make sure that we emit an error if we encounter RIP-relative instructions in
+; 32-bit mode.
+
+define i32 @foo() { ret i32 0 }
+
+define i32 @bar() {
+  call void asm sideeffect "jmpl *_foo(%eip)\0A", "~{dirflag},~{fpsr},~{flags}"()
+  ret i32 0
+}