Index: lib/Target/RISCV/RISCVCallingConv.td
===================================================================
--- lib/Target/RISCV/RISCVCallingConv.td
+++ lib/Target/RISCV/RISCVCallingConv.td
@@ -18,3 +18,16 @@
 
 // Needed for implementation of RISCVRegisterInfo::getNoPreservedMask()
 def CSR_NoRegs : CalleeSavedRegs<(add)>;
+
+// Interrupt handler needs to save/restore all registers that are used,
+// both Caller and Callee saved registers.
+def CSR_Interrupt : CalleeSavedRegs<(add X1, X3, X4, X5, X6, X7, X8, X9,
+    (sequence "X%u", 10, 17),
+    (sequence "X%u", 18, 27),
+    (sequence "X%u", 28, 31))>;
+
+// Interrupt handler with calls to other functions needs to
+// unconditionally save all Caller saved registers.
+def CSR_Interrupt_With_Call :  CalleeSavedRegs<(add X1, X3, X4, X5, X6, X7,
+    (sequence "X%u", 10, 17),
+    (sequence "X%u", 28, 31))>;
Index: lib/Target/RISCV/RISCVFrameLowering.cpp
===================================================================
--- lib/Target/RISCV/RISCVFrameLowering.cpp
+++ lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -212,6 +212,18 @@
     SavedRegs.set(RISCV::X1);
     SavedRegs.set(RISCV::X8);
   }
+
+  const RISCVRegisterInfo *RI = STI.getRegisterInfo();
+  // If interrupt is enabled and there are calls, unconditionally save
+  // all Caller saved registers regardless whether they are used.
+  if (MF.getFunction().hasFnAttribute("interrupt")) {
+    MachineFrameInfo &MFI = MF.getFrameInfo();
+    if(MFI.hasCalls()) {
+      const MCPhysReg *CSRegs = RI->getCalleeSavedRegsForInterruptWithCall();
+      for (unsigned i = 0; CSRegs[i]; ++i)
+        SavedRegs.set(CSRegs[i]);
+    }
+  }
 }
 
 void RISCVFrameLowering::processFunctionBeforeFrameFinalized(
Index: lib/Target/RISCV/RISCVISelLowering.h
===================================================================
--- lib/Target/RISCV/RISCVISelLowering.h
+++ lib/Target/RISCV/RISCVISelLowering.h
@@ -25,6 +25,9 @@
 enum NodeType : unsigned {
   FIRST_NUMBER = ISD::BUILTIN_OP_END,
   RET_FLAG,
+  URET_FLAG,
+  SRET_FLAG,
+  MRET_FLAG,
   CALL,
   SELECT_CC,
   BuildPairF64,
Index: lib/Target/RISCV/RISCVISelLowering.cpp
===================================================================
--- lib/Target/RISCV/RISCVISelLowering.cpp
+++ lib/Target/RISCV/RISCVISelLowering.cpp
@@ -967,6 +967,21 @@
   }
 
   MachineFunction &MF = DAG.getMachineFunction();
+
+  const Function &Func = MF.getFunction();
+  if (Func.hasFnAttribute("interrupt")) {
+    if (!Func.arg_empty())
+      report_fatal_error(
+        "Functions with the interrupt attribute cannot have arguments!");
+
+    StringRef Kind =
+      MF.getFunction().getFnAttribute("interrupt").getValueAsString();
+
+    if (!(Kind == "user" || Kind == "supervisor" || Kind == "machine"))
+      report_fatal_error(
+        "Function interrupt attribute argument not supported!");
+  }
+
   EVT PtrVT = getPointerTy(DAG.getDataLayout());
   MVT XLenVT = Subtarget.getXLenVT();
   unsigned XLenInBytes = Subtarget.getXLen() / 8;
@@ -1515,6 +1530,28 @@
     RetOps.push_back(Glue);
   }
 
+  // Interrupt service routines use different return instructions.
+  const Function &Func = DAG.getMachineFunction().getFunction();
+  if (Func.hasFnAttribute("interrupt")) {
+    if (!Func.getReturnType()->isVoidTy())
+      report_fatal_error(
+          "Functions with the interrupt attribute must have void return type!");
+
+    MachineFunction &MF = DAG.getMachineFunction();
+    StringRef Kind =
+      MF.getFunction().getFnAttribute("interrupt").getValueAsString();
+
+    unsigned RetOpc;
+    if (Kind == "user")
+      RetOpc = RISCVISD::URET_FLAG;
+    else if (Kind == "supervisor")
+      RetOpc = RISCVISD::SRET_FLAG;
+    else
+      RetOpc = RISCVISD::MRET_FLAG;
+
+    return DAG.getNode(RetOpc, DL, MVT::Other, RetOps);
+  }
+
   return DAG.getNode(RISCVISD::RET_FLAG, DL, MVT::Other, RetOps);
 }
 
@@ -1524,6 +1561,12 @@
     break;
   case RISCVISD::RET_FLAG:
     return "RISCVISD::RET_FLAG";
+  case RISCVISD::URET_FLAG:
+    return "RISCVISD::URET_FLAG";
+  case RISCVISD::SRET_FLAG:
+    return "RISCVISD::SRET_FLAG";
+  case RISCVISD::MRET_FLAG:
+    return "RISCVISD::MRET_FLAG";
   case RISCVISD::CALL:
     return "RISCVISD::CALL";
   case RISCVISD::SELECT_CC:
Index: lib/Target/RISCV/RISCVInstrInfo.cpp
===================================================================
--- lib/Target/RISCV/RISCVInstrInfo.cpp
+++ lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -118,7 +118,8 @@
   unsigned Opcode;
 
   if (RISCV::GPRRegClass.hasSubClassEq(RC))
-    Opcode = RISCV::SW;
+    Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ?
+             RISCV::SW : RISCV::SD;
   else if (RISCV::FPR32RegClass.hasSubClassEq(RC))
     Opcode = RISCV::FSW;
   else if (RISCV::FPR64RegClass.hasSubClassEq(RC))
@@ -144,7 +145,8 @@
   unsigned Opcode;
 
   if (RISCV::GPRRegClass.hasSubClassEq(RC))
-    Opcode = RISCV::LW;
+    Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ?
+             RISCV::LW : RISCV::LD;
   else if (RISCV::FPR32RegClass.hasSubClassEq(RC))
     Opcode = RISCV::FLW;
   else if (RISCV::FPR64RegClass.hasSubClassEq(RC))
Index: lib/Target/RISCV/RISCVInstrInfo.td
===================================================================
--- lib/Target/RISCV/RISCVInstrInfo.td
+++ lib/Target/RISCV/RISCVInstrInfo.td
@@ -36,6 +36,12 @@
                           [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
 def RetFlag      : SDNode<"RISCVISD::RET_FLAG", SDTNone,
                           [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
+def URetFlag     : SDNode<"RISCVISD::URET_FLAG", SDTNone,
+                          [SDNPHasChain, SDNPOptInGlue]>;
+def SRetFlag     : SDNode<"RISCVISD::SRET_FLAG", SDTNone,
+                          [SDNPHasChain, SDNPOptInGlue]>;
+def MRetFlag     : SDNode<"RISCVISD::MRET_FLAG", SDTNone,
+                          [SDNPHasChain, SDNPOptInGlue]>;
 def SelectCC     : SDNode<"RISCVISD::SELECT_CC", SDT_RISCVSelectCC,
                           [SDNPInGlue]>;
 def Tail         : SDNode<"RISCVISD::TAIL", SDT_RISCVCall,
@@ -684,6 +690,10 @@
 
 def : Pat<(Call texternalsym:$func), (PseudoCALL texternalsym:$func)>;
 
+def : Pat<(URetFlag), (URET X0, X0)>;
+def : Pat<(SRetFlag), (SRET X0, X0)>;
+def : Pat<(MRetFlag), (MRET X0, X0)>;
+
 let isCall = 1, Defs = [X1] in
 def PseudoCALLIndirect : Pseudo<(outs), (ins GPR:$rs1), [(Call GPR:$rs1)]>,
                          PseudoInstExpansion<(JALR X1, GPR:$rs1, 0)>;
Index: lib/Target/RISCV/RISCVRegisterInfo.h
===================================================================
--- lib/Target/RISCV/RISCVRegisterInfo.h
+++ lib/Target/RISCV/RISCVRegisterInfo.h
@@ -53,6 +53,8 @@
   bool trackLivenessAfterRegAlloc(const MachineFunction &) const override {
     return true;
   }
+
+ const MCPhysReg *getCalleeSavedRegsForInterruptWithCall() const;
 };
 }
 
Index: lib/Target/RISCV/RISCVRegisterInfo.cpp
===================================================================
--- lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -33,6 +33,8 @@
 
 const MCPhysReg *
 RISCVRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
+  if (MF->getFunction().hasFnAttribute("interrupt"))
+    return CSR_Interrupt_SaveList;
   return CSR_SaveList;
 }
 
@@ -108,7 +110,14 @@
 }
 
 const uint32_t *
-RISCVRegisterInfo::getCallPreservedMask(const MachineFunction & /*MF*/,
+RISCVRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
                                         CallingConv::ID /*CC*/) const {
+  if (MF.getFunction().hasFnAttribute("interrupt"))
+    return CSR_Interrupt_RegMask;
   return CSR_RegMask;
 }
+
+const MCPhysReg *
+RISCVRegisterInfo::getCalleeSavedRegsForInterruptWithCall() const {
+  return CSR_Interrupt_With_Call_SaveList;
+}
Index: lib/Target/RISCV/RISCVSubtarget.cpp
===================================================================
--- lib/Target/RISCV/RISCVSubtarget.cpp
+++ lib/Target/RISCV/RISCVSubtarget.cpp
@@ -46,3 +46,4 @@
     : RISCVGenSubtargetInfo(TT, CPU, FS),
       FrameLowering(initializeSubtargetDependencies(CPU, FS, TT.isArch64Bit())),
       InstrInfo(), RegInfo(getHwMode()), TLInfo(TM, *this) {}
+
Index: test/CodeGen/RISCV/interrupt-attr-args-error.ll
===================================================================
--- /dev/null
+++ test/CodeGen/RISCV/interrupt-attr-args-error.ll
@@ -0,0 +1,11 @@
+; RUN: not llc -mtriple riscv32-unknown-elf -o - %s \
+; RUN: 2>&1 | FileCheck %s
+; RUN: not llc -mtriple riscv64-unknown-elf -o - %s \
+; RUN: 2>&1 | FileCheck %s
+
+; CHECK: LLVM ERROR: Functions with the interrupt attribute cannot have arguments!
+define i32 @isr_user(i8 %n) #0 {
+  ret i32 0
+}
+
+attributes #0 = { "interrupt"="user" }
Index: test/CodeGen/RISCV/interrupt-attr-invalid.ll
===================================================================
--- /dev/null
+++ test/CodeGen/RISCV/interrupt-attr-invalid.ll
@@ -0,0 +1,11 @@
+; RUN: not llc -mtriple riscv32-unknown-elf -o - %s \
+; RUN: 2>&1 | FileCheck %s
+; RUN: not llc -mtriple riscv64-unknown-elf -o - %s \
+; RUN: 2>&1 | FileCheck %s
+
+; CHECK: LLVM ERROR: Function interrupt attribute argument not supported!
+define void @isr_user() #0 {
+  ret void
+}
+
+attributes #0 = { "interrupt"="foo" }
Index: test/CodeGen/RISCV/interrupt-attr-nocall.ll
===================================================================
--- /dev/null
+++ test/CodeGen/RISCV/interrupt-attr-nocall.ll
@@ -0,0 +1,79 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple riscv32-unknown-elf -o - %s \
+; RUN: 2>&1 | FileCheck %s -check-prefix CHECK-RV32
+;
+; TODO: Add RV64 tests when we can lower global addresses.
+
+; Checking all registers that are used are being saved.
+; This includes Caller (arguments and temps) and
+; Callee saved registers.
+;
+; extern int a, b, c;
+; __attribute__((interrupt)) void foo_no_call(void) {
+;   c = a + b;
+; }
+;
+
+@a = external global i32
+@b = external global i32
+@c = external global i32
+
+define void @foo_no_call() #0 {
+; CHECK-RV32-LABEL: foo_no_call:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    addi sp, sp, -16
+; CHECK-RV32-NEXT:    sw a0, 12(sp)
+; CHECK-RV32-NEXT:    sw a1, 8(sp)
+; CHECK-RV32-NEXT:    lui a0, %hi(a)
+; CHECK-RV32-NEXT:    lw a0, %lo(a)(a0)
+; CHECK-RV32-NEXT:    lui a1, %hi(b)
+; CHECK-RV32-NEXT:    lw a1, %lo(b)(a1)
+; CHECK-RV32-NEXT:    add a0, a1, a0
+; CHECK-RV32-NEXT:    lui a1, %hi(c)
+; CHECK-RV32-NEXT:    sw a0, %lo(c)(a1)
+; CHECK-RV32-NEXT:    lw a1, 8(sp)
+; CHECK-RV32-NEXT:    lw a0, 12(sp)
+; CHECK-RV32-NEXT:    addi sp, sp, 16
+; CHECK-RV32-NEXT:    mret
+  %1 = load i32, i32* @a
+  %2 = load i32, i32* @b
+  %add = add nsw i32 %2, %1
+  store i32 %add, i32* @c
+  ret void
+}
+
+;
+; Additionally check frame pointer and return address are properly saved.
+;
+
+define void @foo_no_call2() #1 {
+; CHECK-RV32-LABEL: foo_no_call2:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    addi sp, sp, -16
+; CHECK-RV32-NEXT:    sw ra, 12(sp)
+; CHECK-RV32-NEXT:    sw s0, 8(sp)
+; CHECK-RV32-NEXT:    sw a0, 4(sp)
+; CHECK-RV32-NEXT:    sw a1, 0(sp)
+; CHECK-RV32-NEXT:    addi s0, sp, 16
+; CHECK-RV32-NEXT:    lui a0, %hi(a)
+; CHECK-RV32-NEXT:    lw a0, %lo(a)(a0)
+; CHECK-RV32-NEXT:    lui a1, %hi(b)
+; CHECK-RV32-NEXT:    lw a1, %lo(b)(a1)
+; CHECK-RV32-NEXT:    add a0, a1, a0
+; CHECK-RV32-NEXT:    lui a1, %hi(c)
+; CHECK-RV32-NEXT:    sw a0, %lo(c)(a1)
+; CHECK-RV32-NEXT:    lw a1, 0(sp)
+; CHECK-RV32-NEXT:    lw a0, 4(sp)
+; CHECK-RV32-NEXT:    lw s0, 8(sp)
+; CHECK-RV32-NEXT:    lw ra, 12(sp)
+; CHECK-RV32-NEXT:    addi sp, sp, 16
+; CHECK-RV32-NEXT:    mret
+  %1 = load i32, i32* @a
+  %2 = load i32, i32* @b
+  %add = add nsw i32 %2, %1
+  store i32 %add, i32* @c
+  ret void
+}
+
+attributes #0 = { "interrupt"="machine" }
+attributes #1 = { "interrupt"="machine" "no-frame-pointer-elim"="true" }
Index: test/CodeGen/RISCV/interrupt-attr-ret-error.ll
===================================================================
--- /dev/null
+++ test/CodeGen/RISCV/interrupt-attr-ret-error.ll
@@ -0,0 +1,12 @@
+; RUN: not llc -mtriple riscv32-unknown-elf -o - %s \
+; RUN: 2>&1 | FileCheck %s
+; RUN: not llc -mtriple riscv64-unknown-elf -o - %s \
+; RUN: 2>&1 | FileCheck %s
+
+; CHECK: LLVM ERROR: Functions with the interrupt attribute must have void return type!
+define i32 @isr1_user() #0 {
+  ret i32 0
+}
+
+
+attributes #0 = { "interrupt"="user" }
Index: test/CodeGen/RISCV/interrupt-attr.ll
===================================================================
--- /dev/null
+++ test/CodeGen/RISCV/interrupt-attr.ll
@@ -0,0 +1,239 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple riscv32-unknown-elf -o - %s \
+; RUN: 2>&1 | FileCheck %s -check-prefix CHECK -check-prefix CHECK-RV32
+; RUN: llc -mtriple riscv64-unknown-elf -o - %s \
+; RUN: 2>&1 | FileCheck %s -check-prefix CHECK -check-prefix CHECK-RV64
+
+;
+;
+; TODO: Add RV64 tests when we can lower global addresses.
+;
+; Checking for special return instructions (uret, sret, mret).
+;
+define void @foo_user() #0 {
+; CHECK-LABEL: foo_user:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    uret
+  ret void
+}
+
+define void @foo_supervisor() #1 {
+; CHECK-LABEL: foo_supervisor:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sret
+  ret void
+}
+
+define void @foo_machine() #2 {
+; CHECK-LABEL: foo_machine:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    mret
+  ret void
+}
+
+;
+; Checking all Caller saved registers (arguments and temps)
+; are all saved since they might be clobbered if the handler
+; calls another function.
+;
+; extern int otherfoo();
+;
+; __attribute__((interrupt)) void foo_with_call() {
+;   otherfoo();
+; }
+;
+
+declare i32 @otherfoo(...)
+define void @foo_with_call() #2 {
+; CHECK-RV32-LABEL: foo_with_call:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    addi sp, sp, -80
+; CHECK-RV32-NEXT:    sw ra, 76(sp)
+; CHECK-RV32-NEXT:    sw gp, 72(sp)
+; CHECK-RV32-NEXT:    sw tp, 68(sp)
+; CHECK-RV32-NEXT:    sw t0, 64(sp)
+; CHECK-RV32-NEXT:    sw t1, 60(sp)
+; CHECK-RV32-NEXT:    sw t2, 56(sp)
+; CHECK-RV32-NEXT:    sw a0, 52(sp)
+; CHECK-RV32-NEXT:    sw a1, 48(sp)
+; CHECK-RV32-NEXT:    sw a2, 44(sp)
+; CHECK-RV32-NEXT:    sw a3, 40(sp)
+; CHECK-RV32-NEXT:    sw a4, 36(sp)
+; CHECK-RV32-NEXT:    sw a5, 32(sp)
+; CHECK-RV32-NEXT:    sw a6, 28(sp)
+; CHECK-RV32-NEXT:    sw a7, 24(sp)
+; CHECK-RV32-NEXT:    sw t3, 20(sp)
+; CHECK-RV32-NEXT:    sw t4, 16(sp)
+; CHECK-RV32-NEXT:    sw t5, 12(sp)
+; CHECK-RV32-NEXT:    sw t6, 8(sp)
+; CHECK-RV32-NEXT:    call otherfoo
+; CHECK-RV32-NEXT:    lw t6, 8(sp)
+; CHECK-RV32-NEXT:    lw t5, 12(sp)
+; CHECK-RV32-NEXT:    lw t4, 16(sp)
+; CHECK-RV32-NEXT:    lw t3, 20(sp)
+; CHECK-RV32-NEXT:    lw a7, 24(sp)
+; CHECK-RV32-NEXT:    lw a6, 28(sp)
+; CHECK-RV32-NEXT:    lw a5, 32(sp)
+; CHECK-RV32-NEXT:    lw a4, 36(sp)
+; CHECK-RV32-NEXT:    lw a3, 40(sp)
+; CHECK-RV32-NEXT:    lw a2, 44(sp)
+; CHECK-RV32-NEXT:    lw a1, 48(sp)
+; CHECK-RV32-NEXT:    lw a0, 52(sp)
+; CHECK-RV32-NEXT:    lw t2, 56(sp)
+; CHECK-RV32-NEXT:    lw t1, 60(sp)
+; CHECK-RV32-NEXT:    lw t0, 64(sp)
+; CHECK-RV32-NEXT:    lw tp, 68(sp)
+; CHECK-RV32-NEXT:    lw gp, 72(sp)
+; CHECK-RV32-NEXT:    lw ra, 76(sp)
+; CHECK-RV32-NEXT:    addi sp, sp, 80
+; CHECK-RV32-NEXT:    mret
+;
+; CHECK-RV64-LABEL: foo_with_call:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    addi sp, sp, -144
+; CHECK-RV64-NEXT:    sd ra, 136(sp)
+; CHECK-RV64-NEXT:    sd gp, 128(sp)
+; CHECK-RV64-NEXT:    sd tp, 120(sp)
+; CHECK-RV64-NEXT:    sd t0, 112(sp)
+; CHECK-RV64-NEXT:    sd t1, 104(sp)
+; CHECK-RV64-NEXT:    sd t2, 96(sp)
+; CHECK-RV64-NEXT:    sd a0, 88(sp)
+; CHECK-RV64-NEXT:    sd a1, 80(sp)
+; CHECK-RV64-NEXT:    sd a2, 72(sp)
+; CHECK-RV64-NEXT:    sd a3, 64(sp)
+; CHECK-RV64-NEXT:    sd a4, 56(sp)
+; CHECK-RV64-NEXT:    sd a5, 48(sp)
+; CHECK-RV64-NEXT:    sd a6, 40(sp)
+; CHECK-RV64-NEXT:    sd a7, 32(sp)
+; CHECK-RV64-NEXT:    sd t3, 24(sp)
+; CHECK-RV64-NEXT:    sd t4, 16(sp)
+; CHECK-RV64-NEXT:    sd t5, 8(sp)
+; CHECK-RV64-NEXT:    sd t6, 0(sp)
+; CHECK-RV64-NEXT:    call otherfoo
+; CHECK-RV64-NEXT:    ld t6, 0(sp)
+; CHECK-RV64-NEXT:    ld t5, 8(sp)
+; CHECK-RV64-NEXT:    ld t4, 16(sp)
+; CHECK-RV64-NEXT:    ld t3, 24(sp)
+; CHECK-RV64-NEXT:    ld a7, 32(sp)
+; CHECK-RV64-NEXT:    ld a6, 40(sp)
+; CHECK-RV64-NEXT:    ld a5, 48(sp)
+; CHECK-RV64-NEXT:    ld a4, 56(sp)
+; CHECK-RV64-NEXT:    ld a3, 64(sp)
+; CHECK-RV64-NEXT:    ld a2, 72(sp)
+; CHECK-RV64-NEXT:    ld a1, 80(sp)
+; CHECK-RV64-NEXT:    ld a0, 88(sp)
+; CHECK-RV64-NEXT:    ld t2, 96(sp)
+; CHECK-RV64-NEXT:    ld t1, 104(sp)
+; CHECK-RV64-NEXT:    ld t0, 112(sp)
+; CHECK-RV64-NEXT:    ld tp, 120(sp)
+; CHECK-RV64-NEXT:    ld gp, 128(sp)
+; CHECK-RV64-NEXT:    ld ra, 136(sp)
+; CHECK-RV64-NEXT:    addi sp, sp, 144
+; CHECK-RV64-NEXT:    mret
+  %call = call i32 bitcast (i32 (...)* @otherfoo to i32 ()*)()
+  ret void
+}
+
+;
+; Additionally check frame pointer and return address are properly saved.
+;
+define void @foo_with_call2() #3 {
+; CHECK-RV32-LABEL: foo_with_call2:
+; CHECK-RV32:       # %bb.0:
+; CHECK-RV32-NEXT:    addi sp, sp, -80
+; CHECK-RV32-NEXT:    sw ra, 76(sp)
+; CHECK-RV32-NEXT:    sw gp, 72(sp)
+; CHECK-RV32-NEXT:    sw tp, 68(sp)
+; CHECK-RV32-NEXT:    sw t0, 64(sp)
+; CHECK-RV32-NEXT:    sw t1, 60(sp)
+; CHECK-RV32-NEXT:    sw t2, 56(sp)
+; CHECK-RV32-NEXT:    sw s0, 52(sp)
+; CHECK-RV32-NEXT:    sw a0, 48(sp)
+; CHECK-RV32-NEXT:    sw a1, 44(sp)
+; CHECK-RV32-NEXT:    sw a2, 40(sp)
+; CHECK-RV32-NEXT:    sw a3, 36(sp)
+; CHECK-RV32-NEXT:    sw a4, 32(sp)
+; CHECK-RV32-NEXT:    sw a5, 28(sp)
+; CHECK-RV32-NEXT:    sw a6, 24(sp)
+; CHECK-RV32-NEXT:    sw a7, 20(sp)
+; CHECK-RV32-NEXT:    sw t3, 16(sp)
+; CHECK-RV32-NEXT:    sw t4, 12(sp)
+; CHECK-RV32-NEXT:    sw t5, 8(sp)
+; CHECK-RV32-NEXT:    sw t6, 4(sp)
+; CHECK-RV32-NEXT:    addi s0, sp, 80
+; CHECK-RV32-NEXT:    call otherfoo
+; CHECK-RV32-NEXT:    lw t6, 4(sp)
+; CHECK-RV32-NEXT:    lw t5, 8(sp)
+; CHECK-RV32-NEXT:    lw t4, 12(sp)
+; CHECK-RV32-NEXT:    lw t3, 16(sp)
+; CHECK-RV32-NEXT:    lw a7, 20(sp)
+; CHECK-RV32-NEXT:    lw a6, 24(sp)
+; CHECK-RV32-NEXT:    lw a5, 28(sp)
+; CHECK-RV32-NEXT:    lw a4, 32(sp)
+; CHECK-RV32-NEXT:    lw a3, 36(sp)
+; CHECK-RV32-NEXT:    lw a2, 40(sp)
+; CHECK-RV32-NEXT:    lw a1, 44(sp)
+; CHECK-RV32-NEXT:    lw a0, 48(sp)
+; CHECK-RV32-NEXT:    lw s0, 52(sp)
+; CHECK-RV32-NEXT:    lw t2, 56(sp)
+; CHECK-RV32-NEXT:    lw t1, 60(sp)
+; CHECK-RV32-NEXT:    lw t0, 64(sp)
+; CHECK-RV32-NEXT:    lw tp, 68(sp)
+; CHECK-RV32-NEXT:    lw gp, 72(sp)
+; CHECK-RV32-NEXT:    lw ra, 76(sp)
+; CHECK-RV32-NEXT:    addi sp, sp, 80
+; CHECK-RV32-NEXT:    mret
+;
+; CHECK-RV64-LABEL: foo_with_call2:
+; CHECK-RV64:       # %bb.0:
+; CHECK-RV64-NEXT:    addi sp, sp, -160
+; CHECK-RV64-NEXT:    sd ra, 152(sp)
+; CHECK-RV64-NEXT:    sd gp, 144(sp)
+; CHECK-RV64-NEXT:    sd tp, 136(sp)
+; CHECK-RV64-NEXT:    sd t0, 128(sp)
+; CHECK-RV64-NEXT:    sd t1, 120(sp)
+; CHECK-RV64-NEXT:    sd t2, 112(sp)
+; CHECK-RV64-NEXT:    sd s0, 104(sp)
+; CHECK-RV64-NEXT:    sd a0, 96(sp)
+; CHECK-RV64-NEXT:    sd a1, 88(sp)
+; CHECK-RV64-NEXT:    sd a2, 80(sp)
+; CHECK-RV64-NEXT:    sd a3, 72(sp)
+; CHECK-RV64-NEXT:    sd a4, 64(sp)
+; CHECK-RV64-NEXT:    sd a5, 56(sp)
+; CHECK-RV64-NEXT:    sd a6, 48(sp)
+; CHECK-RV64-NEXT:    sd a7, 40(sp)
+; CHECK-RV64-NEXT:    sd t3, 32(sp)
+; CHECK-RV64-NEXT:    sd t4, 24(sp)
+; CHECK-RV64-NEXT:    sd t5, 16(sp)
+; CHECK-RV64-NEXT:    sd t6, 8(sp)
+; CHECK-RV64-NEXT:    addi s0, sp, 160
+; CHECK-RV64-NEXT:    call otherfoo
+; CHECK-RV64-NEXT:    ld t6, 8(sp)
+; CHECK-RV64-NEXT:    ld t5, 16(sp)
+; CHECK-RV64-NEXT:    ld t4, 24(sp)
+; CHECK-RV64-NEXT:    ld t3, 32(sp)
+; CHECK-RV64-NEXT:    ld a7, 40(sp)
+; CHECK-RV64-NEXT:    ld a6, 48(sp)
+; CHECK-RV64-NEXT:    ld a5, 56(sp)
+; CHECK-RV64-NEXT:    ld a4, 64(sp)
+; CHECK-RV64-NEXT:    ld a3, 72(sp)
+; CHECK-RV64-NEXT:    ld a2, 80(sp)
+; CHECK-RV64-NEXT:    ld a1, 88(sp)
+; CHECK-RV64-NEXT:    ld a0, 96(sp)
+; CHECK-RV64-NEXT:    ld s0, 104(sp)
+; CHECK-RV64-NEXT:    ld t2, 112(sp)
+; CHECK-RV64-NEXT:    ld t1, 120(sp)
+; CHECK-RV64-NEXT:    ld t0, 128(sp)
+; CHECK-RV64-NEXT:    ld tp, 136(sp)
+; CHECK-RV64-NEXT:    ld gp, 144(sp)
+; CHECK-RV64-NEXT:    ld ra, 152(sp)
+; CHECK-RV64-NEXT:    addi sp, sp, 160
+; CHECK-RV64-NEXT:    mret
+  %call = call i32 bitcast (i32 (...)* @otherfoo to i32 ()*)()
+  ret void
+}
+
+attributes #0 = { "interrupt"="user" }
+attributes #1 = { "interrupt"="supervisor" }
+attributes #2 = { "interrupt"="machine" }
+attributes #3 = { "interrupt"="machine" "no-frame-pointer-elim"="true" }