Index: lib/Target/RISCV/RISCVCallingConv.td
===================================================================
--- lib/Target/RISCV/RISCVCallingConv.td
+++ lib/Target/RISCV/RISCVCallingConv.td
@@ -18,3 +18,16 @@
 
 // Needed for implementation of RISCVRegisterInfo::getNoPreservedMask()
 def CSR_NoRegs : CalleeSavedRegs<(add)>;
+
+// Interrupt handler needs to save/restore caller-saved registers
+// as callee-saved registers.
+def CSR_Interrupt : CalleeSavedRegs<(add X1,
+    (sequence "X%u", 5, 7),
+    (sequence "X%u", 10, 17),
+    (sequence "X%u", 28, 31))>;
+
+def CSR_X32_F32_Interrupt : CalleeSavedRegs<(add X1,
+    (sequence "X%u", 5, 7),
+    (sequence "X%u", 10, 17),
+    (sequence "X%u", 28, 31),
+    (sequence "F%u_32", 0, 31))>;
Index: lib/Target/RISCV/RISCVFrameLowering.cpp
===================================================================
--- lib/Target/RISCV/RISCVFrameLowering.cpp
+++ lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -212,6 +212,17 @@
     SavedRegs.set(RISCV::X1);
     SavedRegs.set(RISCV::X8);
   }
+
+  // If interrupt is enabled and there are calls, save all registers
+  // regardless whether they are used.
+  if (MF.getFunction().hasFnAttribute("interrupt")) {
+    MachineFrameInfo &MFI = MF.getFrameInfo();
+    if(MFI.hasCalls()) {
+      const MCPhysReg *CSRegs = MF.getRegInfo().getCalleeSavedRegs();
+      for (unsigned i = 0; CSRegs[i]; ++i)
+        SavedRegs.set(CSRegs[i]);
+    }
+  }
 }
 
 void RISCVFrameLowering::processFunctionBeforeFrameFinalized(
Index: lib/Target/RISCV/RISCVISelLowering.h
===================================================================
--- lib/Target/RISCV/RISCVISelLowering.h
+++ lib/Target/RISCV/RISCVISelLowering.h
@@ -25,6 +25,9 @@
 enum NodeType : unsigned {
   FIRST_NUMBER = ISD::BUILTIN_OP_END,
   RET_FLAG,
+  URET_FLAG,
+  SRET_FLAG,
+  MRET_FLAG,
   CALL,
   SELECT_CC,
   BuildPairF64,
Index: lib/Target/RISCV/RISCVISelLowering.cpp
===================================================================
--- lib/Target/RISCV/RISCVISelLowering.cpp
+++ lib/Target/RISCV/RISCVISelLowering.cpp
@@ -967,6 +967,21 @@
   }
 
   MachineFunction &MF = DAG.getMachineFunction();
+
+  const Function &Func = MF.getFunction();
+  if (Func.hasFnAttribute("interrupt")) {
+    if (!Func.arg_empty())
+      report_fatal_error(
+        "Functions with the interrupt attribute cannot have arguments!");
+
+    StringRef Kind =
+      MF.getFunction().getFnAttribute("interrupt").getValueAsString();
+
+    if (!(Kind == "user" || Kind == "supervisor" || Kind == "machine"))
+      report_fatal_error(
+        "Function interrupt attribute argument not supported!");
+  }
+
   EVT PtrVT = getPointerTy(DAG.getDataLayout());
   MVT XLenVT = Subtarget.getXLenVT();
   unsigned XLenInBytes = Subtarget.getXLen() / 8;
@@ -1515,6 +1530,28 @@
     RetOps.push_back(Glue);
   }
 
+  // Interrupt service routines use different return instructions.
+  const Function &Func = DAG.getMachineFunction().getFunction();
+  if (Func.hasFnAttribute("interrupt")) {
+    if (!Func.getReturnType()->isVoidTy())
+      report_fatal_error(
+          "Functions with the interrupt attribute must have void return type!");
+
+    MachineFunction &MF = DAG.getMachineFunction();
+    StringRef Kind =
+      MF.getFunction().getFnAttribute("interrupt").getValueAsString();
+
+    unsigned RetOpc;
+    if (Kind == "user")
+      RetOpc = RISCVISD::URET_FLAG;
+    else if (Kind == "supervisor")
+      RetOpc = RISCVISD::SRET_FLAG;
+    else
+      RetOpc = RISCVISD::MRET_FLAG;
+
+    return DAG.getNode(RetOpc, DL, MVT::Other, RetOps);
+  }
+
   return DAG.getNode(RISCVISD::RET_FLAG, DL, MVT::Other, RetOps);
 }
 
@@ -1524,6 +1561,12 @@
     break;
   case RISCVISD::RET_FLAG:
     return "RISCVISD::RET_FLAG";
+  case RISCVISD::URET_FLAG:
+    return "RISCVISD::URET_FLAG";
+  case RISCVISD::SRET_FLAG:
+    return "RISCVISD::SRET_FLAG";
+  case RISCVISD::MRET_FLAG:
+    return "RISCVISD::MRET_FLAG";
   case RISCVISD::CALL:
     return "RISCVISD::CALL";
   case RISCVISD::SELECT_CC:
Index: lib/Target/RISCV/RISCVInstrInfo.cpp
===================================================================
--- lib/Target/RISCV/RISCVInstrInfo.cpp
+++ lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -118,7 +118,8 @@
   unsigned Opcode;
 
   if (RISCV::GPRRegClass.hasSubClassEq(RC))
-    Opcode = RISCV::SW;
+    Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ?
+             RISCV::SW : RISCV::SD;
   else if (RISCV::FPR32RegClass.hasSubClassEq(RC))
     Opcode = RISCV::FSW;
   else if (RISCV::FPR64RegClass.hasSubClassEq(RC))
@@ -144,7 +145,8 @@
   unsigned Opcode;
 
   if (RISCV::GPRRegClass.hasSubClassEq(RC))
-    Opcode = RISCV::LW;
+    Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ?
+             RISCV::LW : RISCV::LD;
   else if (RISCV::FPR32RegClass.hasSubClassEq(RC))
     Opcode = RISCV::FLW;
   else if (RISCV::FPR64RegClass.hasSubClassEq(RC))
Index: lib/Target/RISCV/RISCVInstrInfo.td
===================================================================
--- lib/Target/RISCV/RISCVInstrInfo.td
+++ lib/Target/RISCV/RISCVInstrInfo.td
@@ -36,6 +36,12 @@
                           [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
 def RetFlag      : SDNode<"RISCVISD::RET_FLAG", SDTNone,
                           [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
+def URetFlag     : SDNode<"RISCVISD::URET_FLAG", SDTNone,
+                          [SDNPHasChain, SDNPOptInGlue]>;
+def SRetFlag     : SDNode<"RISCVISD::SRET_FLAG", SDTNone,
+                          [SDNPHasChain, SDNPOptInGlue]>;
+def MRetFlag     : SDNode<"RISCVISD::MRET_FLAG", SDTNone,
+                          [SDNPHasChain, SDNPOptInGlue]>;
 def SelectCC     : SDNode<"RISCVISD::SELECT_CC", SDT_RISCVSelectCC,
                           [SDNPInGlue]>;
 def Tail         : SDNode<"RISCVISD::TAIL", SDT_RISCVCall,
@@ -684,6 +690,10 @@
 
 def : Pat<(Call texternalsym:$func), (PseudoCALL texternalsym:$func)>;
 
+def : Pat<(URetFlag), (URET X0, X0)>;
+def : Pat<(SRetFlag), (SRET X0, X0)>;
+def : Pat<(MRetFlag), (MRET X0, X0)>;
+
 let isCall = 1, Defs = [X1] in
 def PseudoCALLIndirect : Pseudo<(outs), (ins GPR:$rs1), [(Call GPR:$rs1)]>,
                          PseudoInstExpansion<(JALR X1, GPR:$rs1, 0)>;
Index: lib/Target/RISCV/RISCVRegisterInfo.cpp
===================================================================
--- lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -33,6 +33,11 @@
 
 const MCPhysReg *
 RISCVRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
+  if (MF->getFunction().hasFnAttribute("interrupt")) {
+    if (MF->getSubtarget<RISCVSubtarget>().hasStdExtF())
+      return CSR_X32_F32_Interrupt_SaveList;
+    return CSR_Interrupt_SaveList;
+  }
   return CSR_SaveList;
 }
 
@@ -108,7 +113,9 @@
 }
 
 const uint32_t *
-RISCVRegisterInfo::getCallPreservedMask(const MachineFunction & /*MF*/,
+RISCVRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
                                         CallingConv::ID /*CC*/) const {
+  if (MF.getFunction().hasFnAttribute("interrupt"))
+    return CSR_Interrupt_RegMask;
   return CSR_RegMask;
 }
Index: lib/Target/RISCV/RISCVSubtarget.cpp
===================================================================
--- lib/Target/RISCV/RISCVSubtarget.cpp
+++ lib/Target/RISCV/RISCVSubtarget.cpp
@@ -46,3 +46,4 @@
     : RISCVGenSubtargetInfo(TT, CPU, FS),
       FrameLowering(initializeSubtargetDependencies(CPU, FS, TT.isArch64Bit())),
       InstrInfo(), RegInfo(getHwMode()), TLInfo(TM, *this) {}
+
Index: test/CodeGen/RISCV/interrupt-attr-args-error.ll
===================================================================
--- /dev/null
+++ test/CodeGen/RISCV/interrupt-attr-args-error.ll
@@ -0,0 +1,11 @@
+; RUN: not llc -mtriple riscv32-unknown-elf -o - %s \
+; RUN: 2>&1 | FileCheck %s
+; RUN: not llc -mtriple riscv64-unknown-elf -o - %s \
+; RUN: 2>&1 | FileCheck %s
+
+; CHECK: LLVM ERROR: Functions with the interrupt attribute cannot have arguments!
+define i32 @isr_user(i8 %n) #0 {
+  ret i32 0
+}
+
+attributes #0 = { "interrupt"="user" }
Index: test/CodeGen/RISCV/interrupt-attr-invalid.ll
===================================================================
--- /dev/null
+++ test/CodeGen/RISCV/interrupt-attr-invalid.ll
@@ -0,0 +1,11 @@
+; RUN: not llc -mtriple riscv32-unknown-elf -o - %s \
+; RUN: 2>&1 | FileCheck %s
+; RUN: not llc -mtriple riscv64-unknown-elf -o - %s \
+; RUN: 2>&1 | FileCheck %s
+
+; CHECK: LLVM ERROR: Function interrupt attribute argument not supported!
+define void @isr_user() #0 {
+  ret void
+}
+
+attributes #0 = { "interrupt"="foo" }
Index: test/CodeGen/RISCV/interrupt-attr-ret-error.ll
===================================================================
--- /dev/null
+++ test/CodeGen/RISCV/interrupt-attr-ret-error.ll
@@ -0,0 +1,12 @@
+; RUN: not llc -mtriple riscv32-unknown-elf -o - %s \
+; RUN: 2>&1 | FileCheck %s
+; RUN: not llc -mtriple riscv64-unknown-elf -o - %s \
+; RUN: 2>&1 | FileCheck %s
+
+; CHECK: LLVM ERROR: Functions with the interrupt attribute must have void return type!
+define i32 @isr1_user() #0 {
+  ret i32 0
+}
+
+
+attributes #0 = { "interrupt"="user" }
Index: test/CodeGen/RISCV/interrupt-attr.ll
===================================================================
--- /dev/null
+++ test/CodeGen/RISCV/interrupt-attr.ll
@@ -0,0 +1,161 @@
+; RUN: llc -mtriple riscv32-unknown-elf -o - %s \
+; RUN: 2>&1 | FileCheck %s -check-prefix CHECK -check-prefix CHECK-RET -check-prefix CHECK-RV32
+; RUN: llc -mtriple riscv64-unknown-elf -o - %s \
+; RUN: 2>&1 | FileCheck %s -check-prefix CHECK -check-prefix CHECK-RET -check-prefix CHECK-RV64
+
+
+define void @foo_user() #0 {
+; CHECK-LABEL: foo_user:
+; CHECK-RET: uret
+  ret void
+}
+
+define void @foo_supervisor() #1 {
+; CHECK-LABEL: foo_supervisor:
+; CHECK-RET: sret
+  ret void
+}
+
+define void @foo_machine() #2 {
+; CHECK-LABEL: foo_machine:
+; CHECK-RET: mret
+  ret void
+}
+
+define void @foo() #3 {
+; CHECK-LABEL: foo:
+
+; CHECK-RV32:      addi sp, sp, -128
+; CHECK-RV32-NEXT: sw   ra, 124(sp)
+; CHECK-RV32-NEXT: sw   s0, 120(sp)
+; CHECK-RV32-NEXT: sw   s1, 116(sp)
+; CHECK-RV32-NEXT: sw   s2, 112(sp)
+; CHECK-RV32-NEXT: sw   s3, 108(sp)
+; CHECK-RV32-NEXT: sw   s4, 104(sp)
+; CHECK-RV32-NEXT: sw   s5, 100(sp)
+; CHECK-RV32-NEXT: sw   s6, 96(sp)
+; CHECK-RV32-NEXT: sw   s7, 92(sp)
+; CHECK-RV32-NEXT: sw   s8, 88(sp)
+; CHECK-RV32-NEXT: sw   s9, 84(sp)
+; CHECK-RV32-NEXT: sw   s10, 80(sp)
+; CHECK-RV32-NEXT: sw   s11, 76(sp)
+; CHECK-RV32-NEXT: sw   gp, 72(sp)
+; CHECK-RV32-NEXT: sw   tp, 68(sp)
+; CHECK-RV32-NEXT: sw   t0, 64(sp)
+; CHECK-RV32-NEXT: sw   t1, 60(sp)
+; CHECK-RV32-NEXT: sw   t2, 56(sp)
+; CHECK-RV32-NEXT: sw   a0, 52(sp)
+; CHECK-RV32-NEXT: sw   a1, 48(sp)
+; CHECK-RV32-NEXT: sw   a2, 44(sp)
+; CHECK-RV32-NEXT: sw   a3, 40(sp)
+; CHECK-RV32-NEXT: sw   a4, 36(sp)
+; CHECK-RV32-NEXT: sw   a5, 32(sp)
+; CHECK-RV32-NEXT: sw   a6, 28(sp)
+; CHECK-RV32-NEXT: sw   a7, 24(sp)
+; CHECK-RV32-NEXT: sw   t3, 20(sp)
+; CHECK-RV32-NEXT: sw   t4, 16(sp)
+; CHECK-RV32-NEXT: sw   t5, 12(sp)
+; CHECK-RV32-NEXT: sw   t6, 8(sp)
+; CHECK-RV32:      lw   t6, 8(sp)
+; CHECK-RV32-NEXT: lw   t5, 12(sp)
+; CHECK-RV32-NEXT: lw   t4, 16(sp)
+; CHECK-RV32-NEXT: lw   t3, 20(sp)
+; CHECK-RV32-NEXT: lw   a7, 24(sp)
+; CHECK-RV32-NEXT: lw   a6, 28(sp)
+; CHECK-RV32-NEXT: lw   a5, 32(sp)
+; CHECK-RV32-NEXT: lw   a4, 36(sp)
+; CHECK-RV32-NEXT: lw   a3, 40(sp)
+; CHECK-RV32-NEXT: lw   a2, 44(sp)
+; CHECK-RV32-NEXT: lw   a1, 48(sp)
+; CHECK-RV32-NEXT: lw   a0, 52(sp)
+; CHECK-RV32-NEXT: lw   t2, 56(sp)
+; CHECK-RV32-NEXT: lw   t1, 60(sp)
+; CHECK-RV32-NEXT: lw   t0, 64(sp)
+; CHECK-RV32-NEXT: lw   tp, 68(sp)
+; CHECK-RV32-NEXT: lw   gp, 72(sp)
+; CHECK-RV32-NEXT: lw   s11, 76(sp)
+; CHECK-RV32-NEXT: lw   s10, 80(sp)
+; CHECK-RV32-NEXT: lw   s9, 84(sp)
+; CHECK-RV32-NEXT: lw   s8, 88(sp)
+; CHECK-RV32-NEXT: lw   s7, 92(sp)
+; CHECK-RV32-NEXT: lw   s6, 96(sp)
+; CHECK-RV32-NEXT: lw   s5, 100(sp)
+; CHECK-RV32-NEXT: lw   s4, 104(sp)
+; CHECK-RV32-NEXT: lw   s3, 108(sp)
+; CHECK-RV32-NEXT: lw   s2, 112(sp)
+; CHECK-RV32-NEXT: lw   s1, 116(sp)
+; CHECK-RV32-NEXT: lw   s0, 120(sp)
+; CHECK-RV32-NEXT: lw   ra, 124(sp)
+; CHECK-RV32-NEXT: addi sp, sp, 128
+
+; CHECK-RV64:      addi sp, sp, -240
+; CHECK-RV64-NEXT: sd   ra, 232(sp)
+; CHECK-RV64-NEXT: sd   s0, 224(sp)
+; CHECK-RV64-NEXT: sd   s1, 216(sp)
+; CHECK-RV64-NEXT: sd   s2, 208(sp)
+; CHECK-RV64-NEXT: sd   s3, 200(sp)
+; CHECK-RV64-NEXT: sd   s4, 192(sp)
+; CHECK-RV64-NEXT: sd   s5, 184(sp)
+; CHECK-RV64-NEXT: sd   s6, 176(sp)
+; CHECK-RV64-NEXT: sd   s7, 168(sp)
+; CHECK-RV64-NEXT: sd   s8, 160(sp)
+; CHECK-RV64-NEXT: sd   s9, 152(sp)
+; CHECK-RV64-NEXT: sd   s10, 144(sp)
+; CHECK-RV64-NEXT: sd   s11, 136(sp)
+; CHECK-RV64-NEXT: sd   gp, 128(sp)
+; CHECK-RV64-NEXT: sd   tp, 120(sp)
+; CHECK-RV64-NEXT: sd   t0, 112(sp)
+; CHECK-RV64-NEXT: sd   t1, 104(sp)
+; CHECK-RV64-NEXT: sd   t2, 96(sp)
+; CHECK-RV64-NEXT: sd   a0, 88(sp)
+; CHECK-RV64-NEXT: sd   a1, 80(sp)
+; CHECK-RV64-NEXT: sd   a2, 72(sp)
+; CHECK-RV64-NEXT: sd   a3, 64(sp)
+; CHECK-RV64-NEXT: sd   a4, 56(sp)
+; CHECK-RV64-NEXT: sd   a5, 48(sp)
+; CHECK-RV64-NEXT: sd   a6, 40(sp)
+; CHECK-RV64-NEXT: sd   a7, 32(sp)
+; CHECK-RV64-NEXT: sd   t3, 24(sp)
+; CHECK-RV64-NEXT: sd   t4, 16(sp)
+; CHECK-RV64-NEXT: sd   t5, 8(sp)
+; CHECK-RV64-NEXT: sd   t6, 0(sp)
+; CHECK-RV64:      ld   t6, 0(sp)
+; CHECK-RV64-NEXT: ld   t5, 8(sp)
+; CHECK-RV64-NEXT: ld   t4, 16(sp)
+; CHECK-RV64-NEXT: ld   t3, 24(sp)
+; CHECK-RV64-NEXT: ld   a7, 32(sp)
+; CHECK-RV64-NEXT: ld   a6, 40(sp)
+; CHECK-RV64-NEXT: ld   a5, 48(sp)
+; CHECK-RV64-NEXT: ld   a4, 56(sp)
+; CHECK-RV64-NEXT: ld   a3, 64(sp)
+; CHECK-RV64-NEXT: ld   a2, 72(sp)
+; CHECK-RV64-NEXT: ld   a1, 80(sp)
+; CHECK-RV64-NEXT: ld   a0, 88(sp)
+; CHECK-RV64-NEXT: ld   t2, 96(sp)
+; CHECK-RV64-NEXT: ld   t1, 104(sp)
+; CHECK-RV64-NEXT: ld   t0, 112(sp)
+; CHECK-RV64-NEXT: ld   tp, 120(sp)
+; CHECK-RV64-NEXT: ld   gp, 128(sp)
+; CHECK-RV64-NEXT: ld   s11, 136(sp)
+; CHECK-RV64-NEXT: ld   s10, 144(sp)
+; CHECK-RV64-NEXT: ld   s9, 152(sp)
+; CHECK-RV64-NEXT: ld   s8, 160(sp)
+; CHECK-RV64-NEXT: ld   s7, 168(sp)
+; CHECK-RV64-NEXT: ld   s6, 176(sp)
+; CHECK-RV64-NEXT: ld   s5, 184(sp)
+; CHECK-RV64-NEXT: ld   s4, 192(sp)
+; CHECK-RV64-NEXT: ld   s3, 200(sp)
+; CHECK-RV64-NEXT: ld   s2, 208(sp)
+; CHECK-RV64-NEXT: ld   s1, 216(sp)
+; CHECK-RV64-NEXT: ld   s0, 224(sp)
+; CHECK-RV64-NEXT: ld   ra, 232(sp)
+; CHECK-RV64-NEXT: addi sp, sp, 240
+
+; CHECK-RET: mret
+  ret void
+}
+
+attributes #0 = { "interrupt"="user" }
+attributes #1 = { "interrupt"="supervisor" }
+attributes #2 = { "interrupt"="machine" }
+attributes #3 = { "interrupt" }