DAG: Fold out selects with an undef operand

[arsenm]

Summary

Instcombine already does this, but this can appear during legalization.

test/CodeGen/Hexagon/expand-vselect-kill.ll completely changes when fixed, and I'm not sure what exactly it was looking for in the first place

[kparzysz]

The testcase was looking for two conditional assignments, both based on the same predicate register, but with one condition "if-true" and the other "if-false". The original bug was that the "kill" flag on the condition register wasn't cleared on the first assignment and so it was killed before the second conditional assignment (causing a verifier error). I just replaced this testcase with a .mir version, so it's no longer there.

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

if (N1 == N2)
     return N1;
 
   if (const ConstantSDNode *N0C = dyn_cast<const ConstantSDNode>(N0)) {
     // fold (select true, X, Y) -> X
     // fold (select false, X, Y) -> Y
     return !N0C->isNullValue() ? N1 : N2;
   }
 
+  if (N1.isUndef())
+    return N2;
+
+  if (N2.isUndef())
+    return N1;
+
   // fold (select X, X, Y) -> (or X, Y)
   // fold (select X, 1, Y) -> (or C, Y)
   if (VT == VT0 && VT == MVT::i1 && (N0 == N1 || isOneConstant(N1)))
     return DAG.getNode(ISD::OR, DL, VT, N0, N2);
 
   if (SDValue V = foldSelectOfConstants(N))
     return V;
 

test/CodeGen/AArch64/half.ll

 ; CHECK-LABEL: test_trunc64:
 ; CHECK: fcvt {{h[0-9]+}}, {{d[0-9]+}}
 
   %val16 = fptrunc double %in to half
   store half %val16, half* %addr
   ret void
 }
 
-define i16 @test_fccmp(i1 %a) {
+define i16 @test_fccmp(i1 %a, i16 %val0, i16 %val1) {
 ;CHECK-LABEL: test_fccmp:
 ;CHECK: fcmp
   %cmp0 = fcmp ogt half 0xH3333, undef
   %cmp1 = fcmp ogt half 0xH2222, undef
-  %x = select i1 %cmp0, i16 0, i16 undef
+  %x = select i1 %cmp0, i16 0, i16 %val0
   %or = or i1 %cmp1, %cmp0
-  %y = select i1 %or, i16 4, i16 undef
+  %y = select i1 %or, i16 4, i16 %val1
   %r = add i16 %x, %y
   ret i16 %r
 }

test/CodeGen/AMDGPU/select-undef.ll

+; RUN: llc -mtriple=amdgcn-amd-amdhsa < %s | FileCheck -check-prefix=GCN %s
+
+; GCN-LABEL: {{^}}select_undef_lhs:
+; GCN: s_waitcnt
+; GCN-NEXT: s_setpc_b64
+define float @select_undef_lhs(float %val, i1 %cond) {
+  %undef = call float @llvm.amdgcn.image.sample.f32.v2f32.v8i32(<2 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 0, i1 0, i1 0, i1 0, i1 0, i1 0)
+  %sel = select i1 %cond, float %undef, float %val
+  ret float %sel
+}
+
+; GCN-LABEL: {{^}}select_undef_rhs:
+; GCN: s_waitcnt
+; GCN-NEXT: s_setpc_b64
+define float @select_undef_rhs(float %val, i1 %cond) {
+  %undef = call float @llvm.amdgcn.image.sample.f32.v2f32.v8i32(<2 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 0, i1 0, i1 0, i1 0, i1 0, i1 0)
+  %sel = select i1 %cond, float %val, float %undef
+  ret float %sel
+}
+
+declare float @llvm.amdgcn.image.sample.f32.v2f32.v8i32(<2 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #0

test/CodeGen/ARM/sub-cmp-peephole.ll

 }
 
 ; If the sub/rsb instruction is predicated, we can't use the flags.
 ; <rdar://problem/12263428>
 ; Test case from MultiSource/Benchmarks/Ptrdist/bc/number.s
 ; CHECK: bc_raise
 ; CHECK: rsbeq
 ; CHECK: cmp
-define i32 @bc_raise(i1 %cond) nounwind ssp {
+define i32 @bc_raise(i1 %cond, i32 %val) nounwind ssp {
 entry:
-  %val.2.i = select i1 %cond, i32 0, i32 undef
+  %val.2.i = select i1 %cond, i32 0, i32 %val
   %sub.i = sub nsw i32 0, %val.2.i
   %retval.0.i = select i1 %cond, i32 %val.2.i, i32 %sub.i
   %cmp1 = icmp eq i32 %retval.0.i, 0
   br i1 %cmp1, label %land.lhs.true, label %if.end11
 
 land.lhs.true:                                    ; preds = %num2long.exit
   ret i32 17
 

test/CodeGen/Hexagon/autohvx/isel-extractelt-illegal-type.ll

 ; RUN: llc -march=hexagon < %s | FileCheck %s
 
 ; Make sure this doesn't crash.
 ; CHECK: = mem
 
 target triple = "hexagon"
 
 ; Function Attrs: nounwind readnone
 declare i32 @llvm.hexagon.A2.subh.l16.sat.ll(i32, i32) #0
 
 ; Function Attrs: nounwind readonly
-define dso_local signext i16 @f0(i16* nocapture readonly %a0) local_unnamed_addr #1 {
+define dso_local signext i16 @f0(i16* nocapture readonly %a0, i16 %val) local_unnamed_addr #1 {
 b0:
   %v0 = load <8 x i16>, <8 x i16>* undef, align 2, !tbaa !0
   %v1 = shufflevector <8 x i16> %v0, <8 x i16> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
   %v2 = shufflevector <8 x i16> %v1, <8 x i16> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
   %v3 = lshr <16 x i16> %v2, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
   %v4 = and <16 x i16> %v3, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
   %v5 = extractelement <16 x i16> %v4, i32 0
   %v6 = sext i16 %v5 to i32
   %v7 = tail call i32 @llvm.hexagon.A2.subh.l16.sat.ll(i32 %v6, i32 16)
   %v8 = trunc i32 %v7 to i16
   %v9 = icmp sgt i16 %v8, -1
-  %v10 = select i1 %v9, i16 0, i16 undef
+  %v10 = select i1 %v9, i16 0, i16 %val
   ret i16 %v10
 }
 
 attributes #0 = { nounwind readnone }
 attributes #1 = { nounwind readonly "target-cpu"="hexagonv60" "target-features"="+hvx-length64b,+hvxv60" }
 
 !0 = !{!1, !1, i64 0}
 !1 = !{!"short", !2, i64 0}
 !2 = !{!"omnipotent char", !3, i64 0}
 !3 = !{!"Simple C/C++ TBAA"}

test/CodeGen/Hexagon/expand-vselect-kill.ll

 ; RUN: llc -march=hexagon -verify-machineinstrs < %s | FileCheck %s
 ;
 ; Check that this does not crash.
 
 target triple = "hexagon"
 
 ; CHECK-LABEL: danny:
-; CHECK-DAG: if ([[PREG:p[0-3]]]) [[VREG:v[0-9]+]]
-; CHECK-DAG: if (![[PREG]]) [[VREG]]
-define void @danny(i32 %a0) local_unnamed_addr #0 {
+; CHECK: if ([[PREG:p[0-3]]]) [[VREG:v[0-9]+]]
+define void @danny(i32 %a0, <16 x i32> %val) local_unnamed_addr #0 {
 b0:
   %v1 = icmp eq i32 0, %a0
-  %v2 = select i1 %v1, <16 x i32> zeroinitializer, <16 x i32> undef
+  %v2 = select i1 %v1, <16 x i32> zeroinitializer, <16 x i32> %val
   %v3 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v2, <16 x i32> zeroinitializer, i32 2)
   %v4 = tail call <32 x i32> @llvm.hexagon.V6.vswap(<512 x i1> undef, <16 x i32> undef, <16 x i32> %v3)
   %v5 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v4)
   %v6 = tail call <32 x i32> @llvm.hexagon.V6.vshuffvdd(<16 x i32> undef, <16 x i32> %v5, i32 62)
   %v7 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v6)
   store <16 x i32> %v7, <16 x i32>* undef, align 64
   unreachable
 }
 
 declare <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32>, <16 x i32>, i32) #2
 declare <32 x i32> @llvm.hexagon.V6.vswap(<512 x i1>, <16 x i32>, <16 x i32>) #2
 declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #2
 declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #2
 declare <32 x i32> @llvm.hexagon.V6.vshuffvdd(<16 x i32>, <16 x i32>, i32) #2
 
 ; CHECK-LABEL: sammy:
-; CHECK-DAG: if ([[PREG:p[0-3]]]) [[VREG:v[0-9]+]]
-; CHECK-DAG: if (![[PREG]]) [[VREG]]
-define void @sammy(i32 %a0) local_unnamed_addr #1 {
+; CHECK: if ([[PREG:p[0-3]]]) [[VREG:v[0-9]+]]
+define void @sammy(i32 %a0, <32 x i32> %val) local_unnamed_addr #1 {
 b0:
   %v1 = icmp eq i32 0, %a0
-  %v2 = select i1 %v1, <32 x i32> zeroinitializer, <32 x i32> undef
+  %v2 = select i1 %v1, <32 x i32> zeroinitializer, <32 x i32> %val
   %v3 = tail call <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32> %v2, <32 x i32> zeroinitializer, i32 2)
   %v4 = tail call <64 x i32> @llvm.hexagon.V6.vswap.128B(<1024 x i1> undef, <32 x i32> undef, <32 x i32> %v3)
   %v5 = tail call <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32> %v4)
   %v6 = tail call <64 x i32> @llvm.hexagon.V6.vshuffvdd.128B(<32 x i32> undef, <32 x i32> %v5, i32 62)
   %v7 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v6)
   store <32 x i32> %v7, <32 x i32>* undef, align 128
   unreachable
 }

test/CodeGen/Hexagon/swp-const-tc1.ll

 ; RUN: llc -march=hexagon -enable-pipeliner -enable-pipeliner-opt-size \
 ; RUN:     -verify-machineinstrs \
 ; RUN:     -enable-aa-sched-mi=false -hexagon-expand-condsets=0 \
 ; RUN:     < %s | FileCheck %s
 
 ; Disable expand-condsets because it will assert on undefined registers.
 
 ; Test that we change the CFG correctly for pipelined loops where the trip
 ; count is a compile-time constant, and the trip count is the same as the
 ; number of prolog blocks (i.e., stages).
 
 ; CHECK: memb(r{{[0-9]+}}+#0) =
 ; CHECK: memb(r{{[0-9]+}}+#0) =
 
 ; Function Attrs: nounwind optsize
-define void @f0() #0 {
+define void @f0(i32 %val) #0 {
 b0:
   br label %b1
 
 b1:                                               ; preds = %b5, %b0
   %v0 = load i16, i16* undef, align 2, !tbaa !0
   %v1 = sext i16 %v0 to i32
   %v2 = load i16, i16* undef, align 2, !tbaa !0
   %v3 = sext i16 %v2 to i32
   %v4 = and i32 %v1, 7
   %v5 = and i32 %v3, 7
   br label %b2
 
 b2:                                               ; preds = %b4, %b1
   br label %b3
 
 b3:                                               ; preds = %b3, %b2
   %v6 = phi i32 [ 0, %b2 ], [ %v22, %b3 ]
   %v7 = add i32 %v6, undef
   %v8 = icmp slt i32 undef, %v7
   %v9 = add nsw i32 %v7, 1
-  %v10 = select i1 undef, i32 undef, i32 %v9
+  %v10 = select i1 undef, i32 %val, i32 %v9
   %v11 = add i32 %v10, 0
   %v12 = getelementptr inbounds i8, i8* null, i32 %v11
   %v13 = load i8, i8* %v12, align 1, !tbaa !4
   %v14 = zext i8 %v13 to i32
   %v15 = mul i32 %v14, %v4
   %v16 = add i32 %v15, 0
   %v17 = mul i32 %v16, %v5
   %v18 = add i32 %v17, 32

test/CodeGen/X86/2012-08-07-CmpISelBug.ll

 ; RUN: llc < %s -mtriple=x86_64-apple-macosx | FileCheck %s
 
 ; Cmp lowering should not look past the truncate unless the high bits are known
 ; zero.
 ; rdar://12027825
 
-define void @foo(i8 %arg4, i32 %arg5, i32* %arg14) nounwind {
+define void @foo(i8 %arg4, i32 %arg5, i32* %arg14, i8 %val) nounwind {
 bb:
 ; CHECK-LABEL: foo:
 ; CHECK-NOT: testl
 ; CHECK: testb
   %tmp48 = zext i8 %arg4 to i32
   %tmp49 = and i32 %tmp48, 32
   %tmp50 = add i32 %tmp49, 1593371643
   %tmp55 = sub i32 %tmp50, 0
   %tmp56 = add i32 %tmp55, 7787538
   %tmp57 = xor i32 %tmp56, 1601159181
   %tmp58 = xor i32 %arg5, 1601159181
   %tmp59 = and i32 %tmp57, %tmp58
   %tmp60 = add i32 %tmp59, -1263900958
   %tmp67 = sub i32 %tmp60, 0
   %tmp103 = xor i32 %tmp56, 13
   %tmp104 = trunc i32 %tmp103 to i8
   %tmp105 = sub i8 0, %tmp104
   %tmp106 = add i8 %tmp105, -103
   %tmp113 = sub i8 %tmp106, 0
   %tmp114 = add i8 %tmp113, -72
   %tmp141 = icmp ne i32 %tmp67, -1263900958
-  %tmp142 = select i1 %tmp141, i8 %tmp114, i8 undef
+  %tmp142 = select i1 %tmp141, i8 %tmp114, i8 %val
   %tmp143 = xor i8 %tmp142, 81
   %tmp144 = zext i8 %tmp143 to i32
   %tmp145 = add i32 %tmp144, 2062143348
   %tmp152 = sub i32 %tmp145, 0
   store i32 %tmp152, i32* %arg14
   ret void
 }

test/CodeGen/X86/hoist-spill.ll

 ; RUN: llc < %s | FileCheck %s
 
 ; Check no spills to the same stack slot after hoisting.
 ; CHECK: mov{{.}} %{{.*}}, [[SPOFFSET1:-?[0-9]*]](%rsp)
 ; CHECK: mov{{.}} %{{.*}}, [[SPOFFSET2:-?[0-9]*]](%rsp)
 ; CHECK-NOT: mov{{.}} %{{.*}}, [[SPOFFSET1]](%rsp)
 ; CHECK-NOT: mov{{.}} %{{.*}}, [[SPOFFSET2]](%rsp)
 
 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-unknown-linux-gnu"
 
 @a = external global i32*, align 8
 @b = external global i32, align 4
 @d = external global i32*, align 8
 
 ; Function Attrs: norecurse noreturn nounwind uwtable
-define void @fn1(i32 %p1) {
+define void @fn1(i32 %p1, i32 %val0, i64 %val1) {
 entry:
   %tmp = load i32*, i32** @d, align 8
   %tmp1 = load i32*, i32** @a, align 8
   %tmp2 = sext i32 %p1 to i64
   br label %for.cond
 
 for.cond:                                         ; preds = %for.inc14, %entry
   %indvar = phi i32 [ %indvar.next, %for.inc14 ], [ 0, %entry ]
   %indvars.iv30.in = phi i32 [ %indvars.iv30, %for.inc14 ], [ %p1, %entry ]
   %c.0 = phi i32 [ %inc15, %for.inc14 ], [ 1, %entry ]
   %k.0 = phi i32 [ %k.1.lcssa, %for.inc14 ], [ undef, %entry ]
   %tmp3 = icmp sgt i32 undef, 0
-  %smax52 = select i1 %tmp3, i32 undef, i32 0
+  %smax52 = select i1 %tmp3, i32 %val0, i32 0
   %tmp4 = zext i32 %smax52 to i64
   %tmp5 = icmp sgt i64 undef, %tmp4
-  %smax53 = select i1 %tmp5, i64 undef, i64 %tmp4
+  %smax53 = select i1 %tmp5, i64 %val1, i64 %tmp4
   %tmp6 = add nsw i64 %smax53, 1
   %tmp7 = sub nsw i64 %tmp6, %tmp4
   %tmp8 = add nsw i64 %tmp7, -8
   %tmp9 = sub i32 undef, %indvar
   %tmp10 = icmp sgt i64 %tmp2, 0
   %smax40 = select i1 %tmp10, i64 %tmp2, i64 0
   %scevgep41 = getelementptr i32, i32* %tmp1, i64 %smax40
   %indvars.iv30 = add i32 %indvars.iv30.in, -1

test/CodeGen/X86/pr31045.ll

 ; CHECK-NEXT:    movsbl {{.*}}(%rip), %ecx
 ; CHECK-NEXT:    movzbl {{.*}}(%rip), %edx
 ; CHECK-NEXT:    andl $1, %eax
 ; CHECK-NEXT:    leal (%rax,%rax), %esi
 ; CHECK-NEXT:    subl %ecx, %esi
 ; CHECK-NEXT:    subl %edx, %esi
 ; CHECK-NEXT:    xorl %ecx, %ecx
 ; CHECK-NEXT:    testb %al, %al
-; CHECK-NEXT:    cmovel %eax, %ecx
-; CHECK-NEXT:    movzbl {{.*}}(%rip), %edx
-; CHECK-NEXT:    andl struct_obj_8+{{.*}}(%rip), %ecx
-; CHECK-NEXT:    andl $1, %ecx
-; CHECK-NEXT:    negl %ecx
-; CHECK-NEXT:    andl %edx, %ecx
-; CHECK-NEXT:    negl %ecx
-; CHECK-NEXT:    andl %eax, %ecx
-; CHECK-NEXT:    negl %ecx
-; CHECK-NEXT:    testl %ecx, %esi
+; CHECK-NEXT:    movl $33, %edx
+; CHECK-NEXT:    cmovnel %ecx, %edx
+; CHECK-NEXT:    movzbl {{.*}}(%rip), %ecx
+; CHECK-NEXT:    andl struct_obj_8+{{.*}}(%rip), %edx
+; CHECK-NEXT:    andl $1, %edx
+; CHECK-NEXT:    negl %edx
+; CHECK-NEXT:    andl %ecx, %edx
+; CHECK-NEXT:    negl %edx
+; CHECK-NEXT:    andl %eax, %edx
+; CHECK-NEXT:    negl %edx
+; CHECK-NEXT:    testl %edx, %esi
 ; CHECK-NEXT:    notl %esi
 ; CHECK-NEXT:    movzbl %sil, %eax
 ; CHECK-NEXT:    movw %ax, struct_obj_12+{{.*}}(%rip)
 ; CHECK-NEXT:    setne {{.*}}(%rip)
 ; CHECK-NEXT:    retq
 entry:
   %bf.load = load i32, i32* bitcast (i24* getelementptr inbounds (%struct.d.3.7.11.15.39.71.75.91.95.99.107.123.363, %struct.d.3.7.11.15.39.71.75.91.95.99.107.123.363* @struct_obj_3, i64 0, i32 0, i32 2) to i32*), align 2
   %tmp = load i8, i8* @var_46, align 1
entry:
   %or55 = or i32 %or, 0
   %conv56 = trunc i32 %or55 to i16
   %bf.value = and i16 %conv56, 255
   %bf.set = or i16 %bf.value, 0
   store i16 %bf.set, i16* getelementptr inbounds (%struct.c.2.6.10.14.38.70.74.90.94.98.106.122.362, %struct.c.2.6.10.14.38.70.74.90.94.98.106.122.362* @struct_obj_12, i64 0, i32 1, i32 1, i32 1), align 1
   %lnot = icmp eq i8 undef, 0
   %bf.load65 = load i32, i32* bitcast (i24* getelementptr inbounds (%struct.d.3.7.11.15.39.71.75.91.95.99.107.123.363, %struct.d.3.7.11.15.39.71.75.91.95.99.107.123.363* @struct_obj_8, i64 0, i32 0, i32 2) to i32*), align 2
   %tmp6 = and i32 %bf.load65, 1
-  %tmp7 = select i1 %lnot, i32 undef, i32 0
+  %tmp7 = select i1 %lnot, i32 33, i32 0
   %mul69 = and i32 %tmp6, %tmp7
   %tmp8 = sub nsw i32 0, %mul69
   %mul75 = and i32 %tmp5, %tmp8
   %tmp9 = and i32 %bf.load, 1
   %tmp10 = sub nsw i32 0, %mul75
   %mul80 = and i32 %tmp9, %tmp10
   %factor109 = shl nuw nsw i32 %tmp9, 1
   %sub86 = sub nsw i32 %factor109, %conv1

test/CodeGen/X86/pr32610.ll

 ; Function Attrs: norecurse nounwind optsize ssp
 define void @pr32610() local_unnamed_addr #0 {
 entry:
   %0 = load i32, i32* getelementptr ([1 x i32], [1 x i32]* @b, i32 0, i32 undef), align 4, !tbaa !1
   %cmp = icmp eq i32 undef, %0
   %conv = zext i1 %cmp to i32
   %tobool1.i = icmp ne i32 undef, 0
   %or.cond.i = and i1 %cmp, %tobool1.i
-  %cond.i = select i1 %or.cond.i, i32 %conv, i32 undef
+  %cond.i = select i1 %or.cond.i, i32 %conv, i32 33
   store i32 %cond.i, i32* @c, align 4, !tbaa !1
   %1 = load i32, i32* getelementptr inbounds ([1 x i32], [1 x i32]* @b, i32 0, i32 0), align 4
   %tobool = icmp ne i32 %1, 0
   %2 = select i1 %tobool, i32 %1, i32 undef
   store i32 %2, i32* @d, align 4, !tbaa !1
   ret void
 }