Index: lib/CodeGen/SelectionDAG/DAGCombiner.cpp =================================================================== --- lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -6758,6 +6758,12 @@ return !N0C->isNullValue() ? N1 : N2; } + if (N1.isUndef()) + return N2; + + if (N2.isUndef()) + return N1; + // fold (select X, X, Y) -> (or X, Y) // fold (select X, 1, Y) -> (or C, Y) if (VT == VT0 && VT == MVT::i1 && (N0 == N1 || isOneConstant(N1))) Index: test/CodeGen/AArch64/half.ll =================================================================== --- test/CodeGen/AArch64/half.ll +++ test/CodeGen/AArch64/half.ll @@ -82,14 +82,14 @@ ret void } -define i16 @test_fccmp(i1 %a) { +define i16 @test_fccmp(i1 %a, i16 %val0, i16 %val1) { ;CHECK-LABEL: test_fccmp: ;CHECK: fcmp %cmp0 = fcmp ogt half 0xH3333, undef %cmp1 = fcmp ogt half 0xH2222, undef - %x = select i1 %cmp0, i16 0, i16 undef + %x = select i1 %cmp0, i16 0, i16 %val0 %or = or i1 %cmp1, %cmp0 - %y = select i1 %or, i16 4, i16 undef + %y = select i1 %or, i16 4, i16 %val1 %r = add i16 %x, %y ret i16 %r } Index: test/CodeGen/AMDGPU/select-undef.ll =================================================================== --- /dev/null +++ test/CodeGen/AMDGPU/select-undef.ll @@ -0,0 +1,21 @@ +; RUN: llc -mtriple=amdgcn-amd-amdhsa < %s | FileCheck -check-prefix=GCN %s + +; GCN-LABEL: {{^}}select_undef_lhs: +; GCN: s_waitcnt +; GCN-NEXT: s_setpc_b64 +define float @select_undef_lhs(float %val, i1 %cond) { + %undef = call float @llvm.amdgcn.image.sample.f32.v2f32.v8i32(<2 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 0, i1 0, i1 0, i1 0, i1 0, i1 0) + %sel = select i1 %cond, float %undef, float %val + ret float %sel +} + +; GCN-LABEL: {{^}}select_undef_rhs: +; GCN: s_waitcnt +; GCN-NEXT: s_setpc_b64 +define float @select_undef_rhs(float %val, i1 %cond) { + %undef = call float @llvm.amdgcn.image.sample.f32.v2f32.v8i32(<2 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 0, i1 0, i1 0, i1 0, i1 0, i1 0) + %sel = select i1 %cond, float %val, float %undef + ret float %sel +} + +declare float @llvm.amdgcn.image.sample.f32.v2f32.v8i32(<2 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #0 Index: test/CodeGen/ARM/sub-cmp-peephole.ll =================================================================== --- test/CodeGen/ARM/sub-cmp-peephole.ll +++ test/CodeGen/ARM/sub-cmp-peephole.ll @@ -73,9 +73,9 @@ ; CHECK: bc_raise ; CHECK: rsbeq ; CHECK: cmp -define i32 @bc_raise(i1 %cond) nounwind ssp { +define i32 @bc_raise(i1 %cond, i32 %val) nounwind ssp { entry: - %val.2.i = select i1 %cond, i32 0, i32 undef + %val.2.i = select i1 %cond, i32 0, i32 %val %sub.i = sub nsw i32 0, %val.2.i %retval.0.i = select i1 %cond, i32 %val.2.i, i32 %sub.i %cmp1 = icmp eq i32 %retval.0.i, 0 Index: test/CodeGen/Hexagon/autohvx/isel-extractelt-illegal-type.ll =================================================================== --- test/CodeGen/Hexagon/autohvx/isel-extractelt-illegal-type.ll +++ test/CodeGen/Hexagon/autohvx/isel-extractelt-illegal-type.ll @@ -9,7 +9,7 @@ declare i32 @llvm.hexagon.A2.subh.l16.sat.ll(i32, i32) #0 ; Function Attrs: nounwind readonly -define dso_local signext i16 @f0(i16* nocapture readonly %a0) local_unnamed_addr #1 { +define dso_local signext i16 @f0(i16* nocapture readonly %a0, i16 %val) local_unnamed_addr #1 { b0: %v0 = load <8 x i16>, <8 x i16>* undef, align 2, !tbaa !0 %v1 = shufflevector <8 x i16> %v0, <8 x i16> undef, <8 x i32> @@ -21,7 +21,7 @@ %v7 = tail call i32 @llvm.hexagon.A2.subh.l16.sat.ll(i32 %v6, i32 16) %v8 = trunc i32 %v7 to i16 %v9 = icmp sgt i16 %v8, -1 - %v10 = select i1 %v9, i16 0, i16 undef + %v10 = select i1 %v9, i16 0, i16 %val ret i16 %v10 } Index: test/CodeGen/Hexagon/expand-vselect-kill.ll =================================================================== --- test/CodeGen/Hexagon/expand-vselect-kill.ll +++ test/CodeGen/Hexagon/expand-vselect-kill.ll @@ -5,12 +5,11 @@ target triple = "hexagon" ; CHECK-LABEL: danny: -; CHECK-DAG: if ([[PREG:p[0-3]]]) [[VREG:v[0-9]+]] -; CHECK-DAG: if (![[PREG]]) [[VREG]] -define void @danny(i32 %a0) local_unnamed_addr #0 { +; CHECK: if ([[PREG:p[0-3]]]) [[VREG:v[0-9]+]] +define void @danny(i32 %a0, <16 x i32> %val) local_unnamed_addr #0 { b0: %v1 = icmp eq i32 0, %a0 - %v2 = select i1 %v1, <16 x i32> zeroinitializer, <16 x i32> undef + %v2 = select i1 %v1, <16 x i32> zeroinitializer, <16 x i32> %val %v3 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v2, <16 x i32> zeroinitializer, i32 2) %v4 = tail call <32 x i32> @llvm.hexagon.V6.vswap(<512 x i1> undef, <16 x i32> undef, <16 x i32> %v3) %v5 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v4) @@ -27,12 +26,11 @@ declare <32 x i32> @llvm.hexagon.V6.vshuffvdd(<16 x i32>, <16 x i32>, i32) #2 ; CHECK-LABEL: sammy: -; CHECK-DAG: if ([[PREG:p[0-3]]]) [[VREG:v[0-9]+]] -; CHECK-DAG: if (![[PREG]]) [[VREG]] -define void @sammy(i32 %a0) local_unnamed_addr #1 { +; CHECK: if ([[PREG:p[0-3]]]) [[VREG:v[0-9]+]] +define void @sammy(i32 %a0, <32 x i32> %val) local_unnamed_addr #1 { b0: %v1 = icmp eq i32 0, %a0 - %v2 = select i1 %v1, <32 x i32> zeroinitializer, <32 x i32> undef + %v2 = select i1 %v1, <32 x i32> zeroinitializer, <32 x i32> %val %v3 = tail call <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32> %v2, <32 x i32> zeroinitializer, i32 2) %v4 = tail call <64 x i32> @llvm.hexagon.V6.vswap.128B(<1024 x i1> undef, <32 x i32> undef, <32 x i32> %v3) %v5 = tail call <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32> %v4) Index: test/CodeGen/Hexagon/swp-const-tc1.ll =================================================================== --- test/CodeGen/Hexagon/swp-const-tc1.ll +++ test/CodeGen/Hexagon/swp-const-tc1.ll @@ -13,7 +13,7 @@ ; CHECK: memb(r{{[0-9]+}}+#0) = ; Function Attrs: nounwind optsize -define void @f0() #0 { +define void @f0(i32 %val) #0 { b0: br label %b1 @@ -34,7 +34,7 @@ %v7 = add i32 %v6, undef %v8 = icmp slt i32 undef, %v7 %v9 = add nsw i32 %v7, 1 - %v10 = select i1 undef, i32 undef, i32 %v9 + %v10 = select i1 undef, i32 %val, i32 %v9 %v11 = add i32 %v10, 0 %v12 = getelementptr inbounds i8, i8* null, i32 %v11 %v13 = load i8, i8* %v12, align 1, !tbaa !4 Index: test/CodeGen/X86/2012-08-07-CmpISelBug.ll =================================================================== --- test/CodeGen/X86/2012-08-07-CmpISelBug.ll +++ test/CodeGen/X86/2012-08-07-CmpISelBug.ll @@ -4,7 +4,7 @@ ; zero. ; rdar://12027825 -define void @foo(i8 %arg4, i32 %arg5, i32* %arg14) nounwind { +define void @foo(i8 %arg4, i32 %arg5, i32* %arg14, i8 %val) nounwind { bb: ; CHECK-LABEL: foo: ; CHECK-NOT: testl @@ -26,7 +26,7 @@ %tmp113 = sub i8 %tmp106, 0 %tmp114 = add i8 %tmp113, -72 %tmp141 = icmp ne i32 %tmp67, -1263900958 - %tmp142 = select i1 %tmp141, i8 %tmp114, i8 undef + %tmp142 = select i1 %tmp141, i8 %tmp114, i8 %val %tmp143 = xor i8 %tmp142, 81 %tmp144 = zext i8 %tmp143 to i32 %tmp145 = add i32 %tmp144, 2062143348 Index: test/CodeGen/X86/hoist-spill.ll =================================================================== --- test/CodeGen/X86/hoist-spill.ll +++ test/CodeGen/X86/hoist-spill.ll @@ -14,7 +14,7 @@ @d = external global i32*, align 8 ; Function Attrs: norecurse noreturn nounwind uwtable -define void @fn1(i32 %p1) { +define void @fn1(i32 %p1, i32 %val0, i64 %val1) { entry: %tmp = load i32*, i32** @d, align 8 %tmp1 = load i32*, i32** @a, align 8 @@ -27,10 +27,10 @@ %c.0 = phi i32 [ %inc15, %for.inc14 ], [ 1, %entry ] %k.0 = phi i32 [ %k.1.lcssa, %for.inc14 ], [ undef, %entry ] %tmp3 = icmp sgt i32 undef, 0 - %smax52 = select i1 %tmp3, i32 undef, i32 0 + %smax52 = select i1 %tmp3, i32 %val0, i32 0 %tmp4 = zext i32 %smax52 to i64 %tmp5 = icmp sgt i64 undef, %tmp4 - %smax53 = select i1 %tmp5, i64 undef, i64 %tmp4 + %smax53 = select i1 %tmp5, i64 %val1, i64 %tmp4 %tmp6 = add nsw i64 %smax53, 1 %tmp7 = sub nsw i64 %tmp6, %tmp4 %tmp8 = add nsw i64 %tmp7, -8 Index: test/CodeGen/X86/pr31045.ll =================================================================== --- test/CodeGen/X86/pr31045.ll +++ test/CodeGen/X86/pr31045.ll @@ -27,16 +27,17 @@ ; CHECK-NEXT: subl %edx, %esi ; CHECK-NEXT: xorl %ecx, %ecx ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: cmovel %eax, %ecx -; CHECK-NEXT: movzbl {{.*}}(%rip), %edx -; CHECK-NEXT: andl struct_obj_8+{{.*}}(%rip), %ecx -; CHECK-NEXT: andl $1, %ecx -; CHECK-NEXT: negl %ecx -; CHECK-NEXT: andl %edx, %ecx -; CHECK-NEXT: negl %ecx -; CHECK-NEXT: andl %eax, %ecx -; CHECK-NEXT: negl %ecx -; CHECK-NEXT: testl %ecx, %esi +; CHECK-NEXT: movl $33, %edx +; CHECK-NEXT: cmovnel %ecx, %edx +; CHECK-NEXT: movzbl {{.*}}(%rip), %ecx +; CHECK-NEXT: andl struct_obj_8+{{.*}}(%rip), %edx +; CHECK-NEXT: andl $1, %edx +; CHECK-NEXT: negl %edx +; CHECK-NEXT: andl %ecx, %edx +; CHECK-NEXT: negl %edx +; CHECK-NEXT: andl %eax, %edx +; CHECK-NEXT: negl %edx +; CHECK-NEXT: testl %edx, %esi ; CHECK-NEXT: notl %esi ; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: movw %ax, struct_obj_12+{{.*}}(%rip) @@ -67,7 +68,7 @@ %lnot = icmp eq i8 undef, 0 %bf.load65 = load i32, i32* bitcast (i24* getelementptr inbounds (%struct.d.3.7.11.15.39.71.75.91.95.99.107.123.363, %struct.d.3.7.11.15.39.71.75.91.95.99.107.123.363* @struct_obj_8, i64 0, i32 0, i32 2) to i32*), align 2 %tmp6 = and i32 %bf.load65, 1 - %tmp7 = select i1 %lnot, i32 undef, i32 0 + %tmp7 = select i1 %lnot, i32 33, i32 0 %mul69 = and i32 %tmp6, %tmp7 %tmp8 = sub nsw i32 0, %mul69 %mul75 = and i32 %tmp5, %tmp8 Index: test/CodeGen/X86/pr32610.ll =================================================================== --- test/CodeGen/X86/pr32610.ll +++ test/CodeGen/X86/pr32610.ll @@ -20,7 +20,7 @@ %conv = zext i1 %cmp to i32 %tobool1.i = icmp ne i32 undef, 0 %or.cond.i = and i1 %cmp, %tobool1.i - %cond.i = select i1 %or.cond.i, i32 %conv, i32 undef + %cond.i = select i1 %or.cond.i, i32 %conv, i32 33 store i32 %cond.i, i32* @c, align 4, !tbaa !1 %1 = load i32, i32* getelementptr inbounds ([1 x i32], [1 x i32]* @b, i32 0, i32 0), align 4 %tobool = icmp ne i32 %1, 0