Index: include/llvm/Transforms/Utils/BasicBlockUtils.h =================================================================== --- include/llvm/Transforms/Utils/BasicBlockUtils.h +++ include/llvm/Transforms/Utils/BasicBlockUtils.h @@ -58,7 +58,8 @@ /// value indicates success or failure. bool MergeBlockIntoPredecessor(BasicBlock *BB, DominatorTree *DT = nullptr, LoopInfo *LI = nullptr, - MemoryDependenceResults *MemDep = nullptr); + MemoryDependenceResults *MemDep = nullptr, + DeferredDominance *DDT = nullptr); /// Replace all uses of an instruction (specified by BI) with a value, then /// remove and delete the original instruction. Index: lib/CodeGen/CodeGenPrepare.cpp =================================================================== --- lib/CodeGen/CodeGenPrepare.cpp +++ lib/CodeGen/CodeGenPrepare.cpp @@ -516,8 +516,16 @@ bool CodeGenPrepare::eliminateFallThrough(Function &F) { bool Changed = false; // Scan all of the blocks in the function, except for the entry block. - for (Function::iterator I = std::next(F.begin()), E = F.end(); I != E;) { - BasicBlock *BB = &*I++; + // Use a temporary array to avoid iterator being invalidated when + // deleting blocks. + SmallVector Blocks; + for (Function::iterator I = std::next(F.begin()), E = F.end(); I != E;) + Blocks.push_back(&*I++); + + for (auto &Block : Blocks) { + auto *BB = cast_or_null(Block); + if (!BB) + continue; // If the destination block has a single pred, then this is a trivial // edge, just collapse it. BasicBlock *SinglePred = BB->getSinglePredecessor(); @@ -528,17 +536,10 @@ BranchInst *Term = dyn_cast(SinglePred->getTerminator()); if (Term && !Term->isConditional()) { Changed = true; - LLVM_DEBUG(dbgs() << "To merge:\n" << *SinglePred << "\n\n\n"); - // Remember if SinglePred was the entry block of the function. - // If so, we will need to move BB back to the entry position. - bool isEntry = SinglePred == &SinglePred->getParent()->getEntryBlock(); - MergeBasicBlockIntoOnlyPred(BB, nullptr); - - if (isEntry && BB != &BB->getParent()->getEntryBlock()) - BB->moveBefore(&BB->getParent()->getEntryBlock()); + LLVM_DEBUG(dbgs() << "To merge:\n" << *BB << "\n\n\n"); - // We have erased a block. Update the iterator. - I = BB->getIterator(); + // Merge BB into SinglePred and delete it. + MergeBlockIntoPredecessor(BB); } } return Changed; @@ -591,9 +592,18 @@ } bool MadeChange = false; + // Copy blocks into a temporary array to avoid iterator invalidation issues + // as we remove them. // Note that this intentionally skips the entry block. - for (Function::iterator I = std::next(F.begin()), E = F.end(); I != E;) { - BasicBlock *BB = &*I++; + // FIXME: use one line initializer? + SmallVector Blocks; + for (Function::iterator I = std::next(F.begin()), E = F.end(); I != E;) + Blocks.push_back(&*I++); + + for (auto &Block : Blocks) { + BasicBlock *BB = cast_or_null(Block); + if (!BB) + continue; BasicBlock *DestBB = findDestBlockOfMergeableEmptyBlock(BB); if (!DestBB || !isMergingEmptyBlockProfitable(BB, DestBB, Preheaders.count(BB))) @@ -762,15 +772,12 @@ // just collapse it. if (BasicBlock *SinglePred = DestBB->getSinglePredecessor()) { if (SinglePred != DestBB) { - // Remember if SinglePred was the entry block of the function. If so, we - // will need to move BB back to the entry position. - bool isEntry = SinglePred == &SinglePred->getParent()->getEntryBlock(); - MergeBasicBlockIntoOnlyPred(DestBB, nullptr); - - if (isEntry && BB != &BB->getParent()->getEntryBlock()) - BB->moveBefore(&BB->getParent()->getEntryBlock()); - - LLVM_DEBUG(dbgs() << "AFTER:\n" << *DestBB << "\n\n\n"); + assert(SinglePred == BB && + "Single predecessor not the same as predecessor"); + // Merge DestBB into SinglePred/BB and delete it. + MergeBlockIntoPredecessor(DestBB); + // Note: BB will not be deleted on this path, its single predecessor will. + LLVM_DEBUG(dbgs() << "AFTER:\n" << *SinglePred << "\n\n\n"); return; } } Index: lib/Transforms/Scalar/LoopSimplifyCFG.cpp =================================================================== --- lib/Transforms/Scalar/LoopSimplifyCFG.cpp +++ lib/Transforms/Scalar/LoopSimplifyCFG.cpp @@ -27,11 +27,12 @@ #include "llvm/Analysis/ScalarEvolution.h" #include "llvm/Analysis/ScalarEvolutionAliasAnalysis.h" #include "llvm/Analysis/TargetTransformInfo.h" -#include "llvm/Transforms/Utils/Local.h" #include "llvm/IR/Dominators.h" #include "llvm/Transforms/Scalar.h" #include "llvm/Transforms/Scalar/LoopPassManager.h" #include "llvm/Transforms/Utils.h" +#include "llvm/Transforms/Utils/BasicBlockUtils.h" +#include "llvm/Transforms/Utils/Local.h" #include "llvm/Transforms/Utils/LoopUtils.h" using namespace llvm; @@ -55,11 +56,8 @@ if (!Pred || !Pred->getSingleSuccessor() || LI.getLoopFor(Pred) != &L) continue; - // Pred is going to disappear, so we need to update the loop info. - if (L.getHeader() == Pred) - L.moveToHeader(Succ); - LI.removeBlock(Pred); - MergeBasicBlockIntoOnlyPred(Succ, &DT); + // Merge Succ into Pred and delete it. + MergeBlockIntoPredecessor(Succ, &DT, &LI); SE.forgetLoop(&L); Changed = true; Index: lib/Transforms/Utils/BasicBlockUtils.cpp =================================================================== --- lib/Transforms/Utils/BasicBlockUtils.cpp +++ lib/Transforms/Utils/BasicBlockUtils.cpp @@ -117,9 +117,12 @@ bool llvm::MergeBlockIntoPredecessor(BasicBlock *BB, DominatorTree *DT, LoopInfo *LI, - MemoryDependenceResults *MemDep) { - // Don't merge away blocks who have their address taken. - if (BB->hasAddressTaken()) return false; + MemoryDependenceResults *MemDep, + DeferredDominance *DDT) { + assert(!(DT && DDT) && "Cannot call with both DT and DDT."); + + if (BB->hasAddressTaken()) + return false; // Can't merge if there are multiple predecessors, or no predecessors. BasicBlock *PredBB = BB->getUniquePredecessor(); @@ -131,16 +134,8 @@ if (PredBB->getTerminator()->isExceptional()) return false; - succ_iterator SI(succ_begin(PredBB)), SE(succ_end(PredBB)); - BasicBlock *OnlySucc = BB; - for (; SI != SE; ++SI) - if (*SI != OnlySucc) { - OnlySucc = nullptr; // There are multiple distinct successors! - break; - } - - // Can't merge if there are multiple successors. - if (!OnlySucc) return false; + // Can't merge if there are multiple distinct successors. + if (PredBB->getUniqueSuccessor() != BB) return false; // Can't merge if there is PHI loop. for (PHINode &PN : BB->phis()) @@ -158,6 +153,18 @@ FoldSingleEntryPHINodes(BB, MemDep); } + // Deferred DT update: Collect all the edges that exit BB. These + // dominator edges will be redirected from Pred. + std::vector Updates; + if (DDT) { + Updates.reserve(1 + (2 * succ_size(BB))); + Updates.push_back({DominatorTree::Delete, PredBB, BB}); + for (auto I = succ_begin(BB), E = succ_end(BB); I != E; ++I) { + Updates.push_back({DominatorTree::Delete, BB, *I}); + Updates.push_back({DominatorTree::Insert, PredBB, *I}); + } + } + // Delete the unconditional branch from the predecessor... PredBB->getInstList().pop_back(); @@ -204,7 +211,12 @@ if (MemDep) MemDep->invalidateCachedPredecessors(); - BB->eraseFromParent(); + if (DDT) { + DDT->deleteBB(BB); // Deferred deletion of BB. + DDT->applyUpdates(Updates); + } else { + BB->eraseFromParent(); // Nuke BB. + } return true; } Index: test/CodeGen/AMDGPU/branch-relaxation.ll =================================================================== --- test/CodeGen/AMDGPU/branch-relaxation.ll +++ test/CodeGen/AMDGPU/branch-relaxation.ll @@ -441,7 +441,7 @@ ; GCN-NEXT: s_xor_b64 exec, exec, [[TEMP_MASK1]] ; GCN-NEXT: ; mask branch [[RET:BB[0-9]+_[0-9]+]] -; GCN: [[LOOP_BODY:BB[0-9]+_[0-9]+]]: ; %loop_body +; GCN: [[LOOP_BODY:BB[0-9]+_[0-9]+]]: ; %loop ; GCN: ;;#ASMSTART ; GCN: v_nop_e64 ; GCN: v_nop_e64 @@ -452,7 +452,7 @@ ; GCN: ;;#ASMEND ; GCN: s_cbranch_vccz [[RET]] -; GCN-NEXT: [[LONGBB:BB[0-9]+_[0-9]+]]: ; %loop_body +; GCN-NEXT: [[LONGBB:BB[0-9]+_[0-9]+]]: ; %loop ; GCN-NEXT: ; in Loop: Header=[[LOOP_BODY]] Depth=1 ; GCN-NEXT: s_getpc_b64 vcc ; GCN-NEXT: s_sub_u32 vcc_lo, vcc_lo, ([[LONGBB]]+4)-[[LOOP_BODY]] Index: test/CodeGen/AMDGPU/nested-loop-conditions.ll =================================================================== --- test/CodeGen/AMDGPU/nested-loop-conditions.ll +++ test/CodeGen/AMDGPU/nested-loop-conditions.ll @@ -59,12 +59,12 @@ ; GCN-LABEL: {{^}}reduced_nested_loop_conditions: -; GCN: s_cmp_eq_u32 s{{[0-9]+}}, 1 -; GCN-NEXT: s_cbranch_scc1 +; GCN: s_cmp_lg_u32 s{{[0-9]+}}, 1 +; GCN-NEXT: s_cbranch_scc0 ; FIXME: Should fold to unconditional branch? ; GCN: ; implicit-def -; GCN: s_cbranch_vccz +; GCN: s_cbranch_vccnz ; GCN: ds_read_b32 Index: test/CodeGen/AMDGPU/si-annotate-cf.ll =================================================================== --- test/CodeGen/AMDGPU/si-annotate-cf.ll +++ test/CodeGen/AMDGPU/si-annotate-cf.ll @@ -89,11 +89,11 @@ ; This broke the old AMDIL cfg structurizer ; FUNC-LABEL: {{^}}loop_land_info_assert: -; SI: s_cmp_gt_i32 -; SI-NEXT: s_cbranch_scc0 [[ENDPGM:BB[0-9]+_[0-9]+]] +; SI: s_cmp_lt_i32 +; SI-NEXT: s_cbranch_scc1 [[ENDPGM:BB[0-9]+_[0-9]+]] -; SI: s_cmpk_gt_i32 -; SI-NEXT: s_cbranch_scc1 [[ENDPGM]] +; SI: s_cmpk_lt_i32 +; SI-NEXT: s_cbranch_scc0 [[ENDPGM]] ; SI: [[INFLOOP:BB[0-9]+_[0-9]+]] ; SI: s_cbranch_vccnz [[INFLOOP]] Index: test/CodeGen/ARM/indirectbr.ll =================================================================== --- test/CodeGen/ARM/indirectbr.ll +++ test/CodeGen/ARM/indirectbr.ll @@ -47,7 +47,7 @@ br label %L2 L2: ; preds = %L3, %bb2 -; THUMB-LABEL: %L1.clone +; THUMB-LABEL: %.split4 ; THUMB: muls %res.2 = phi i32 [ %res.1, %L3 ], [ 1, %bb2 ] ; [#uses=1] %phitmp = mul i32 %res.2, 6 ; [#uses=1] Index: test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll =================================================================== --- test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll +++ test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll @@ -160,7 +160,7 @@ ; Validate with memcmp()?: define signext i32 @equalityFoldTwoConstants() { ; CHECK-LABEL: equalityFoldTwoConstants: -; CHECK: # %bb.0: # %endblock +; CHECK: # %bb.0: # %loadbb ; CHECK-NEXT: li 3, 1 ; CHECK-NEXT: blr %call = tail call signext i32 @memcmp(i8* bitcast ([15 x i32]* @zeroEqualityTest04.buffer1 to i8*), i8* bitcast ([15 x i32]* @zeroEqualityTest04.buffer2 to i8*), i64 16) Index: test/CodeGen/PowerPC/memcmp-mergeexpand.ll =================================================================== --- test/CodeGen/PowerPC/memcmp-mergeexpand.ll +++ test/CodeGen/PowerPC/memcmp-mergeexpand.ll @@ -7,7 +7,7 @@ define zeroext i1 @opeq1( ; PPC64LE-LABEL: opeq1: -; PPC64LE: # %bb.0: # %opeq1.exit +; PPC64LE: # %bb.0: # %entry ; PPC64LE-NEXT: ld 3, 0(3) ; PPC64LE-NEXT: ld 4, 0(4) ; PPC64LE-NEXT: xor 3, 3, 4 Index: test/CodeGen/PowerPC/ppc-shrink-wrapping.ll =================================================================== --- test/CodeGen/PowerPC/ppc-shrink-wrapping.ll +++ test/CodeGen/PowerPC/ppc-shrink-wrapping.ll @@ -169,7 +169,7 @@ ; CHECK-NEXT: bne 0, .[[LOOP]] ; ; Next BB -; CHECK: %for.end +; CHECK: %for.exit ; CHECK: mtlr {{[0-9]+}} ; CHECK-NEXT: blr define i32 @freqSaveAndRestoreOutsideLoop2(i32 %cond) { Index: test/CodeGen/PowerPC/simplifyConstCmpToISEL.ll =================================================================== --- test/CodeGen/PowerPC/simplifyConstCmpToISEL.ll +++ test/CodeGen/PowerPC/simplifyConstCmpToISEL.ll @@ -3,7 +3,7 @@ ; RUN: -ppc-convert-rr-to-ri -verify-machineinstrs | FileCheck %s define void @test(i32 zeroext %parts) { ; CHECK-LABEL: test: -; CHECK: # %bb.0: # %cond.end.i +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cmplwi 0, 3, 1 ; CHECK-NEXT: bnelr+ 0 ; CHECK-NEXT: # %bb.1: # %test2.exit.us.unr-lcssa Index: test/CodeGen/Thumb2/2010-11-22-EpilogueBug.ll =================================================================== --- test/CodeGen/Thumb2/2010-11-22-EpilogueBug.ll +++ test/CodeGen/Thumb2/2010-11-22-EpilogueBug.ll @@ -25,7 +25,7 @@ br i1 undef, label %return, label %bb return: -; CHECK: %return +; CHECK: %bb3 ; 'mov sp, r7' would have left sp in an invalid state ; CHECK-NOT: mov sp, r7 ; CHECK-NOT: sub, sp, #4 Index: test/CodeGen/Thumb2/thumb2-jtb.ll =================================================================== --- test/CodeGen/Thumb2/thumb2-jtb.ll +++ test/CodeGen/Thumb2/thumb2-jtb.ll @@ -14,9 +14,6 @@ entry: br i1 %b, label %codeRepl127.exitStub, label %newFuncRoot -newFuncRoot: - br label %_getopt_internal.exit.ce - codeRepl127.exitStub: ; preds = %_getopt_internal.exit.ce ; Add an explicit edge back to before the jump table to ensure this block ; is placed first. @@ -103,6 +100,9 @@ codeRepl103.exitStub: ; preds = %_getopt_internal.exit.ce ret i16 26 +newFuncRoot: + br label %_getopt_internal.exit.ce + _getopt_internal.exit.ce: ; preds = %newFuncRoot switch i32 %0, label %codeRepl127.exitStub [ i32 -1, label %parse_options.exit.loopexit.exitStub Index: test/CodeGen/X86/2006-11-17-IllegalMove.ll =================================================================== --- test/CodeGen/X86/2006-11-17-IllegalMove.ll +++ test/CodeGen/X86/2006-11-17-IllegalMove.ll @@ -6,9 +6,9 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: movl 0, %eax ; CHECK-NEXT: decl %eax -; CHECK-NEXT: cmpl $2, %eax -; CHECK-NEXT: jae .LBB0_2 -; CHECK-NEXT: # %bb.1: # %cond_next129 +; CHECK-NEXT: cmpl $1, %eax +; CHECK-NEXT: ja .LBB0_2 +; CHECK-NEXT: # %bb.1: # %bb77 ; CHECK-NEXT: movb 0, %al ; CHECK-NEXT: movzbl %al, %eax ; CHECK-NEXT: # kill: def $eax killed $eax def $ax Index: test/CodeGen/X86/avx-cmp.ll =================================================================== --- test/CodeGen/X86/avx-cmp.ll +++ test/CodeGen/X86/avx-cmp.ll @@ -26,12 +26,15 @@ define void @render() nounwind { ; CHECK-LABEL: render: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: pushq %rbp ; CHECK-NEXT: pushq %rbx +; CHECK-NEXT: pushq %rax ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: jne .LBB2_6 ; CHECK-NEXT: # %bb.1: # %for.cond5.preheader ; CHECK-NEXT: xorl %ebx, %ebx +; CHECK-NEXT: movb $1, %bpl ; CHECK-NEXT: jmp .LBB2_2 ; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .LBB2_5: # %if.then @@ -43,8 +46,8 @@ ; CHECK-NEXT: jne .LBB2_2 ; CHECK-NEXT: # %bb.3: # %for.cond5 ; CHECK-NEXT: # in Loop: Header=BB2_2 Depth=1 -; CHECK-NEXT: testb %bl, %bl -; CHECK-NEXT: je .LBB2_2 +; CHECK-NEXT: testb %bpl, %bpl +; CHECK-NEXT: jne .LBB2_2 ; CHECK-NEXT: # %bb.4: # %for.body33 ; CHECK-NEXT: # in Loop: Header=BB2_2 Depth=1 ; CHECK-NEXT: vucomisd {{\.LCPI.*}}, %xmm0 @@ -52,7 +55,9 @@ ; CHECK-NEXT: jp .LBB2_5 ; CHECK-NEXT: jmp .LBB2_2 ; CHECK-NEXT: .LBB2_6: # %for.end52 +; CHECK-NEXT: addq $8, %rsp ; CHECK-NEXT: popq %rbx +; CHECK-NEXT: popq %rbp ; CHECK-NEXT: retq entry: br i1 undef, label %for.cond5, label %for.end52 Index: test/CodeGen/X86/avx-splat.ll =================================================================== --- test/CodeGen/X86/avx-splat.ll +++ test/CodeGen/X86/avx-splat.ll @@ -58,7 +58,7 @@ ; define <8 x float> @funcE() nounwind { ; CHECK-LABEL: funcE: -; CHECK: # %bb.0: # %for_exit499 +; CHECK: # %bb.0: # %allocas ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: # implicit-def: $ymm0 Index: test/CodeGen/X86/avx2-vbroadcast.ll =================================================================== --- test/CodeGen/X86/avx2-vbroadcast.ll +++ test/CodeGen/X86/avx2-vbroadcast.ll @@ -686,7 +686,7 @@ ; X32-NEXT: ## %bb.2: ## %ret ; X32-NEXT: retl ; X32-NEXT: .p2align 4, 0x90 -; X32-NEXT: LBB33_1: ## %footer349VF +; X32-NEXT: LBB33_1: ## %footer329VF ; X32-NEXT: ## =>This Inner Loop Header: Depth=1 ; X32-NEXT: jmp LBB33_1 ; @@ -698,7 +698,7 @@ ; X64-NEXT: ## %bb.2: ## %ret ; X64-NEXT: retq ; X64-NEXT: .p2align 4, 0x90 -; X64-NEXT: LBB33_1: ## %footer349VF +; X64-NEXT: LBB33_1: ## %footer329VF ; X64-NEXT: ## =>This Inner Loop Header: Depth=1 ; X64-NEXT: jmp LBB33_1 WGLoopsEntry: Index: test/CodeGen/X86/avx512-i1test.ll =================================================================== --- test/CodeGen/X86/avx512-i1test.ll +++ test/CodeGen/X86/avx512-i1test.ll @@ -7,7 +7,7 @@ define void @func() { ; CHECK-LABEL: func: -; CHECK: # %bb.0: # %L_10 +; CHECK: # %bb.0: # %bb1 ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: je .LBB0_1 @@ -70,7 +70,7 @@ ; CHECK-NEXT: je .LBB1_1 ; CHECK-NEXT: # %bb.2: # %if.then ; CHECK-NEXT: jmp bar # TAILCALL -; CHECK-NEXT: .LBB1_1: # %return +; CHECK-NEXT: .LBB1_1: # %if.end ; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: orq $-2, %rax ; CHECK-NEXT: retq Index: test/CodeGen/X86/block-placement.ll =================================================================== --- test/CodeGen/X86/block-placement.ll +++ test/CodeGen/X86/block-placement.ll @@ -317,7 +317,7 @@ ; a function. This is a gross CFG reduced out of the single source GCC. ; CHECK-LABEL: unnatural_cfg1 ; CHECK: %entry -; CHECK: %loop.body1 +; CHECK: %loop.header ; CHECK: %loop.body2 ; CHECK: %loop.body3 @@ -611,7 +611,7 @@ ; CHECK-LABEL: test_unnatural_cfg_backwards_inner_loop ; CHECK: %entry ; CHECK: %loop2b -; CHECK: %loop1 +; CHECK: %loop3 entry: br i1 undef, label %loop2a, label %body Index: test/CodeGen/X86/hoist-spill.ll =================================================================== --- test/CodeGen/X86/hoist-spill.ll +++ test/CodeGen/X86/hoist-spill.ll @@ -48,9 +48,6 @@ %cmp326 = icmp sgt i32 %k.0, %p1 br i1 %cmp326, label %for.cond4.preheader, label %for.body.preheader -for.body.preheader: ; preds = %for.cond - br label %for.body - for.cond4.preheader: ; preds = %for.body, %for.cond %k.1.lcssa = phi i32 [ %k.0, %for.cond ], [ %add, %for.body ] %cmp528 = icmp sgt i32 %sub., %p1 @@ -95,6 +92,9 @@ middle.block: ; preds = %vector.body, %vector.body.preheader.split br i1 undef, label %for.inc14, label %for.body6 +for.body.preheader: ; preds = %for.cond + br label %for.body + for.body: ; preds = %for.body, %for.body.preheader %k.127 = phi i32 [ %k.0, %for.body.preheader ], [ %add, %for.body ] %add = add nsw i32 %k.127, 1 Index: test/CodeGen/X86/ins_subreg_coalesce-1.ll =================================================================== --- test/CodeGen/X86/ins_subreg_coalesce-1.ll +++ test/CodeGen/X86/ins_subreg_coalesce-1.ll @@ -3,7 +3,7 @@ define fastcc i32 @t() nounwind { ; CHECK-LABEL: t: -; CHECK: # %bb.0: # %walkExprTree.exit +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: movzwl 0, %eax ; CHECK-NEXT: orl $2, %eax ; CHECK-NEXT: movw %ax, 0 Index: test/CodeGen/X86/memcmp-mergeexpand.ll =================================================================== --- test/CodeGen/X86/memcmp-mergeexpand.ll +++ test/CodeGen/X86/memcmp-mergeexpand.ll @@ -8,7 +8,7 @@ define zeroext i1 @opeq1( ; X86-LABEL: opeq1: -; X86: # %bb.0: # %opeq1.exit +; X86: # %bb.0: # %entry ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl (%ecx), %edx @@ -20,7 +20,7 @@ ; X86-NEXT: retl ; ; X64-LABEL: opeq1: -; X64: # %bb.0: # %opeq1.exit +; X64: # %bb.0: # %entry ; X64-NEXT: movq (%rdi), %rax ; X64-NEXT: cmpq (%rsi), %rax ; X64-NEXT: sete %al Index: test/CodeGen/X86/pr32108.ll =================================================================== --- test/CodeGen/X86/pr32108.ll +++ test/CodeGen/X86/pr32108.ll @@ -3,7 +3,7 @@ define void @pr32108() { ; CHECK-LABEL: pr32108: -; CHECK: # %bb.0: # %CF257 +; CHECK: # %bb.0: # %BB ; CHECK-NEXT: movb $0, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .LBB0_1: # %CF244 Index: test/CodeGen/X86/setcc-lowering.ll =================================================================== --- test/CodeGen/X86/setcc-lowering.ll +++ test/CodeGen/X86/setcc-lowering.ll @@ -43,7 +43,7 @@ define void @pr26232(i64 %a, <16 x i1> %b) { ; AVX-LABEL: pr26232: -; AVX: # %bb.0: # %for_loop599.preheader +; AVX: # %bb.0: # %allocas ; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; AVX-NEXT: vmovdqa {{.*#+}} xmm2 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128] ; AVX-NEXT: .p2align 4, 0x90 @@ -64,7 +64,7 @@ ; AVX-NEXT: retq ; ; KNL-32-LABEL: pr26232: -; KNL-32: # %bb.0: # %for_loop599.preheader +; KNL-32: # %bb.0: # %allocas ; KNL-32-NEXT: pushl %esi ; KNL-32-NEXT: .cfi_def_cfa_offset 8 ; KNL-32-NEXT: .cfi_offset %esi, -8 Index: test/CodeGen/X86/split-store.ll =================================================================== --- test/CodeGen/X86/split-store.ll +++ test/CodeGen/X86/split-store.ll @@ -232,7 +232,7 @@ define void @mbb_int32_float_pair(i32 %tmp1, float %tmp2, i64* %ref.tmp) { ; CHECK-LABEL: mbb_int32_float_pair: -; CHECK: # %bb.0: # %next +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: movl %edi, (%rsi) ; CHECK-NEXT: movss %xmm0, 4(%rsi) ; CHECK-NEXT: retq @@ -250,7 +250,7 @@ define void @mbb_int32_float_multi_stores(i32 %tmp1, float %tmp2, i64* %ref.tmp, i64* %ref.tmp1, i1 %cmp) { ; CHECK-LABEL: mbb_int32_float_multi_stores: -; CHECK: # %bb.0: # %bb1 +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: movl %edi, (%rsi) ; CHECK-NEXT: movss %xmm0, 4(%rsi) ; CHECK-NEXT: testb $1, %cl Index: test/CodeGen/X86/tail-dup-merge-loop-headers.ll =================================================================== --- test/CodeGen/X86/tail-dup-merge-loop-headers.ll +++ test/CodeGen/X86/tail-dup-merge-loop-headers.ll @@ -10,7 +10,7 @@ ; CHECK-NOT: # %{{[a-zA-Z_]+}} ; CHECK: # %inner_loop_latch ; CHECK-NOT: # %{{[a-zA-Z_]+}} -; CHECK: # %inner_loop_test +; CHECK: # %inner_loop_top ; CHECK-NOT: # %{{[a-zA-Z_]+}} ; CHECK: # %exit define void @tail_dup_merge_loops(i32 %a, i8* %b, i8* %c) local_unnamed_addr #0 { Index: test/DebugInfo/Generic/sunk-compare.ll =================================================================== --- test/DebugInfo/Generic/sunk-compare.ll +++ test/DebugInfo/Generic/sunk-compare.ll @@ -8,7 +8,7 @@ ; We check that the compare instruction retains its debug loc after ; it is sunk into other.bb by the codegen prepare pass. ; -; CHECK: other.bb: +; CHECK: entry: ; CHECK-NEXT: icmp{{.*}}%x, 0, !dbg ![[MDHANDLE:[0-9]*]] ; CHECK: ![[MDHANDLE]] = !DILocation(line: 2 ; Index: test/Transforms/CodeGenPrepare/X86/computedgoto.ll =================================================================== --- test/Transforms/CodeGenPrepare/X86/computedgoto.ll +++ test/Transforms/CodeGenPrepare/X86/computedgoto.ll @@ -168,7 +168,7 @@ ; the block it terminates. define void @loop(i64* nocapture readonly %p) { ; CHECK-LABEL: @loop( -; CHECK-NEXT: bb0.clone: +; CHECK-NEXT: entry: ; CHECK-NEXT: br label [[DOTSPLIT:%.*]] ; CHECK: bb0: ; CHECK-NEXT: br label [[DOTSPLIT]] Index: test/Transforms/CodeGenPrepare/basic.ll =================================================================== --- test/Transforms/CodeGenPrepare/basic.ll +++ test/Transforms/CodeGenPrepare/basic.ll @@ -13,7 +13,7 @@ %1 = icmp ugt i64 %0, 3 br i1 %1, label %T, label %trap -; CHECK: T: +; CHECK: entry: ; CHECK-NOT: br label % trap: ; preds = %0, %entry Index: test/Transforms/LoopSimplifyCFG/scev.ll =================================================================== --- test/Transforms/LoopSimplifyCFG/scev.ll +++ test/Transforms/LoopSimplifyCFG/scev.ll @@ -6,22 +6,22 @@ define void @t_run_test() { ; CHECK-LABEL: @t_run_test( ; CHECK-NEXT: entry: -; CHECK-NEXT: br label [[LOOP_PH:%.*]] -; CHECK: loop.ph: -; CHECK-NEXT: br label [[LOOP_BODY:%.*]] -; CHECK: loop.body: -; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[LOOP_PH]] ], [ [[INC:%.*]], [[LOOP_BODY]] ] +; CHECK-NEXT: br label %[[LOOP_PH:.*]] +; CHECK: [[LOOP_PH]]: +; CHECK-NEXT: br label %[[LOOP_BODY:.*]] +; CHECK: [[LOOP_BODY]]: +; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, %[[LOOP_PH]] ], [ [[INC:%.*]], %[[LOOP_BODY]] ] ; CHECK-NEXT: [[INC]] = add i32 [[IV]], 1 ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[INC]], 10 -; CHECK-NEXT: br i1 [[CMP]], label [[LOOP_BODY]], label [[EXIT:%.*]] -; CHECK: exit: -; CHECK-NEXT: br label [[LOOP_BODY2:%.*]] -; CHECK: loop.body2: -; CHECK-NEXT: [[IV2:%.*]] = phi i32 [ 0, [[EXIT]] ], [ [[INC2:%.*]], [[LOOP_BODY2]] ] +; CHECK-NEXT: br i1 [[CMP]], label %[[LOOP_BODY]], label %[[EXIT:.*]] +; CHECK: [[EXIT]]: +; CHECK-NEXT: br label %[[LOOP_BODY2:.*]] +; CHECK: [[LOOP_BODY2]]: +; CHECK-NEXT: [[IV2:%.*]] = phi i32 [ 0, %[[EXIT]] ], [ [[INC2:%.*]], %[[LOOP_BODY2]] ] ; CHECK-NEXT: [[INC2]] = add i32 [[IV2]], 1 ; CHECK-NEXT: [[CMP2:%.*]] = icmp ult i32 [[INC2]], 10 -; CHECK-NEXT: br i1 [[CMP2]], label [[LOOP_BODY2]], label [[EXIT2:%.*]] -; CHECK: exit2: +; CHECK-NEXT: br i1 [[CMP2]], label %[[LOOP_BODY2]], label %[[EXIT2:.*]] +; CHECK: [[EXIT2]]: ; CHECK-NEXT: ret void ; entry: Index: test/Transforms/LoopStrengthReduce/ARM/2012-06-15-lsr-noaddrmode.ll =================================================================== --- test/Transforms/LoopStrengthReduce/ARM/2012-06-15-lsr-noaddrmode.ll +++ test/Transforms/LoopStrengthReduce/ARM/2012-06-15-lsr-noaddrmode.ll @@ -44,7 +44,7 @@ ; CHECK: @main ; Check that the loop preheader contains no address computation. -; CHECK: %end_of_chain +; CHECK: %while.cond.i.i ; CHECK-NOT: add{{.*}}lsl ; CHECK: ldr{{.*}}lsl #2 ; CHECK: ldr{{.*}}lsl #2 Index: test/Transforms/LoopStrengthReduce/X86/2012-01-13-phielim.ll =================================================================== --- test/Transforms/LoopStrengthReduce/X86/2012-01-13-phielim.ll +++ test/Transforms/LoopStrengthReduce/X86/2012-01-13-phielim.ll @@ -96,7 +96,8 @@ ; itself a phi. ; ; CHECK: @test3 -; CHECK: %for.body3.lr.ph.us.i.loopexit +; CHECK: %meshBB1 +; CHECK: %meshBB ; CHECK-NEXT: Parent Loop ; CHECK-NEXT: Inner Loop ; CHECK-NEXT: incq Index: test/Transforms/SimpleLoopUnswitch/trivial-unswitch-iteration.ll =================================================================== --- test/Transforms/SimpleLoopUnswitch/trivial-unswitch-iteration.ll +++ test/Transforms/SimpleLoopUnswitch/trivial-unswitch-iteration.ll @@ -13,7 +13,7 @@ ; CHECK-NEXT: br i1 %{{.*}}, label %entry.split.split, label %loop_exit ; ; CHECK: entry.split.split: -; CHECK-NEXT: br label %do_something +; CHECK-NEXT: br label %loop_begin loop_begin: br i1 %cond1, label %continue, label %loop_exit ; first trivial condition @@ -27,9 +27,9 @@ do_something: call void @some_func() noreturn nounwind br label %loop_begin -; CHECK: do_something: +; CHECK: loop_begin: ; CHECK-NEXT: call -; CHECK-NEXT: br label %do_something +; CHECK-NEXT: br label %loop_begin loop_exit: ret i32 0 @@ -38,4 +38,4 @@ ; ; CHECK: loop_exit.split: ; CHECK-NEXT: ret -} \ No newline at end of file +}