Index: lib/Target/ARM/ARM.h =================================================================== --- lib/Target/ARM/ARM.h +++ lib/Target/ARM/ARM.h @@ -15,6 +15,7 @@ #ifndef LLVM_LIB_TARGET_ARM_ARM_H #define LLVM_LIB_TARGET_ARM_ARM_H +#include "llvm/IR/LegacyPassManager.h" #include "llvm/Support/CodeGen.h" #include #include @@ -35,6 +36,8 @@ class MCInst; class PassRegistry; + +Pass *createARMParallelDSPPass(); FunctionPass *createARMISelDag(ARMBaseTargetMachine &TM, CodeGenOpt::Level OptLevel); FunctionPass *createA15SDOptimizerPass(); @@ -57,6 +60,8 @@ BasicBlockInfo &BBI); std::vector computeAllBlockSizes(MachineFunction *MF); + +void initializeARMParallelDSPPass(PassRegistry &); void initializeARMLoadStoreOptPass(PassRegistry &); void initializeARMPreAllocLoadStoreOptPass(PassRegistry &); void initializeARMConstantIslandsPass(PassRegistry &); Index: lib/Target/ARM/ARMParallelDSP.cpp =================================================================== --- /dev/null +++ lib/Target/ARM/ARMParallelDSP.cpp @@ -0,0 +1,528 @@ +//===- ParallelDSP.cpp - Parallel DSP Pass --------------------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +/// \file +/// Armv6 introduced instructions to perform 32-bit SIMD operations. The +/// purpose of this pass is do some IR pattern matching to create ACLE +/// DSP intrinsics, which map on these 32-bit SIMD operations. +// +//===----------------------------------------------------------------------===// + +#include "llvm/ADT/SmallPtrSet.h" +#include "llvm/Analysis/AliasAnalysis.h" +#include "llvm/Analysis/LoopAccessAnalysis.h" +#include "llvm/Analysis/LoopPass.h" +#include "llvm/Analysis/LoopInfo.h" +#include "llvm/IR/Instructions.h" +#include "llvm/IR/NoFolder.h" +#include "llvm/Transforms/Scalar.h" +#include "llvm/Transforms/Utils/BasicBlockUtils.h" +#include "llvm/Transforms/Utils/LoopUtils.h" +#include "llvm/Pass.h" +#include "llvm/PassRegistry.h" +#include "llvm/PassSupport.h" +#include "llvm/Support/Debug.h" +#include "llvm/IR/PatternMatch.h" +#include "llvm/CodeGen/TargetPassConfig.h" +#include "ARM.h" +#include "ARMSubtarget.h" + +using namespace llvm; +using namespace PatternMatch; + +#define DEBUG_TYPE "parallel-dsp" + +namespace { + struct ParallelMAC; + struct Reduction; + + using ParallelMACList = SmallVector; + using ReductionList = SmallVector; + using ValueList = SmallVector; + using LoadInstList = SmallVector; + using PMACPair = std::pair; + using PMACPairList = SmallVector; + + // 'ParallelMAC' and 'Reduction' are just some bookkeeping data structures. + // 'Reduction' contains the phi-node and accumulator statement from where we + // start pattern matching, and 'ParallelMAC' the multiplication + // instructions that are candidates for parallel execution. + struct ParallelMAC { + Instruction *Mul; + ValueList VL; // List of all (narrow) operands of this Mul + LoadInstList VecLd; // List of all load instructions of this Mul + + ParallelMAC(Instruction *I, ValueList &V) : Mul(I), VL(V) {}; + }; + + struct Reduction { + PHINode *Phi; // The Phi-node from where we start + // pattern matching. + Instruction *AccIntAdd; // The accumulating integer add statement, + // i.e, the reduction statement. + + Reduction (PHINode *P, Instruction *Acc) : Phi(P), AccIntAdd(Acc) { }; + }; + + class ARMParallelDSP : public LoopPass { + ScalarEvolution *SE; + AliasAnalysis *AA; + TargetLibraryInfo *TLI; + DominatorTree *DT; + LoopInfo *LI; + Loop *L; + const DataLayout *DL; + Module *M; + + bool InsertParallelMACs(Reduction &Reduction, PMACPairList &PMACPairs); + bool AreSequentialLoads(LoadInst *Ld0, LoadInst *Ld1, LoadInstList &VecLd); + PMACPairList CreateParallelMACPairs(ParallelMACList &Candidates); + Instruction *CreateSMLADCall(LoadInst *VecLd0, LoadInst *VecLd1, + Instruction *Acc, Instruction *InsertAfter); + + /// Try to match and generate: SMLAD, SMLADX - Signed Multiply Accumulate + /// Dual performs two signed 16x16-bit multiplications. It adds the + /// products to a 32-bit accumulate operand. Optionally, the instruction can + /// exchange the halfwords of the second operand before performing the + /// arithmetic. + bool MatchSMLAD(Function &F); + + public: + static char ID; + + ARMParallelDSP() : LoopPass(ID) { } + + void getAnalysisUsage(AnalysisUsage &AU) const override { + LoopPass::getAnalysisUsage(AU); + AU.addRequired(); + AU.addRequired(); + AU.addRequired(); + AU.addRequired(); + AU.addRequired(); + AU.addRequired(); + AU.addRequired(); + AU.addPreserved(); + AU.setPreservesCFG(); + } + + bool runOnLoop(Loop *TheLoop, LPPassManager &) override { + L = TheLoop; + SE = &getAnalysis().getSE(); + AA = &getAnalysis().getAAResults(); + TLI = &getAnalysis().getTLI(); + DT = &getAnalysis().getDomTree(); + LI = &getAnalysis().getLoopInfo(); + auto &TPC = getAnalysis(); + + BasicBlock *Header = TheLoop->getHeader(); + Function &F = *Header->getParent(); + M = F.getParent(); + DL = &M->getDataLayout(); + + auto &TM = TPC.getTM(); + auto *ST = &TM.getSubtarget(F); + + if (!ST->hasDSP()) { + LLVM_DEBUG(dbgs() << "DSP extension not enabled, not running pass " + "ARMParallelDSP\n"); + return false; + } + + LoopAccessInfo LAI(L, SE, TLI, AA, DT, LI); + + LLVM_DEBUG(dbgs() << "\n== Parallel DSP pass ==\n\n"); + return MatchSMLAD(F); + } + }; +} + +template +static bool IsNarrowSequence(Value *V, ValueList &VL) { + LLVM_DEBUG(dbgs() << "Is narrow sequence: "; V->dump()); + ConstantInt *CInt; + + if (match(V, m_ConstantInt(CInt))) { + // If a constant is used, it needs to fit within the bit width. + if (CInt->getUniqueInteger().getBitWidth() <= BitWidth) { + LLVM_DEBUG(dbgs() << "OK: found narrow constant.\n"); + VL.push_back(CInt); + return true; + } + LLVM_DEBUG(dbgs() << "Found wide constant:\t"; CInt->dump()); + return false; + } + + auto *I = dyn_cast(V); + if (!I) + return false; + + Value *Val, *LHS, *RHS; + bool isNarrow = false; + + if (match(V, m_Trunc(m_Value(Val)))) { + if (cast(I)->getDestTy()->getIntegerBitWidth() == BitWidth) + isNarrow = IsNarrowSequence(Val, VL); + } else if (match(V, m_Add(m_Value(LHS), m_Value(RHS)))) { + if (IsNarrowSequence(LHS, VL) && + IsNarrowSequence(RHS, VL)) + isNarrow = true; + } else if (match(V, m_ZExtOrSExt(m_Value(Val)))) { + if (cast(I)->getSrcTy()->getIntegerBitWidth() == BitWidth) + isNarrow = true; + else + LLVM_DEBUG(dbgs() << "Wrong SrcTy size of CastInst: " << + cast(I)->getSrcTy()->getIntegerBitWidth()); + + if (match(Val, m_Load(m_Value(Val)))) { + auto *Ld = dyn_cast(I->getOperand(0)); + LLVM_DEBUG(dbgs() << "Found narrow Load:\t"; Ld->dump()); + VL.push_back(Ld); + isNarrow = true; + } else if (!isa(I->getOperand(0))) + VL.push_back(I->getOperand(0)); + } + + if (isNarrow) { + LLVM_DEBUG(dbgs() << "Found narrow Op:\t"; I->dump()); + VL.push_back(I); + } else + LLVM_DEBUG(dbgs() << "Found unsupported Op:\t"; I->dump()); + + return isNarrow; +} + +// Element-by-element comparison of Value lists returning true if they are +// instructions with the same opcode or constants with the same value. +static bool AreSymmetrical(const ValueList &VL0, + const ValueList &VL1) { + if (VL0.size() != VL1.size()) { + LLVM_DEBUG(dbgs() << "Muls are mismatching operand list lengths: " + << VL0.size() << " != " << VL1.size() << "\n"); + return false; + } + + const unsigned Pairs = VL0.size(); + LLVM_DEBUG(dbgs() << "Number of operand pairs: " << Pairs << "\n"); + + for (unsigned i = 0; i < Pairs; ++i) { + const Value *V0 = VL0[i]; + const Value *V1 = VL1[i]; + const auto *Inst0 = dyn_cast(V0); + const auto *Inst1 = dyn_cast(V1); + + LLVM_DEBUG(dbgs() << "Pair " << i << ":\n"; + dbgs() << "mul1: "; V0->dump(); + dbgs() << "mul2: "; V1->dump()); + + if (!Inst0 || !Inst1) + return false; + + if (Inst0->getOpcode() == Inst1->getOpcode()) { + LLVM_DEBUG(dbgs() << "OK: opcodes match!\n"); + continue; + } + + const APInt *C0, *C1; + if (!(match(V0, m_APInt(C0)) && match(V1, m_APInt(C1)) && C0 == C1)) + return false; + } + + LLVM_DEBUG(dbgs() << "OK: found symmetrical operand lists.\n"); + return true; +} + +bool ARMParallelDSP::AreSequentialLoads(LoadInst *Ld0, LoadInst *Ld1, + LoadInstList &VecLd) { + if (!Ld0 || !Ld1) + return false; + + LLVM_DEBUG(dbgs() << "Are consecutive loads:\n"; + dbgs() << "Ld0:"; Ld0->dump(); + dbgs() << "Ld1:"; Ld1->dump(); + ); + + if (Ld0->isVolatile() || Ld1->isVolatile()) { + LLVM_DEBUG(dbgs() << "No, not touching volatile loads\n"); + return false; + } + if (!Ld0->hasOneUse() || !Ld1->hasOneUse()) { + LLVM_DEBUG(dbgs() << "No, load has more than one use.\n"); + return false; + } + + if (isConsecutiveAccess(Ld0, Ld1, *DL, *SE)) { + VecLd.push_back(Ld0); + VecLd.push_back(Ld1); + LLVM_DEBUG(dbgs() << "OK: loads are consecutive.\n"); + return true; + } + + LLVM_DEBUG(dbgs() << "No, Ld0 and Ld1 aren't consecutive.\n"); + return false; +} + +PMACPairList +ARMParallelDSP::CreateParallelMACPairs(ParallelMACList &Candidates) { + const unsigned Elems = Candidates.size(); + PMACPairList PMACPairs; + + for(unsigned i=0; idump(); + dbgs() << "- "; Mul1->dump()); + + const ValueList &VL0 = PMul0.VL; + const ValueList &VL1 = PMul1.VL; + + // A mul has 2 operands, and a narrow op consist of sext and a load; thus + // we expect at least 4 items in this list. + if (VL0.size() < 4) { + LLVM_DEBUG(dbgs() << "Operand list too short.\n"); + continue; + } + + if (!AreSymmetrical(VL0, VL1)) + continue; + + LLVM_DEBUG(dbgs() << "OK: mul operands list match:\n"); + + // The first elements of each vector should be loads with sexts. If we find + // that its two pairs of consecutive loads, then these can be transformed + // into two wider loads and the users can be replaced with DSP + // intrinsics. + for (unsigned x = 0; x < VL0.size(); x += 4) { + auto *Ld0 = dyn_cast(VL0[x]); + auto *Ld1 = dyn_cast(VL1[x]); + auto *Ld2 = dyn_cast(VL0[x+2]); + auto *Ld3 = dyn_cast(VL1[x+2]); + + LLVM_DEBUG(dbgs() << "Looking at operands " << x << ":\n"; + dbgs() << "\t mul1: "; VL0[x]->dump(); + dbgs() << "\t mul2: "; VL1[x]->dump(); + dbgs() << "and operands " << x + 2 << ":\n"; + dbgs() << "\t mul1: "; VL0[x+2]->dump(); + dbgs() << "\t mul2: "; VL1[x+2]->dump()); + + if (AreSequentialLoads(Ld0, Ld1, Candidates[i].VecLd) && + AreSequentialLoads(Ld2, Ld3, Candidates[j].VecLd)) { + LLVM_DEBUG(dbgs() << "OK: found two pairs of parallel loads!\n"); + PMACPairs.push_back(std::make_pair(&PMul0, &PMul1)); + } + } + } + } + return PMACPairs; +} + +bool ARMParallelDSP::InsertParallelMACs(Reduction &Reduction, + PMACPairList &PMACPairs) { + bool Result = false; + Instruction *Acc = Reduction.Phi; + Instruction *InsertAfter = Reduction.AccIntAdd; + + for (auto &Pair : PMACPairs) { + LLVM_DEBUG(dbgs() << "Found parallel MACs!!\n"; + dbgs() << "- "; Pair.first->Mul->dump(); + dbgs() << "- "; Pair.second->Mul->dump()); + + Acc = CreateSMLADCall(Pair.first->VecLd[0], Pair.second->VecLd[0], Acc, + InsertAfter); + InsertAfter = Acc; + if (Acc == Reduction.Phi) + continue; + + LLVM_DEBUG(dbgs() << "Replace Accumulate: "; Acc->dump()); + Reduction.AccIntAdd->replaceAllUsesWith(Acc); + Result = true; + } + return Result; +} + +static ReductionList MatchReductions(Function &F, Loop *TheLoop, + BasicBlock *Header) { + ReductionList Reductions; + RecurrenceDescriptor RecDesc; + const bool HasFnNoNaNAttr = + F.getFnAttribute("no-nans-fp-math").getValueAsString() == "true"; + + // TODO: should we handle multiple latch blocks? + BasicBlock *Latch = TheLoop->getLoopLatch(); + if (!Latch) + return Reductions; + + for (PHINode &Phi : Header->phis()) { + if (!Phi.getType()->isIntegerTy()) + continue; + const bool IsReduction = + RecurrenceDescriptor::AddReductionVar(&Phi, + RecurrenceDescriptor::RK_IntegerAdd, + TheLoop, HasFnNoNaNAttr, RecDesc); + if (!IsReduction) + continue; + + Instruction *Acc = dyn_cast(Phi.getIncomingValueForBlock(Latch)); + if (!Acc) + continue; + + Reductions.push_back(Reduction(&Phi, Acc)); + } + + LLVM_DEBUG( + dbgs() << "\nAccumulating integer additions (reductions) found:\n"; + for (auto R : Reductions) { + dbgs() << "- "; R.Phi->dump(); + dbgs() << "-> "; R.AccIntAdd->dump(); + } + ); + return Reductions; +} + +static void AddCandidateMAC(ParallelMACList &Candidates, const Instruction *Acc, + Value *MulOp0, Value *MulOp1, int MulOpNum) { + Instruction *Mul = dyn_cast(Acc->getOperand(MulOpNum)); + LLVM_DEBUG(dbgs() << "Found acc mul:\t"; Mul->dump()); + ValueList VL; + if (IsNarrowSequence<16>(MulOp0, VL) && + IsNarrowSequence<16>(MulOp1, VL)) { + LLVM_DEBUG(dbgs() << "OK: found narrow mul: "; Mul->dump()); + Candidates.push_back(ParallelMAC(Mul, VL)); + } +} + +static ParallelMACList MatchParallelMACs(Reduction &R) { + ParallelMACList Candidates; + const Instruction *Acc = R.AccIntAdd; + Value *A, *MulOp0, *MulOp1; + LLVM_DEBUG(dbgs() << "- Analysing:\t"; Acc->dump()); + + // Pattern 1: the accumulator is the RHS of the mul. + while(match(Acc, m_Add(m_Mul(m_Value(MulOp0), m_Value(MulOp1)), + m_Value(A)))){ + AddCandidateMAC(Candidates, Acc, MulOp0, MulOp1, 0); + Acc = dyn_cast(A); + } + // Pattern 2: the accumulator is the LHS of the mul. + while(match(Acc, m_Add(m_Value(A), + m_Mul(m_Value(MulOp0), m_Value(MulOp1))))) { + AddCandidateMAC(Candidates, Acc, MulOp0, MulOp1, 1); + Acc = dyn_cast(A); + } + + // The last mul in the chain has a slightly different pattern: + // the mul is the first operand + if (match(Acc, m_Add(m_Mul(m_Value(MulOp0), m_Value(MulOp1)), m_Value(A)))) + AddCandidateMAC(Candidates, Acc, MulOp0, MulOp1, 0); + + // Because we start at the bottom of the chain, and we work our way up, + // the muls are added in reverse program order to the list. + std::reverse(Candidates.begin(), Candidates.end()); + return Candidates; +} + +// Loop Pass that needs to identify integer add/sub reductions of 16-bit vector +// multiplications. +// To use SMLAD: +// 1) we first need to find integer add reduction PHIs, +// 2) then from the PHI, look for this pattern: +// +// acc0 = phi i32 [0, %entry], [%acc1, %loop.body] +// ld0 = load i16 +// sext0 = sext i16 %ld0 to i32 +// ld1 = load i16 +// sext1 = sext i16 %ld1 to i32 +// mul0 = mul %sext0, %sext1 +// ld2 = load i16 +// sext2 = sext i16 %ld2 to i32 +// ld3 = load i16 +// sext3 = sext i16 %ld3 to i32 +// mul1 = mul i32 %sext2, %sext3 +// add0 = add i32 %mul0, %acc0 +// acc1 = add i32 %add0, %mul1 +// +// Which can be selected to: +// +// ldr.h r0 +// ldr.h r1 +// smlad r2, r0, r1, r2 +// +// If constants are used instead of loads, these will need to be hoisted +// out and into a register. +// +// If loop invariants are used instead of loads, these need to be packed +// before the loop begins. +// +// Can only be enabled for cores which support unaligned accesses. +// +bool ARMParallelDSP::MatchSMLAD(Function &F) { + BasicBlock *Header = L->getHeader(); + + LLVM_DEBUG(dbgs() << "= Matching SMLAD =\n"; + dbgs() << "Header block:\n"; Header->dump(); + dbgs() << "Loop info:\n\n"; L->dump()); + + bool Changed = false; + + ReductionList Reductions = MatchReductions(F, L, Header); + for (auto &R : Reductions) { + ParallelMACList Candidates = MatchParallelMACs(R); + PMACPairList PMACPairs = CreateParallelMACPairs(Candidates); + Changed = InsertParallelMACs(R, PMACPairs) || Changed; + } + return Changed; +} + +Instruction *ARMParallelDSP::CreateSMLADCall(LoadInst *VecLd0, LoadInst *VecLd1, + Instruction *Acc, + Instruction *InsertAfter) { + LLVM_DEBUG(dbgs() << "Create SMLAD intrinsic using:\n"; + dbgs() << "- "; VecLd0->dump(); + dbgs() << "- "; VecLd1->dump(); + dbgs() << "- "; Acc->dump()); + + IRBuilder Builder(InsertAfter->getParent(), + ++BasicBlock::iterator(InsertAfter)); + + // Replace the reduction chain with an intrinsic call + Type *AccTy = Acc->getType(); + unsigned AddrSpace = VecLd0->getPointerAddressSpace(); + Value *VecPtr = Builder.CreateBitCast(VecLd0->getPointerOperand(), + AccTy->getPointerTo(AddrSpace)); + VecLd0 = Builder.CreateLoad(Acc->getType(), VecPtr); + + AddrSpace = VecLd1->getPointerAddressSpace(); + VecPtr = Builder.CreateBitCast(VecLd1->getPointerOperand(), + AccTy->getPointerTo(AddrSpace)); + VecLd1 = Builder.CreateLoad(Acc->getType(), VecPtr); + + Value* Args[] = { VecLd0, VecLd1, Acc }; + Function *SMLAD = Intrinsic::getDeclaration(M, Intrinsic::arm_smlad); + + CallInst *Call = Builder.CreateCall(SMLAD, Args); + return Call; +} + +Pass *llvm::createARMParallelDSPPass() { + return new ARMParallelDSP(); +} + +char ARMParallelDSP::ID = 0; + +INITIALIZE_PASS_BEGIN(ARMParallelDSP, "parallel-dsp", + "Transform loops to use DSP intrinsics", false, false); +INITIALIZE_PASS_END(ARMParallelDSP, "parallel-dsp", + "Transform loops to use DSP intrinsics", false, false); Index: lib/Target/ARM/ARMTargetMachine.cpp =================================================================== --- lib/Target/ARM/ARMTargetMachine.cpp +++ lib/Target/ARM/ARMTargetMachine.cpp @@ -89,6 +89,7 @@ initializeGlobalISel(Registry); initializeARMLoadStoreOptPass(Registry); initializeARMPreAllocLoadStoreOptPass(Registry); + initializeARMParallelDSPPass(Registry); initializeARMConstantIslandsPass(Registry); initializeARMExecutionDomainFixPass(Registry); initializeARMExpandPseudoPass(Registry); @@ -404,6 +405,9 @@ } bool ARMPassConfig::addPreISel() { + if (getOptLevel() != CodeGenOpt::None) + addPass(createARMParallelDSPPass()); + if ((TM->getOptLevel() != CodeGenOpt::None && EnableGlobalMerge == cl::BOU_UNSET) || EnableGlobalMerge == cl::BOU_TRUE) { Index: lib/Target/ARM/CMakeLists.txt =================================================================== --- lib/Target/ARM/CMakeLists.txt +++ lib/Target/ARM/CMakeLists.txt @@ -34,6 +34,7 @@ ARMISelLowering.cpp ARMInstrInfo.cpp ARMLegalizerInfo.cpp + ARMParallelDSP.cpp ARMLoadStoreOptimizer.cpp ARMMCInstLower.cpp ARMMachineFunctionInfo.cpp Index: lib/Target/ARM/LLVMBuild.txt =================================================================== --- lib/Target/ARM/LLVMBuild.txt +++ lib/Target/ARM/LLVMBuild.txt @@ -31,5 +31,5 @@ type = Library name = ARMCodeGen parent = ARM -required_libraries = ARMAsmPrinter ARMDesc ARMInfo Analysis AsmPrinter CodeGen Core MC Scalar SelectionDAG Support Target GlobalISel ARMUtils +required_libraries = ARMAsmPrinter ARMDesc ARMInfo Analysis AsmPrinter CodeGen Core MC Scalar SelectionDAG Support Target GlobalISel ARMUtils TransformUtils add_to_library_groups = ARM Index: test/CodeGen/ARM/smlad0.ll =================================================================== --- /dev/null +++ test/CodeGen/ARM/smlad0.ll @@ -0,0 +1,53 @@ +; RUN: opt -mtriple=arm-arm-eabi -mcpu=cortex-m33 < %s -parallel-dsp -S | FileCheck %s +; RUN: opt -mtriple=arm-arm-eabi -mcpu=cortex-m0 < %s -parallel-dsp -S | FileCheck %s --check-prefix=CHECK-NODSP + +; CHECK: %mac1{{\.}}026 = phi i32 [ [[V8:%[0-9]+]], %for.body ], [ 0, %for.body.preheader ] +; CHECK: [[V4:%[0-9]+]] = bitcast i16* %arrayidx3 to i32* +; CHECK: [[V5:%[0-9]+]] = load i32, i32* [[V4]] +; CHECK: [[V6:%[0-9]+]] = bitcast i16* %arrayidx to i32* +; CHECK: [[V7:%[0-9]+]] = load i32, i32* [[V6]] +; CHECK: [[V8]] = call i32 @llvm.arm.smlad(i32 [[V5]], i32 [[V7]], i32 %mac1{{\.}}026) + +; CHECK-NODSP-NOT: call i32 @llvm.arm.smlad + +define dso_local i32 @test(i32 %arg, i32* nocapture readnone %arg1, i16* nocapture readonly %arg2, i16* nocapture readonly %arg3) { +entry: + %cmp24 = icmp sgt i32 %arg, 0 + br i1 %cmp24, label %for.body.preheader, label %for.cond.cleanup + +for.body.preheader: + %.pre = load i16, i16* %arg3, align 2 + %.pre27 = load i16, i16* %arg2, align 2 + br label %for.body + +for.cond.cleanup: + %mac1.0.lcssa = phi i32 [ 0, %entry ], [ %add11, %for.body ] + ret i32 %mac1.0.lcssa + +for.body: + %mac1.026 = phi i32 [ %add11, %for.body ], [ 0, %for.body.preheader ] + %i.025 = phi i32 [ %add, %for.body ], [ 0, %for.body.preheader ] + %arrayidx = getelementptr inbounds i16, i16* %arg3, i32 %i.025 + %0 = load i16, i16* %arrayidx, align 2 + %add = add nuw nsw i32 %i.025, 1 + %arrayidx1 = getelementptr inbounds i16, i16* %arg3, i32 %add + %1 = load i16, i16* %arrayidx1, align 2 + %arrayidx3 = getelementptr inbounds i16, i16* %arg2, i32 %i.025 + %2 = load i16, i16* %arrayidx3, align 2 + %conv = sext i16 %2 to i32 + %conv4 = sext i16 %0 to i32 + %mul = mul nsw i32 %conv, %conv4 + %arrayidx6 = getelementptr inbounds i16, i16* %arg2, i32 %add + %3 = load i16, i16* %arrayidx6, align 2 + %conv7 = sext i16 %3 to i32 + %conv8 = sext i16 %1 to i32 + %mul9 = mul nsw i32 %conv7, %conv8 + %add10 = add i32 %mul, %mac1.026 + +; Here the Mul is the LHS, and the Add the RHS. + %add11 = add i32 %mul9, %add10 + + %exitcond = icmp ne i32 %add, %arg + br i1 %exitcond, label %for.body, label %for.cond.cleanup +} + Index: test/CodeGen/ARM/smlad1.ll =================================================================== --- /dev/null +++ test/CodeGen/ARM/smlad1.ll @@ -0,0 +1,50 @@ +; RUN: opt -mtriple=arm-arm-eabi -mcpu=cortex-m33 < %s -parallel-dsp -S | FileCheck %s + +; CHECK: %mac1{{\.}}026 = phi i32 [ [[V8:%[0-9]+]], %for.body ], [ 0, %for.body.preheader ] +; CHECK: [[V4:%[0-9]+]] = bitcast i16* %arrayidx3 to i32* +; CHECK: [[V5:%[0-9]+]] = load i32, i32* [[V4]] +; CHECK: [[V6:%[0-9]+]] = bitcast i16* %arrayidx to i32* +; CHECK: [[V7:%[0-9]+]] = load i32, i32* [[V6]] +; CHECK: [[V8]] = call i32 @llvm.arm.smlad(i32 [[V5]], i32 [[V7]], i32 %mac1{{\.}}026) + +define dso_local i32 @test(i32 %arg, i32* nocapture readnone %arg1, i16* nocapture readonly %arg2, i16* nocapture readonly %arg3) { +entry: + %cmp24 = icmp sgt i32 %arg, 0 + br i1 %cmp24, label %for.body.preheader, label %for.cond.cleanup + +for.body.preheader: + %.pre = load i16, i16* %arg3, align 2 + %.pre27 = load i16, i16* %arg2, align 2 + br label %for.body + +for.cond.cleanup: + %mac1.0.lcssa = phi i32 [ 0, %entry ], [ %add11, %for.body ] + ret i32 %mac1.0.lcssa + +for.body: + %mac1.026 = phi i32 [ %add11, %for.body ], [ 0, %for.body.preheader ] + %i.025 = phi i32 [ %add, %for.body ], [ 0, %for.body.preheader ] + %arrayidx = getelementptr inbounds i16, i16* %arg3, i32 %i.025 + %0 = load i16, i16* %arrayidx, align 2 + %add = add nuw nsw i32 %i.025, 1 + %arrayidx1 = getelementptr inbounds i16, i16* %arg3, i32 %add + %1 = load i16, i16* %arrayidx1, align 2 + %arrayidx3 = getelementptr inbounds i16, i16* %arg2, i32 %i.025 + %2 = load i16, i16* %arrayidx3, align 2 + %conv = sext i16 %2 to i32 + %conv4 = sext i16 %0 to i32 + %mul = mul nsw i32 %conv, %conv4 + %arrayidx6 = getelementptr inbounds i16, i16* %arg2, i32 %add + %3 = load i16, i16* %arrayidx6, align 2 + %conv7 = sext i16 %3 to i32 + %conv8 = sext i16 %1 to i32 + %mul9 = mul nsw i32 %conv7, %conv8 + %add10 = add i32 %mul, %mac1.026 + +; And here the Add is the LHS, the Mul the RHS + %add11 = add i32 %add10, %mul9 + + %exitcond = icmp ne i32 %add, %arg + br i1 %exitcond, label %for.body, label %for.cond.cleanup +} + Index: test/CodeGen/ARM/smlad2.ll =================================================================== --- /dev/null +++ test/CodeGen/ARM/smlad2.ll @@ -0,0 +1,52 @@ +; RUN: opt -mtriple=arm-arm-eabi -mcpu=cortex-m33 < %s -parallel-dsp -S | FileCheck %s +; +; Check that we don't generate the smlad instruction here as the operands of +; both muls are not symmetrical (see also comments inlined below). +; +; CHECK-NOT: call i32 @llvm.arm.smlad +; +define dso_local i32 @test(i32 %arg, i32* nocapture readnone %arg1, i16* nocapture readonly %arg2, i16* nocapture readonly %arg3) { +entry: + %cmp24 = icmp sgt i32 %arg, 0 + br i1 %cmp24, label %for.body.preheader, label %for.cond.cleanup + +for.body.preheader: + %.pre = load i16, i16* %arg3, align 2 + %.pre27 = load i16, i16* %arg2, align 2 + br label %for.body + +for.cond.cleanup: + %mac1.0.lcssa = phi i32 [ 0, %entry ], [ %add11, %for.body ] + ret i32 %mac1.0.lcssa + +for.body: + %mac1.026 = phi i32 [ %add11, %for.body ], [ 0, %for.body.preheader ] + %i.025 = phi i32 [ %add, %for.body ], [ 0, %for.body.preheader ] + %arrayidx = getelementptr inbounds i16, i16* %arg3, i32 %i.025 + %0 = load i16, i16* %arrayidx, align 2 + %add = add nuw nsw i32 %i.025, 1 + %arrayidx1 = getelementptr inbounds i16, i16* %arg3, i32 %add + %1 = load i16, i16* %arrayidx1, align 2 + %arrayidx3 = getelementptr inbounds i16, i16* %arg2, i32 %i.025 + %2 = load i16, i16* %arrayidx3, align 2 + %conv = sext i16 %2 to i32 + +; This zero-extends the 2nd operand of %mul: + %conv4 = zext i16 %0 to i32 + + %mul = mul nsw i32 %conv, %conv4 + %arrayidx6 = getelementptr inbounds i16, i16* %arg2, i32 %add + %3 = load i16, i16* %arrayidx6, align 2 + +; And here we only have sign-extensions. Thus, the operands of +; %mul and %mul9 are not symmetrical: + %conv7 = sext i16 %3 to i32 + %conv8 = sext i16 %1 to i32 + + %mul9 = mul nsw i32 %conv7, %conv8 + %add10 = add i32 %mul, %mac1.026 + %add11 = add i32 %add10, %mul9 + %exitcond = icmp ne i32 %add, %arg + br i1 %exitcond, label %for.body, label %for.cond.cleanup +} + Index: test/CodeGen/ARM/smlad3.ll =================================================================== --- /dev/null +++ test/CodeGen/ARM/smlad3.ll @@ -0,0 +1,51 @@ +; RUN: opt -mtriple=arm-arm-eabi -mcpu=cortex-m33 < %s -parallel-dsp -S | FileCheck %s +; +; Check that we don't generate the smlad instruction here as the loads +; are not consecutive (see also comments inlined below). +; +; CHECK-NOT: call i32 @llvm.arm.smlad +; +define dso_local i32 @test(i32 %arg, i32* nocapture readnone %arg1, i16* nocapture readonly %arg2, i16* nocapture readonly %arg3) { +entry: + %cmp24 = icmp sgt i32 %arg, 0 + br i1 %cmp24, label %for.body.preheader, label %for.cond.cleanup + +for.body.preheader: + %.pre = load i16, i16* %arg3, align 2 + %.pre27 = load i16, i16* %arg2, align 2 + br label %for.body + +for.cond.cleanup: + %mac1.0.lcssa = phi i32 [ 0, %entry ], [ %add11, %for.body ] + ret i32 %mac1.0.lcssa + +for.body: + %mac1.026 = phi i32 [ %add11, %for.body ], [ 0, %for.body.preheader ] + %i.025 = phi i32 [ %add, %for.body ], [ 0, %for.body.preheader ] + %arrayidx = getelementptr inbounds i16, i16* %arg3, i32 %i.025 + %0 = load i16, i16* %arrayidx, align 2 + %add = add nuw nsw i32 %i.025, 1 + %arrayidx1 = getelementptr inbounds i16, i16* %arg3, i32 %add + %1 = load i16, i16* %arrayidx1, align 2 + %arrayidx3 = getelementptr inbounds i16, i16* %arg2, i32 %i.025 + %2 = load i16, i16* %arrayidx3, align 2 + %conv = sext i16 %2 to i32 + %conv4 = sext i16 %0 to i32 + %mul = mul nsw i32 %conv, %conv4 + +; Here we add another constants offset of 2, to make sure the +; loads to %3 and %2 are not consecutive: + + %add5 = add nuw nsw i32 %i.025, 2 + %arrayidx6 = getelementptr inbounds i16, i16* %arg2, i32 %add5 + %3 = load i16, i16* %arrayidx6, align 2 + + %conv7 = sext i16 %3 to i32 + %conv8 = sext i16 %1 to i32 + %mul9 = mul nsw i32 %conv7, %conv8 + %add10 = add i32 %mul, %mac1.026 + %add11 = add i32 %add10, %mul9 + %exitcond = icmp ne i32 %add, %arg + br i1 %exitcond, label %for.body, label %for.cond.cleanup +} + Index: test/CodeGen/ARM/smlad4.ll =================================================================== --- /dev/null +++ test/CodeGen/ARM/smlad4.ll @@ -0,0 +1,51 @@ +; RUN: opt -mtriple=arm-arm-eabi -mcpu=cortex-m33 < %s -parallel-dsp -S | FileCheck %s +; +; Check that we don't generate the smlad instruction here as the loads +; are not not narrow loads (see also comments inlined below). +; +; CHECK-NOT: call i32 @llvm.arm.smlad +; +; Arg2 is now an i32, while Arg3 is still and i16: +; +define dso_local i32 @test(i32 %arg, i32* nocapture readnone %arg1, i32* nocapture readonly %arg2, i16* nocapture readonly %arg3) { +entry: + %cmp22 = icmp sgt i32 %arg, 0 + br i1 %cmp22, label %for.body.preheader, label %for.cond.cleanup + +for.body.preheader: + %.pre = load i16, i16* %arg3, align 2 + br label %for.body + +for.cond.cleanup: + %mac1.0.lcssa = phi i32 [ 0, %entry ], [ %add9, %for.body ] + ret i32 %mac1.0.lcssa + +for.body: + %0 = phi i16 [ %1, %for.body ], [ %.pre, %for.body.preheader ] + %mac1.024 = phi i32 [ %add9, %for.body ], [ 0, %for.body.preheader ] + %i.023 = phi i32 [ %add, %for.body ], [ 0, %for.body.preheader ] + %add = add nuw nsw i32 %i.023, 1 + %arrayidx1 = getelementptr inbounds i16, i16* %arg3, i32 %add + %1 = load i16, i16* %arrayidx1, align 2 + %conv = sext i16 %0 to i32 + +; This is now a 'normal' i32 load to %2: + + %arrayidx3 = getelementptr inbounds i32, i32* %arg2, i32 %i.023 + %2 = load i32, i32* %arrayidx3, align 4 + +; This mul has now 1 operand which is a narrow load, and the other a normal +; i32 load: + + %mul = mul nsw i32 %2, %conv + + %add4 = add nuw nsw i32 %i.023, 2 + %arrayidx5 = getelementptr inbounds i32, i32* %arg2, i32 %add4 + %3 = load i32, i32* %arrayidx5, align 4 + %conv6 = sext i16 %1 to i32 + %mul7 = mul nsw i32 %3, %conv6 + %add8 = add i32 %mul, %mac1.024 + %add9 = add i32 %add8, %mul7 + %exitcond = icmp eq i32 %add, %arg + br i1 %exitcond, label %for.cond.cleanup, label %for.body +} Index: test/CodeGen/ARM/smlad5.ll =================================================================== --- /dev/null +++ test/CodeGen/ARM/smlad5.ll @@ -0,0 +1,45 @@ +; RUN: opt -mtriple=arm-arm-eabi -mcpu=cortex-m33 < %s -parallel-dsp -S | FileCheck %s +; +; Check that we don't generate the smlad instruction when the loads +; are volatile loads. +; +; CHECK-NOT: call i32 @llvm.arm.smlad +; +define dso_local i32 @test(i32 %arg, i32* nocapture readnone %arg1, i16* nocapture readonly %arg2, i16* nocapture readonly %arg3) { +entry: + %cmp24 = icmp sgt i32 %arg, 0 + br i1 %cmp24, label %for.body.preheader, label %for.cond.cleanup + +for.body.preheader: + %.pre = load i16, i16* %arg3, align 2 + %.pre27 = load i16, i16* %arg2, align 2 + br label %for.body + +for.cond.cleanup: + %mac1.0.lcssa = phi i32 [ 0, %entry ], [ %add11, %for.body ] + ret i32 %mac1.0.lcssa + +for.body: + %mac1.026 = phi i32 [ %add11, %for.body ], [ 0, %for.body.preheader ] + %i.025 = phi i32 [ %add, %for.body ], [ 0, %for.body.preheader ] + %arrayidx = getelementptr inbounds i16, i16* %arg3, i32 %i.025 + %0 = load volatile i16, i16* %arrayidx, align 2 + %add = add nuw nsw i32 %i.025, 1 + %arrayidx1 = getelementptr inbounds i16, i16* %arg3, i32 %add + %1 = load volatile i16, i16* %arrayidx1, align 2 + %arrayidx3 = getelementptr inbounds i16, i16* %arg2, i32 %i.025 + %2 = load volatile i16, i16* %arrayidx3, align 2 + %conv = sext i16 %2 to i32 + %conv4 = sext i16 %0 to i32 + %mul = mul nsw i32 %conv, %conv4 + %arrayidx6 = getelementptr inbounds i16, i16* %arg2, i32 %add + %3 = load volatile i16, i16* %arrayidx6, align 2 + %conv7 = sext i16 %3 to i32 + %conv8 = sext i16 %1 to i32 + %mul9 = mul nsw i32 %conv7, %conv8 + %add10 = add i32 %mul, %mac1.026 + %add11 = add i32 %add10, %mul9 + %exitcond = icmp ne i32 %add, %arg + br i1 %exitcond, label %for.body, label %for.cond.cleanup +} +