Index: lib/Target/Mips/Mips16FrameLowering.cpp
===================================================================
--- lib/Target/Mips/Mips16FrameLowering.cpp
+++ lib/Target/Mips/Mips16FrameLowering.cpp
@@ -42,7 +42,6 @@
 
 void Mips16FrameLowering::emitPrologue(MachineFunction &MF,
                                        MachineBasicBlock &MBB) const {
-  assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
   MachineFrameInfo &MFI = MF.getFrameInfo();
   const Mips16InstrInfo &TII =
       *static_cast<const Mips16InstrInfo *>(STI.getInstrInfo());
@@ -92,11 +91,11 @@
 
 void Mips16FrameLowering::emitEpilogue(MachineFunction &MF,
                                  MachineBasicBlock &MBB) const {
-  MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
+  MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator();
   MachineFrameInfo &MFI = MF.getFrameInfo();
   const Mips16InstrInfo &TII =
       *static_cast<const Mips16InstrInfo *>(STI.getInstrInfo());
-  DebugLoc dl = MBBI->getDebugLoc();
+  DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
   uint64_t StackSize = MFI.getStackSize();
 
   if (!StackSize)
@@ -117,7 +116,6 @@
                           const std::vector<CalleeSavedInfo> &CSI,
                           const TargetRegisterInfo *TRI) const {
   MachineFunction *MF = MBB.getParent();
-  MachineBasicBlock *EntryBlock = &MF->front();
 
   //
   // Registers RA, S0,S1 are the callee saved registers and they
@@ -134,7 +132,7 @@
     bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA)
       && MF->getFrameInfo().isReturnAddressTaken();
     if (!IsRAAndRetAddrIsTaken)
-      EntryBlock->addLiveIn(Reg);
+      MBB.addLiveIn(Reg);
   }
 
   return true;
Index: lib/Target/Mips/MipsFrameLowering.h
===================================================================
--- lib/Target/Mips/MipsFrameLowering.h
+++ lib/Target/Mips/MipsFrameLowering.h
@@ -36,6 +36,10 @@
 
   bool isFPCloseToIncomingSP() const override { return false; }
 
+  bool enableShrinkWrapping(const MachineFunction &MF) const override {
+    return true;
+  }
+
   MachineBasicBlock::iterator
   eliminateCallFramePseudoInstr(MachineFunction &MF,
                                 MachineBasicBlock &MBB,
Index: lib/Target/Mips/MipsSEFrameLowering.cpp
===================================================================
--- lib/Target/Mips/MipsSEFrameLowering.cpp
+++ lib/Target/Mips/MipsSEFrameLowering.cpp
@@ -394,7 +394,6 @@
 
 void MipsSEFrameLowering::emitPrologue(MachineFunction &MF,
                                        MachineBasicBlock &MBB) const {
-  assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
   MachineFrameInfo &MFI    = MF.getFrameInfo();
   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
 
@@ -682,7 +681,7 @@
 
 void MipsSEFrameLowering::emitEpilogue(MachineFunction &MF,
                                        MachineBasicBlock &MBB) const {
-  MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
+  MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator();
   MachineFrameInfo &MFI            = MF.getFrameInfo();
   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
 
@@ -691,7 +690,7 @@
   const MipsRegisterInfo &RegInfo =
       *static_cast<const MipsRegisterInfo *>(STI.getRegisterInfo());
 
-  DebugLoc DL = MBBI->getDebugLoc();
+  DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
   MipsABIInfo ABI = STI.getABI();
   unsigned SP = ABI.GetStackPtr();
   unsigned FP = ABI.GetFramePtr();
@@ -790,7 +789,6 @@
                           const std::vector<CalleeSavedInfo> &CSI,
                           const TargetRegisterInfo *TRI) const {
   MachineFunction *MF = MBB.getParent();
-  MachineBasicBlock *EntryBlock = &MF->front();
   const TargetInstrInfo &TII = *STI.getInstrInfo();
 
   for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
@@ -803,7 +801,7 @@
     bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA || Reg == Mips::RA_64)
         && MF->getFrameInfo().isReturnAddressTaken();
     if (!IsRAAndRetAddrIsTaken)
-      EntryBlock->addLiveIn(Reg);
+      MBB.addLiveIn(Reg);
 
     // ISRs require HI/LO to be spilled into kernel registers to be then
     // spilled to the stack frame.
@@ -828,7 +826,7 @@
     // Insert the spill to the stack frame.
     bool IsKill = !IsRAAndRetAddrIsTaken;
     const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
-    TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill,
+    TII.storeRegToStackSlot(MBB, MI, Reg, IsKill,
                             CSI[i].getFrameIdx(), RC, TRI);
   }
 
Index: test/CodeGen/Mips/blez_bgez.ll
===================================================================
--- test/CodeGen/Mips/blez_bgez.ll
+++ test/CodeGen/Mips/blez_bgez.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=mipsel < %s | FileCheck %s
-; RUN: llc -march=mips64el < %s | FileCheck %s
+; RUN: llc -march=mipsel -enable-shrink-wrap=false  < %s | FileCheck %s
+; RUN: llc -march=mips64el -enable-shrink-wrap=false < %s | FileCheck %s
 
 ; CHECK-LABEL: test_blez:
 ; CHECK: blez ${{[0-9]+}}, {{\$|\.L}}BB
Index: test/CodeGen/Mips/brdelayslot.ll
===================================================================
--- test/CodeGen/Mips/brdelayslot.ll
+++ test/CodeGen/Mips/brdelayslot.ll
@@ -6,6 +6,7 @@
 ; RUN: llc -march=mipsel -disable-mips-df-forward-search=false \
 ; RUN: -relocation-model=static < %s | FileCheck %s -check-prefix=FORWARD
 ; RUN: llc -march=mipsel -disable-mips-df-backward-search -relocation-model=pic \
+; RUN: -enable-shrink-wrap=false \
 ; RUN: -disable-mips-df-succbb-search=false -disable-preheader-prot=true < %s | \
 ; RUN: FileCheck %s -check-prefix=SUCCBB
 
Index: test/CodeGen/Mips/shrink-wrapping.ll
===================================================================
--- /dev/null
+++ test/CodeGen/Mips/shrink-wrapping.ll
@@ -0,0 +1,34 @@
+; RUN: llc -march=mips -enable-shrink-wrap=true < %s | \
+; RUN:   FileCheck %s -check-prefixes=SHRINK-WRAP,ALL
+
+; RUN: llc -march=mips -enable-shrink-wrap=false < %s | \
+; RUN:   FileCheck %s -check-prefixes=NO-SHRINK-WRAP,ALL
+
+define dso_local i32 @foo(i32 signext %a) local_unnamed_addr nounwind {
+entry:
+; ALL: %bb.0:
+; SHRINK-WRAP-NEXT: beqz
+; NO-SHRINK-WRAP-NEXT: addiu $sp, $sp, -[[SIZE:[0-9]+]]
+; NO-SHRINK-WRAP-NEXT: sw $ra, {{[0-9]+}}($sp)
+  %cmp = icmp eq i32 %a, 0
+  br i1 %cmp, label %return, label %if.end
+
+if.end:
+; ALL: %bb.1:
+; SHRINK-WRAP-NEXT: addiu $sp, $sp, -[[SIZE:[0-9]+]]
+; SHRINK-WRAP-NEXT: sw $ra, {{[0-9]+}}($sp)
+  %add = add nsw i32 %a, 1
+  tail call void @foo2(i32 signext %add)
+; SHRINK-WRAP: lw $ra, {{[0-9]+}}($sp)
+; SHRINK-WRAP-NEXT: addiu $sp, $sp, [[SIZE]]
+  br label %return
+
+return:
+; ALL: BB0_2
+; NO-SHRINK-WRAP: lw $ra, {{[0-9]+}}($sp)
+; NO-SHRINK-WRAP: addiu $sp, $sp, [[SIZE]]
+; SHRINK-WRAP-NOT: addiu $sp, $sp
+  ret i32 0
+}
+
+declare dso_local void @foo2(i32 signext) local_unnamed_addr