Index: lib/Target/Mips/MipsBranchExpansion.cpp =================================================================== --- lib/Target/Mips/MipsBranchExpansion.cpp +++ lib/Target/Mips/MipsBranchExpansion.cpp @@ -446,7 +446,7 @@ // operands to lowered instructions. BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_LUi), Mips::AT) - .addMBB(TgtMBB) + .addMBB(TgtMBB, MipsII::MO_ABS_HI) .addMBB(BalTgtMBB); MachineInstrBuilder BalInstr = @@ -454,7 +454,7 @@ MachineInstrBuilder ADDiuInstr = BuildMI(*MFp, DL, TII->get(Mips::LONG_BRANCH_ADDiu), Mips::AT) .addReg(Mips::AT) - .addMBB(TgtMBB) + .addMBB(TgtMBB, MipsII::MO_ABS_LO) .addMBB(BalTgtMBB); if (STI->hasMips32r6()) { LongBrMBB->insert(Pos, ADDiuInstr); Index: lib/Target/Mips/MipsMCInstLower.h =================================================================== --- lib/Target/Mips/MipsMCInstLower.h +++ lib/Target/Mips/MipsMCInstLower.h @@ -44,8 +44,8 @@ MCOperand createSub(MachineBasicBlock *BB1, MachineBasicBlock *BB2, MipsMCExpr::MipsExprKind Kind) const; void lowerLongBranchLUi(const MachineInstr *MI, MCInst &OutMI) const; - void lowerLongBranchADDiu(const MachineInstr *MI, MCInst &OutMI, int Opcode, - MipsMCExpr::MipsExprKind Kind) const; + void lowerLongBranchADDiu(const MachineInstr *MI, MCInst &OutMI, + int Opcode) const; bool lowerLongBranch(const MachineInstr *MI, MCInst &OutMI) const; }; Index: lib/Target/Mips/MipsMCInstLower.cpp =================================================================== --- lib/Target/Mips/MipsMCInstLower.cpp +++ lib/Target/Mips/MipsMCInstLower.cpp @@ -219,26 +219,78 @@ // Lower register operand. OutMI.addOperand(LowerOperand(MI->getOperand(0))); - // Create %hi($tgt-$baltgt). - OutMI.addOperand(createSub(MI->getOperand(1).getMBB(), - MI->getOperand(2).getMBB(), - MipsMCExpr::MEK_HI)); + MipsMCExpr::MipsExprKind Kind; + unsigned TargetFlags = MI->getOperand(1).getTargetFlags(); + switch (TargetFlags) { + case MipsII::MO_HIGHEST: + Kind = MipsMCExpr::MEK_HIGHEST; + break; + case MipsII::MO_HIGHER: + Kind = MipsMCExpr::MEK_HIGHER; + break; + case MipsII::MO_ABS_HI: + Kind = MipsMCExpr::MEK_HI; + break; + case MipsII::MO_ABS_LO: + Kind = MipsMCExpr::MEK_LO; + break; + default: + report_fatal_error("Unexpected flags for lowerLongBranchLUi"); + } + + if (MI->getNumOperands() == 2) { + const MCExpr *Expr = + MCSymbolRefExpr::create(MI->getOperand(1).getMBB()->getSymbol(), *Ctx); + const MipsMCExpr *MipsExpr = MipsMCExpr::create(Kind, Expr, *Ctx); + OutMI.addOperand(MCOperand::createExpr(MipsExpr)); + } else if (MI->getNumOperands() == 3) { + // Create %hi($tgt-$baltgt). + OutMI.addOperand(createSub(MI->getOperand(1).getMBB(), + MI->getOperand(2).getMBB(), Kind)); + } } -void MipsMCInstLower::lowerLongBranchADDiu( - const MachineInstr *MI, MCInst &OutMI, int Opcode, - MipsMCExpr::MipsExprKind Kind) const { +void MipsMCInstLower::lowerLongBranchADDiu(const MachineInstr *MI, + MCInst &OutMI, int Opcode) const { OutMI.setOpcode(Opcode); + MipsMCExpr::MipsExprKind Kind; + unsigned TargetFlags = MI->getOperand(2).getTargetFlags(); + switch (TargetFlags) { + case MipsII::MO_HIGHEST: + Kind = MipsMCExpr::MEK_HIGHEST; + break; + case MipsII::MO_HIGHER: + Kind = MipsMCExpr::MEK_HIGHER; + break; + case MipsII::MO_ABS_HI: + Kind = MipsMCExpr::MEK_HI; + break; + case MipsII::MO_ABS_LO: + Kind = MipsMCExpr::MEK_LO; + break; + default: + report_fatal_error("Unexpected flags for lowerLongBranchADDiu"); + ; + } + // Lower two register operands. for (unsigned I = 0, E = 2; I != E; ++I) { const MachineOperand &MO = MI->getOperand(I); OutMI.addOperand(LowerOperand(MO)); } - // Create %lo($tgt-$baltgt) or %hi($tgt-$baltgt). - OutMI.addOperand(createSub(MI->getOperand(2).getMBB(), - MI->getOperand(3).getMBB(), Kind)); + if (MI->getNumOperands() == 3) { + // Lower register operand. + const MCExpr *Expr = + MCSymbolRefExpr::create(MI->getOperand(2).getMBB()->getSymbol(), *Ctx); + const MipsMCExpr *MipsExpr = MipsMCExpr::create(Kind, Expr, *Ctx); + OutMI.addOperand(MCOperand::createExpr(MipsExpr)); + } else if (MI->getNumOperands() == 4) { + // Create %lo($tgt-$baltgt) or %hi($tgt-$baltgt). + OutMI.addOperand(createSub(MI->getOperand(2).getMBB(), + MI->getOperand(3).getMBB(), Kind)); + } } bool MipsMCInstLower::lowerLongBranch(const MachineInstr *MI, @@ -250,16 +302,10 @@ lowerLongBranchLUi(MI, OutMI); return true; case Mips::LONG_BRANCH_ADDiu: - lowerLongBranchADDiu(MI, OutMI, Mips::ADDiu, MipsMCExpr::MEK_LO); + lowerLongBranchADDiu(MI, OutMI, Mips::ADDiu); return true; case Mips::LONG_BRANCH_DADDiu: - unsigned TargetFlags = MI->getOperand(2).getTargetFlags(); - if (TargetFlags == MipsII::MO_ABS_HI) - lowerLongBranchADDiu(MI, OutMI, Mips::DADDiu, MipsMCExpr::MEK_HI); - else if (TargetFlags == MipsII::MO_ABS_LO) - lowerLongBranchADDiu(MI, OutMI, Mips::DADDiu, MipsMCExpr::MEK_LO); - else - report_fatal_error("Unexpected flags for LONG_BRANCH_DADDiu"); + lowerLongBranchADDiu(MI, OutMI, Mips::DADDiu); return true; } } Index: test/CodeGen/Mips/longbranch/branch-limits-fp-micromips.mir =================================================================== --- test/CodeGen/Mips/longbranch/branch-limits-fp-micromips.mir +++ test/CodeGen/Mips/longbranch/branch-limits-fp-micromips.mir @@ -98,9 +98,9 @@ ; PIC: successors: %bb.2(0x80000000) ; PIC: $sp = ADDiu $sp, -8 ; PIC: SW $ra, $sp, 0 - ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2 ; PIC: BAL_BR_MM %bb.2, implicit-def $ra { - ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2 ; PIC: } ; PIC: bb.2.entry: ; PIC: successors: %bb.4(0x80000000) Index: test/CodeGen/Mips/longbranch/branch-limits-fp-micromipsr6.mir =================================================================== --- test/CodeGen/Mips/longbranch/branch-limits-fp-micromipsr6.mir +++ test/CodeGen/Mips/longbranch/branch-limits-fp-micromipsr6.mir @@ -92,8 +92,8 @@ ; PIC: successors: %bb.2(0x80000000) ; PIC: $sp = ADDiu $sp, -8 ; PIC: SW $ra, $sp, 0 - ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 - ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2 ; PIC: BALC_MMR6 %bb.2, implicit-def $ra ; PIC: bb.2.entry: ; PIC: successors: %bb.4(0x80000000) @@ -184,8 +184,8 @@ ; PIC: successors: %bb.2(0x80000000) ; PIC: $sp = ADDiu $sp, -8 ; PIC: SW $ra, $sp, 0 - ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 - ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2 ; PIC: BALC_MMR6 %bb.2, implicit-def $ra ; PIC: bb.2.entry: ; PIC: successors: %bb.4(0x80000000) Index: test/CodeGen/Mips/longbranch/branch-limits-fp-mips.mir =================================================================== --- test/CodeGen/Mips/longbranch/branch-limits-fp-mips.mir +++ test/CodeGen/Mips/longbranch/branch-limits-fp-mips.mir @@ -99,9 +99,9 @@ ; PIC: successors: %bb.2(0x80000000) ; PIC: $sp = ADDiu $sp, -8 ; PIC: SW $ra, $sp, 0 - ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2 ; PIC: BAL_BR %bb.2, implicit-def $ra { - ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2 ; PIC: } ; PIC: bb.2.entry: ; PIC: successors: %bb.4(0x80000000) @@ -203,9 +203,9 @@ ; PIC: successors: %bb.2(0x80000000) ; PIC: $sp = ADDiu $sp, -8 ; PIC: SW $ra, $sp, 0 - ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2 ; PIC: BAL_BR %bb.2, implicit-def $ra { - ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2 ; PIC: } ; PIC: bb.2.entry: ; PIC: successors: %bb.4(0x80000000) Index: test/CodeGen/Mips/longbranch/branch-limits-fp-mipsr6.mir =================================================================== --- test/CodeGen/Mips/longbranch/branch-limits-fp-mipsr6.mir +++ test/CodeGen/Mips/longbranch/branch-limits-fp-mipsr6.mir @@ -99,8 +99,8 @@ ; PIC: successors: %bb.2(0x80000000) ; PIC: $sp = ADDiu $sp, -8 ; PIC: SW $ra, $sp, 0 - ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 - ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2 ; PIC: BALC %bb.2, implicit-def $ra ; PIC: bb.2.entry: ; PIC: successors: %bb.4(0x80000000) @@ -199,8 +199,8 @@ ; PIC: successors: %bb.2(0x80000000) ; PIC: $sp = ADDiu $sp, -8 ; PIC: SW $ra, $sp, 0 - ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 - ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2 ; PIC: BALC %bb.2, implicit-def $ra ; PIC: bb.2.entry: ; PIC: successors: %bb.4(0x80000000) Index: test/CodeGen/Mips/longbranch/branch-limits-int-microMIPS.mir =================================================================== --- test/CodeGen/Mips/longbranch/branch-limits-int-microMIPS.mir +++ test/CodeGen/Mips/longbranch/branch-limits-int-microMIPS.mir @@ -153,9 +153,9 @@ ; PIC: successors: %bb.2(0x80000000) ; PIC: $sp = ADDiu $sp, -8 ; PIC: SW $ra, $sp, 0 - ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2 ; PIC: BAL_BR_MM %bb.2, implicit-def $ra { - ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2 ; PIC: } ; PIC: bb.2 (%ir-block.0): ; PIC: successors: %bb.4(0x80000000) @@ -248,9 +248,9 @@ ; PIC: successors: %bb.2(0x80000000) ; PIC: $sp = ADDiu $sp, -8 ; PIC: SW $ra, $sp, 0 - ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2 ; PIC: BAL_BR_MM %bb.2, implicit-def $ra { - ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2 ; PIC: } ; PIC: bb.2 (%ir-block.0): ; PIC: successors: %bb.4(0x80000000) @@ -343,9 +343,9 @@ ; PIC: successors: %bb.2(0x80000000) ; PIC: $sp = ADDiu $sp, -8 ; PIC: SW $ra, $sp, 0 - ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2 ; PIC: BAL_BR_MM %bb.2, implicit-def $ra { - ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2 ; PIC: } ; PIC: bb.2 (%ir-block.0): ; PIC: successors: %bb.4(0x80000000) @@ -438,9 +438,9 @@ ; PIC: successors: %bb.2(0x80000000) ; PIC: $sp = ADDiu $sp, -8 ; PIC: SW $ra, $sp, 0 - ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2 ; PIC: BAL_BR_MM %bb.2, implicit-def $ra { - ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2 ; PIC: } ; PIC: bb.2 (%ir-block.0): ; PIC: successors: %bb.4(0x80000000) @@ -533,9 +533,9 @@ ; PIC: successors: %bb.2(0x80000000) ; PIC: $sp = ADDiu $sp, -8 ; PIC: SW $ra, $sp, 0 - ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2 ; PIC: BAL_BR_MM %bb.2, implicit-def $ra { - ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2 ; PIC: } ; PIC: bb.2 (%ir-block.0): ; PIC: successors: %bb.4(0x80000000) @@ -624,9 +624,9 @@ ; PIC: successors: %bb.2(0x80000000) ; PIC: $sp = ADDiu $sp, -8 ; PIC: SW $ra, $sp, 0 - ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2 ; PIC: BAL_BR_MM %bb.2, implicit-def $ra { - ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2 ; PIC: } ; PIC: bb.2 (%ir-block.0): ; PIC: successors: %bb.4(0x80000000) @@ -719,9 +719,9 @@ ; PIC: successors: %bb.2(0x80000000) ; PIC: $sp = ADDiu $sp, -8 ; PIC: SW $ra, $sp, 0 - ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2 ; PIC: BAL_BR_MM %bb.2, implicit-def $ra { - ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2 ; PIC: } ; PIC: bb.2 (%ir-block.0): ; PIC: successors: %bb.4(0x80000000) @@ -814,9 +814,9 @@ ; PIC: successors: %bb.2(0x80000000) ; PIC: $sp = ADDiu $sp, -8 ; PIC: SW $ra, $sp, 0 - ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2 ; PIC: BAL_BR_MM %bb.2, implicit-def $ra { - ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2 ; PIC: } ; PIC: bb.2 (%ir-block.0): ; PIC: successors: %bb.4(0x80000000) Index: test/CodeGen/Mips/longbranch/branch-limits-int-micromipsr6.mir =================================================================== --- test/CodeGen/Mips/longbranch/branch-limits-int-micromipsr6.mir +++ test/CodeGen/Mips/longbranch/branch-limits-int-micromipsr6.mir @@ -195,8 +195,8 @@ ; PIC: successors: %bb.2(0x80000000) ; PIC: $sp = ADDiu $sp, -8 ; PIC: SW $ra, $sp, 0 - ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 - ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2 ; PIC: BALC_MMR6 %bb.2, implicit-def $ra ; PIC: bb.2 (%ir-block.0): ; PIC: successors: %bb.4(0x80000000) @@ -282,8 +282,8 @@ ; PIC: successors: %bb.2(0x80000000) ; PIC: $sp = ADDiu $sp, -8 ; PIC: SW $ra, $sp, 0 - ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 - ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2 ; PIC: BALC_MMR6 %bb.2, implicit-def $ra ; PIC: bb.2 (%ir-block.0): ; PIC: successors: %bb.4(0x80000000) @@ -369,8 +369,8 @@ ; PIC: successors: %bb.2(0x80000000) ; PIC: $sp = ADDiu $sp, -8 ; PIC: SW $ra, $sp, 0 - ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 - ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2 ; PIC: BALC_MMR6 %bb.2, implicit-def $ra ; PIC: bb.2 (%ir-block.0): ; PIC: successors: %bb.4(0x80000000) @@ -456,8 +456,8 @@ ; PIC: successors: %bb.2(0x80000000) ; PIC: $sp = ADDiu $sp, -8 ; PIC: SW $ra, $sp, 0 - ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 - ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2 ; PIC: BALC_MMR6 %bb.2, implicit-def $ra ; PIC: bb.2 (%ir-block.0): ; PIC: successors: %bb.4(0x80000000) @@ -543,8 +543,8 @@ ; PIC: successors: %bb.2(0x80000000) ; PIC: $sp = ADDiu $sp, -8 ; PIC: SW $ra, $sp, 0 - ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 - ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2 ; PIC: BALC_MMR6 %bb.2, implicit-def $ra ; PIC: bb.2 (%ir-block.0): ; PIC: successors: %bb.4(0x80000000) @@ -630,8 +630,8 @@ ; PIC: successors: %bb.2(0x80000000) ; PIC: $sp = ADDiu $sp, -8 ; PIC: SW $ra, $sp, 0 - ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 - ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2 ; PIC: BALC_MMR6 %bb.2, implicit-def $ra ; PIC: bb.2 (%ir-block.0): ; PIC: successors: %bb.4(0x80000000) @@ -717,8 +717,8 @@ ; PIC: successors: %bb.2(0x80000000) ; PIC: $sp = ADDiu $sp, -8 ; PIC: SW $ra, $sp, 0 - ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 - ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2 ; PIC: BALC_MMR6 %bb.2, implicit-def $ra ; PIC: bb.2 (%ir-block.0): ; PIC: successors: %bb.4(0x80000000) @@ -804,8 +804,8 @@ ; PIC: successors: %bb.2(0x80000000) ; PIC: $sp = ADDiu $sp, -8 ; PIC: SW $ra, $sp, 0 - ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 - ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2 ; PIC: BALC_MMR6 %bb.2, implicit-def $ra ; PIC: bb.2 (%ir-block.0): ; PIC: successors: %bb.4(0x80000000) @@ -891,8 +891,8 @@ ; PIC: successors: %bb.2(0x80000000) ; PIC: $sp = ADDiu $sp, -8 ; PIC: SW $ra, $sp, 0 - ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 - ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2 ; PIC: BALC_MMR6 %bb.2, implicit-def $ra ; PIC: bb.2 (%ir-block.0): ; PIC: successors: %bb.4(0x80000000) @@ -978,8 +978,8 @@ ; PIC: successors: %bb.2(0x80000000) ; PIC: $sp = ADDiu $sp, -8 ; PIC: SW $ra, $sp, 0 - ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 - ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2 ; PIC: BALC_MMR6 %bb.2, implicit-def $ra ; PIC: bb.2 (%ir-block.0): ; PIC: successors: %bb.4(0x80000000) @@ -1065,8 +1065,8 @@ ; PIC: successors: %bb.2(0x80000000) ; PIC: $sp = ADDiu $sp, -8 ; PIC: SW $ra, $sp, 0 - ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 - ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2 ; PIC: BALC_MMR6 %bb.2, implicit-def $ra ; PIC: bb.2 (%ir-block.0): ; PIC: successors: %bb.4(0x80000000) @@ -1152,8 +1152,8 @@ ; PIC: successors: %bb.2(0x80000000) ; PIC: $sp = ADDiu $sp, -8 ; PIC: SW $ra, $sp, 0 - ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 - ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2 ; PIC: BALC_MMR6 %bb.2, implicit-def $ra ; PIC: bb.2 (%ir-block.0): ; PIC: successors: %bb.4(0x80000000) Index: test/CodeGen/Mips/longbranch/branch-limits-int-mipsr6.mir =================================================================== --- test/CodeGen/Mips/longbranch/branch-limits-int-mipsr6.mir +++ test/CodeGen/Mips/longbranch/branch-limits-int-mipsr6.mir @@ -195,8 +195,8 @@ ; PIC: successors: %bb.2(0x80000000) ; PIC: $sp = ADDiu $sp, -8 ; PIC: SW $ra, $sp, 0 - ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 - ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2 ; PIC: BALC %bb.2, implicit-def $ra ; PIC: bb.2 (%ir-block.0): ; PIC: successors: %bb.4(0x80000000) @@ -282,8 +282,8 @@ ; PIC: successors: %bb.2(0x80000000) ; PIC: $sp = ADDiu $sp, -8 ; PIC: SW $ra, $sp, 0 - ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 - ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2 ; PIC: BALC %bb.2, implicit-def $ra ; PIC: bb.2 (%ir-block.0): ; PIC: successors: %bb.4(0x80000000) @@ -369,8 +369,8 @@ ; PIC: successors: %bb.2(0x80000000) ; PIC: $sp = ADDiu $sp, -8 ; PIC: SW $ra, $sp, 0 - ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 - ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2 ; PIC: BALC %bb.2, implicit-def $ra ; PIC: bb.2 (%ir-block.0): ; PIC: successors: %bb.4(0x80000000) @@ -456,8 +456,8 @@ ; PIC: successors: %bb.2(0x80000000) ; PIC: $sp = ADDiu $sp, -8 ; PIC: SW $ra, $sp, 0 - ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 - ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2 ; PIC: BALC %bb.2, implicit-def $ra ; PIC: bb.2 (%ir-block.0): ; PIC: successors: %bb.4(0x80000000) @@ -543,8 +543,8 @@ ; PIC: successors: %bb.2(0x80000000) ; PIC: $sp = ADDiu $sp, -8 ; PIC: SW $ra, $sp, 0 - ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 - ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2 ; PIC: BALC %bb.2, implicit-def $ra ; PIC: bb.2 (%ir-block.0): ; PIC: successors: %bb.4(0x80000000) @@ -630,8 +630,8 @@ ; PIC: successors: %bb.2(0x80000000) ; PIC: $sp = ADDiu $sp, -8 ; PIC: SW $ra, $sp, 0 - ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 - ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2 ; PIC: BALC %bb.2, implicit-def $ra ; PIC: bb.2 (%ir-block.0): ; PIC: successors: %bb.4(0x80000000) @@ -717,8 +717,8 @@ ; PIC: successors: %bb.2(0x80000000) ; PIC: $sp = ADDiu $sp, -8 ; PIC: SW $ra, $sp, 0 - ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 - ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2 ; PIC: BALC %bb.2, implicit-def $ra ; PIC: bb.2 (%ir-block.0): ; PIC: successors: %bb.4(0x80000000) @@ -804,8 +804,8 @@ ; PIC: successors: %bb.2(0x80000000) ; PIC: $sp = ADDiu $sp, -8 ; PIC: SW $ra, $sp, 0 - ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 - ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2 ; PIC: BALC %bb.2, implicit-def $ra ; PIC: bb.2 (%ir-block.0): ; PIC: successors: %bb.4(0x80000000) @@ -891,8 +891,8 @@ ; PIC: successors: %bb.2(0x80000000) ; PIC: $sp = ADDiu $sp, -8 ; PIC: SW $ra, $sp, 0 - ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 - ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2 ; PIC: BALC %bb.2, implicit-def $ra ; PIC: bb.2 (%ir-block.0): ; PIC: successors: %bb.4(0x80000000) @@ -978,8 +978,8 @@ ; PIC: successors: %bb.2(0x80000000) ; PIC: $sp = ADDiu $sp, -8 ; PIC: SW $ra, $sp, 0 - ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 - ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2 ; PIC: BALC %bb.2, implicit-def $ra ; PIC: bb.2 (%ir-block.0): ; PIC: successors: %bb.4(0x80000000) @@ -1065,8 +1065,8 @@ ; PIC: successors: %bb.2(0x80000000) ; PIC: $sp = ADDiu $sp, -8 ; PIC: SW $ra, $sp, 0 - ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 - ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2 ; PIC: BALC %bb.2, implicit-def $ra ; PIC: bb.2 (%ir-block.0): ; PIC: successors: %bb.4(0x80000000) @@ -1152,8 +1152,8 @@ ; PIC: successors: %bb.2(0x80000000) ; PIC: $sp = ADDiu $sp, -8 ; PIC: SW $ra, $sp, 0 - ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 - ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2 ; PIC: BALC %bb.2, implicit-def $ra ; PIC: bb.2 (%ir-block.0): ; PIC: successors: %bb.4(0x80000000) Index: test/CodeGen/Mips/longbranch/branch-limits-int.mir =================================================================== --- test/CodeGen/Mips/longbranch/branch-limits-int.mir +++ test/CodeGen/Mips/longbranch/branch-limits-int.mir @@ -137,9 +137,9 @@ ; PIC: successors: %bb.2(0x80000000) ; PIC: $sp = ADDiu $sp, -8 ; PIC: SW $ra, $sp, 0 - ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2 ; PIC: BAL_BR %bb.2, implicit-def $ra { - ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2 ; PIC: } ; PIC: bb.2 (%ir-block.0): ; PIC: successors: %bb.4(0x80000000) @@ -236,9 +236,9 @@ ; PIC: successors: %bb.2(0x80000000) ; PIC: $sp = ADDiu $sp, -8 ; PIC: SW $ra, $sp, 0 - ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2 ; PIC: BAL_BR %bb.2, implicit-def $ra { - ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2 ; PIC: } ; PIC: bb.2 (%ir-block.0): ; PIC: successors: %bb.4(0x80000000) @@ -335,9 +335,9 @@ ; PIC: successors: %bb.2(0x80000000) ; PIC: $sp = ADDiu $sp, -8 ; PIC: SW $ra, $sp, 0 - ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2 ; PIC: BAL_BR %bb.2, implicit-def $ra { - ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2 ; PIC: } ; PIC: bb.2 (%ir-block.0): ; PIC: successors: %bb.4(0x80000000) @@ -434,9 +434,9 @@ ; PIC: successors: %bb.2(0x80000000) ; PIC: $sp = ADDiu $sp, -8 ; PIC: SW $ra, $sp, 0 - ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2 ; PIC: BAL_BR %bb.2, implicit-def $ra { - ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2 ; PIC: } ; PIC: bb.2 (%ir-block.0): ; PIC: successors: %bb.4(0x80000000) @@ -533,9 +533,9 @@ ; PIC: successors: %bb.2(0x80000000) ; PIC: $sp = ADDiu $sp, -8 ; PIC: SW $ra, $sp, 0 - ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2 ; PIC: BAL_BR %bb.2, implicit-def $ra { - ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2 ; PIC: } ; PIC: bb.2 (%ir-block.0): ; PIC: successors: %bb.4(0x80000000) @@ -632,9 +632,9 @@ ; PIC: successors: %bb.2(0x80000000) ; PIC: $sp = ADDiu $sp, -8 ; PIC: SW $ra, $sp, 0 - ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2 ; PIC: BAL_BR %bb.2, implicit-def $ra { - ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2 + ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2 ; PIC: } ; PIC: bb.2 (%ir-block.0): ; PIC: successors: %bb.4(0x80000000)