Index: lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp =================================================================== --- lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp +++ lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp @@ -443,7 +443,7 @@ } bool isVSrcB32() const { - return isVCSrcF32() || isLiteralImm(MVT::i32); + return isVCSrcF32() || isLiteralImm(MVT::i32) || isExpr(); } bool isVSrcB64() const { @@ -460,7 +460,7 @@ } bool isVSrcF32() const { - return isVCSrcF32() || isLiteralImm(MVT::f32); + return isVCSrcF32() || isLiteralImm(MVT::f32) || isExpr(); } bool isVSrcF64() const { Index: test/MC/AMDGPU/expressions.s =================================================================== --- test/MC/AMDGPU/expressions.s +++ test/MC/AMDGPU/expressions.s @@ -40,6 +40,9 @@ s_mov_b32 s0, foo+2 // VI: s_mov_b32 s0, 514 ; encoding: [0xff,0x00,0x80,0xbe,0x02,0x02,0x00,0x00] +v_mul_f32 v0, foo+2, v2 +// VI: v_mul_f32_e32 v0, 514, v2 ; encoding: [0xff,0x04,0x00,0x0a,0x02,0x02,0x00,0x00] + BB1: v_nop_e64 BB2: Index: test/MC/AMDGPU/reloc.s =================================================================== --- test/MC/AMDGPU/reloc.s +++ test/MC/AMDGPU/reloc.s @@ -9,6 +9,13 @@ // CHECK: R_AMDGPU_GOTPCREL32_HI global_var2 0x0 // CHECK: R_AMDGPU_REL32_LO global_var3 0x0 // CHECK: R_AMDGPU_REL32_HI global_var4 0x0 +// CHECK: R_AMDGPU_ABS32_LO SCRATCH_RSRC_DWORD0 0x0 +// CHECK: R_AMDGPU_ABS32_HI SCRATCH_RSRC_DWORD1 0x0 +// CHECK: R_AMDGPU_GOTPCREL global_var0 0x0 +// CHECK: R_AMDGPU_GOTPCREL32_LO global_var1 0x0 +// CHECK: R_AMDGPU_GOTPCREL32_HI global_var2 0x0 +// CHECK: R_AMDGPU_REL32_LO global_var3 0x0 +// CHECK: R_AMDGPU_REL32_HI global_var4 0x0 // CHECK: R_AMDGPU_ABS32 var 0x0 // CHECK: } // CHECK: .rel.data { @@ -25,6 +32,14 @@ s_mov_b32 s5, global_var3@rel32@lo s_mov_b32 s6, global_var4@rel32@hi + v_mov_b32 v0, SCRATCH_RSRC_DWORD0 + v_mov_b32 v1, SCRATCH_RSRC_DWORD1 + v_mov_b32 v2, global_var0@GOTPCREL + v_mov_b32 v3, global_var1@gotpcrel32@lo + v_mov_b32 v4, global_var2@gotpcrel32@hi + v_mov_b32 v5, global_var3@rel32@lo + v_mov_b32 v6, global_var4@rel32@hi + .globl global_var0 .globl global_var1 .globl global_var2