Index: lib/Target/Mips/MipsInstrFPU.td =================================================================== --- lib/Target/Mips/MipsInstrFPU.td +++ lib/Target/Mips/MipsInstrFPU.td @@ -265,6 +265,75 @@ defm D64 : C_COND_M<"d", FGR64Opnd, 17, II_C_CC_D>, ISA_MIPS1_NOT_32R6_64R6, AdditionalRequires<[IsFP64bit]>; +class C_COND_FT_CC : + InstSE<(outs), (ins FCCRegsOpnd:$cc, RC:$fs, RC:$ft), + !strconcat("c.", CondStr, ".", Typestr, "\t $cc, $fs, $ft"), + [], itin, FrmFR>; + + +multiclass C_COND_M_CC fmt, + InstrItinClass itin> { + def C_F_#NAME : C_COND_FT_CC<"f", TypeStr, RC, itin>, C_COND_FM_CC; + def C_UN_#NAME : C_COND_FT_CC<"un", TypeStr, RC, itin>, C_COND_FM_CC; + def C_EQ_#NAME : C_COND_FT_CC<"eq", TypeStr, RC, itin>, C_COND_FM_CC; + def C_UEQ_#NAME : C_COND_FT_CC<"ueq", TypeStr, RC, itin>, C_COND_FM_CC; + def C_OLT_#NAME : C_COND_FT_CC<"olt", TypeStr, RC, itin>, C_COND_FM_CC; + def C_ULT_#NAME : C_COND_FT_CC<"ult", TypeStr, RC, itin>, C_COND_FM_CC; + def C_OLE_#NAME : C_COND_FT_CC<"ole", TypeStr, RC, itin>, C_COND_FM_CC; + def C_ULE_#NAME : C_COND_FT_CC<"ule", TypeStr, RC, itin>, C_COND_FM_CC; + def C_SF_#NAME : C_COND_FT_CC<"sf", TypeStr, RC, itin>, C_COND_FM_CC; + def C_NGLE_#NAME : C_COND_FT_CC<"ngle", TypeStr, RC, itin>, C_COND_FM_CC; + def C_SEQ_#NAME : C_COND_FT_CC<"seq", TypeStr, RC, itin>, C_COND_FM_CC; + def C_NGL_#NAME : C_COND_FT_CC<"ngl", TypeStr, RC, itin>, C_COND_FM_CC; + def C_LT_#NAME : C_COND_FT_CC<"lt", TypeStr, RC, itin>, C_COND_FM_CC; + def C_NGE_#NAME : C_COND_FT_CC<"nge", TypeStr, RC, itin>, C_COND_FM_CC; + def C_LE_#NAME : C_COND_FT_CC<"le", TypeStr, RC, itin>, C_COND_FM_CC; + def C_NGT_#NAME : C_COND_FT_CC<"ngt", TypeStr, RC, itin>, C_COND_FM_CC; +} + +defm S_CC : C_COND_M_CC<"s", FGR32Opnd, 16, II_C_CC_S>, INSN_MIPS4_32_NOT_32R6_64R6; +defm D32_CC : C_COND_M_CC<"d", AFGR64Opnd, 17, II_C_CC_D>, INSN_MIPS4_32_NOT_32R6_64R6, + AdditionalRequires<[NotFP64bit]>; +let DecoderNamespace = "Mips64" in +defm D64_CC : C_COND_M_CC<"d", FGR64Opnd, 17, II_C_CC_D>, INSN_MIPS4_32_NOT_32R6_64R6, + AdditionalRequires<[IsFP64bit]>; + + +class CCInstAlias: + MipsInstAlias, INSN_MIPS4_32_NOT_32R6_64R6; + +multiclass CCondInstAlias { + def : CCInstAlias; + def : CCInstAlias, + AdditionalRequires<[NotFP64bit]>; + def : CCInstAlias, + AdditionalRequires<[IsFP64bit]>; +} + +defm : CCondInstAlias<"f", C_F_S_CC, C_F_D32_CC, C_F_D64_CC>; +defm : CCondInstAlias<"un", C_UN_S_CC, C_UN_D32_CC, C_UN_D64_CC>; +defm : CCondInstAlias<"eq", C_EQ_S_CC, C_EQ_D32_CC, C_EQ_D64_CC>; +defm : CCondInstAlias<"ueq", C_UEQ_S_CC, C_UEQ_D32_CC, C_UEQ_D64_CC>; +defm : CCondInstAlias<"olt", C_OLT_S_CC, C_OLT_D32_CC, C_OLT_D64_CC>; +defm : CCondInstAlias<"ult", C_ULT_S_CC, C_ULT_D32_CC, C_ULT_D64_CC>; +defm : CCondInstAlias<"ole", C_OLE_S_CC, C_OLE_D32_CC, C_OLE_D64_CC>; +defm : CCondInstAlias<"ule", C_ULE_S_CC, C_ULE_D32_CC, C_ULE_D64_CC>; +defm : CCondInstAlias<"sf", C_SF_S_CC, C_SF_D32_CC, C_SF_D64_CC>; +defm : CCondInstAlias<"ngle", C_NGLE_S_CC, C_NGLE_D32_CC, C_NGLE_D64_CC>; +defm : CCondInstAlias<"seq", C_SEQ_S_CC, C_SEQ_D32_CC, C_SEQ_D64_CC>; +defm : CCondInstAlias<"ngl", C_NGL_S_CC, C_NGL_D32_CC, C_NGL_D64_CC>; +defm : CCondInstAlias<"lt", C_LT_S_CC, C_LT_D32_CC, C_LT_D64_CC>; +defm : CCondInstAlias<"nge", C_NGE_S_CC, C_NGE_D32_CC, C_NGE_D64_CC>; +defm : CCondInstAlias<"le", C_LE_S_CC, C_LE_D32_CC, C_LE_D64_CC>; +defm : CCondInstAlias<"ngt", C_NGT_S_CC, C_NGT_D32_CC, C_NGT_D64_CC>; + //===----------------------------------------------------------------------===// // Floating Point Instructions //===----------------------------------------------------------------------===// Index: lib/Target/Mips/MipsInstrFormats.td =================================================================== --- lib/Target/Mips/MipsInstrFormats.td +++ lib/Target/Mips/MipsInstrFormats.td @@ -791,10 +791,11 @@ let Inst{15-0} = offset; } -class CEQS_FM fmt> : StdArch { +class CEQS_FM_CC fmt> : StdArch { bits<5> fs; bits<5> ft; bits<4> cond; + bits<3> cc; bits<32> Inst; @@ -802,15 +803,34 @@ let Inst{25-21} = fmt; let Inst{20-16} = ft; let Inst{15-11} = fs; - let Inst{10-8} = 0; // cc + let Inst{10-8} = cc; let Inst{7-4} = 0x3; let Inst{3-0} = cond; } +class CEQS_FM fmt> : StdArch { + bits<5> fs; + bits<5> ft; + bits<4> cond; + + bits<32> Inst; + + let Inst{31-26} = 0x11; + let Inst{25-21} = fmt; + let Inst{20-16} = ft; + let Inst{15-11} = fs; + let Inst{10-4} = 0x3; + let Inst{3-0} = cond; +} + class C_COND_FM fmt, bits<4> c> : CEQS_FM { let cond = c; } +class C_COND_FM_CC fmt, bits<4> c> : CEQS_FM_CC { + let cond = c; +} + class CMov_I_F_FM funct, bits<5> fmt> : StdArch { bits<5> fd; bits<5> fs; Index: test/MC/Disassembler/Mips/mips32/valid-mips32-el.txt =================================================================== --- test/MC/Disassembler/Mips/mips32/valid-mips32-el.txt +++ test/MC/Disassembler/Mips/mips32/valid-mips32-el.txt @@ -44,6 +44,34 @@ 0x3a 0x30 0x07 0x46 # CHECK: c.seq.s $f6, $f7 0x38 0x60 0x2e 0x46 # CHECK: c.sf.d $f12, $f14 0x38 0x30 0x07 0x46 # CHECK: c.sf.s $f6, $f7 +0x32 0x71 0x2e 0x46 # CHECK: c.eq.d $fcc1, $f14, $f14 +0x32 0xc5 0x11 0x46 # CHECK: c.eq.s $fcc5, $f24, $f17 +0x30 0x54 0x34 0x46 # CHECK: c.f.d $fcc4, $f10, $f20 +0x30 0xf4 0x07 0x46 # CHECK: c.f.s $fcc4, $f30, $f7 +0x3e 0x94 0x22 0x46 # CHECK: c.le.d $fcc4, $f18, $f2 +0x3e 0xc6 0x04 0x46 # CHECK: c.le.s $fcc6, $f24, $f4 +0x3c 0x43 0x22 0x46 # CHECK: c.lt.d $fcc3, $f8, $f2 +0x3c 0x8a 0x0e 0x46 # CHECK: c.lt.s $fcc2, $f17, $f14 +0x3d 0xa5 0x30 0x46 # CHECK: c.nge.d $fcc5, $f20, $f16 +0x3d 0x5b 0x08 0x46 # CHECK: c.nge.s $fcc3, $f11, $f8 +0x3b 0xfa 0x17 0x46 # CHECK: c.ngl.s $fcc2, $f31, $f23 +0x39 0x92 0x17 0x46 # CHECK: c.ngle.s $fcc2, $f18, $f23 +0x3f 0xc4 0x26 0x46 # CHECK: c.ngt.d $fcc4, $f24, $f6 +0x3f 0x45 0x0d 0x46 # CHECK: c.ngt.s $fcc5, $f8, $f13 +0x36 0x82 0x3e 0x46 # CHECK: c.ole.d $fcc2, $f16, $f30 +0x36 0x3b 0x14 0x46 # CHECK: c.ole.s $fcc3, $f7, $f20 +0x34 0x94 0x3c 0x46 # CHECK: c.olt.d $fcc4, $f18, $f28 +0x34 0xa6 0x07 0x46 # CHECK: c.olt.s $fcc6, $f20, $f7 +0x3a 0xf4 0x28 0x46 # CHECK: c.seq.d $fcc4, $f30, $f8 +0x3a 0x0f 0x19 0x46 # CHECK: c.seq.s $fcc7, $f1, $f25 +0x33 0x64 0x38 0x46 # CHECK: c.ueq.d $fcc4, $f12, $f24 +0x33 0x1e 0x1e 0x46 # CHECK: c.ueq.s $fcc6, $f3, $f30 +0x37 0xc7 0x32 0x46 # CHECK: c.ule.d $fcc7, $f24, $f18 +0x37 0xaf 0x1e 0x46 # CHECK: c.ule.s $fcc7, $f21, $f30 +0x35 0x36 0x30 0x46 # CHECK: c.ult.d $fcc6, $f6, $f16 +0x35 0xc7 0x0a 0x46 # CHECK: c.ult.s $fcc7, $f24, $f10 +0x31 0xb6 0x38 0x46 # CHECK: c.un.d $fcc6, $f22, $f24 +0x31 0xf1 0x04 0x46 # CHECK: c.un.s $fcc1, $f30, $f4 0x33 0x60 0x2e 0x46 # CHECK: c.ueq.d $f12, $f14 0x33 0xe0 0x12 0x46 # CHECK: c.ueq.s $f28, $f18 0x37 0x60 0x2e 0x46 # CHECK: c.ule.d $f12, $f14 Index: test/MC/Disassembler/Mips/mips32/valid-mips32.txt =================================================================== --- test/MC/Disassembler/Mips/mips32/valid-mips32.txt +++ test/MC/Disassembler/Mips/mips32/valid-mips32.txt @@ -52,6 +52,34 @@ 0x46 0x07 0x30 0x35 # CHECK: c.ult.s $f6, $f7 0x46 0x2e 0x60 0x31 # CHECK: c.un.d $f12, $f14 0x46 0x07 0x30 0x31 # CHECK: c.un.s $f6, $f7 +0x46 0x2e 0x71 0x32 # CHECK: c.eq.d $fcc1, $f14, $f14 +0x46 0x11 0xc5 0x32 # CHECK: c.eq.s $fcc5, $f24, $f17 +0x46 0x34 0x54 0x30 # CHECK: c.f.d $fcc4, $f10, $f20 +0x46 0x07 0xf4 0x30 # CHECK: c.f.s $fcc4, $f30, $f7 +0x46 0x22 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f2 +0x46 0x04 0xc6 0x3e # CHECK: c.le.s $fcc6, $f24, $f4 +0x46 0x22 0x43 0x3c # CHECK: c.lt.d $fcc3, $f8, $f2 +0x46 0x0e 0x8a 0x3c # CHECK: c.lt.s $fcc2, $f17, $f14 +0x46 0x30 0xa5 0x3d # CHECK: c.nge.d $fcc5, $f20, $f16 +0x46 0x08 0x5b 0x3d # CHECK: c.nge.s $fcc3, $f11, $f8 +0x46 0x17 0xfa 0x3b # CHECK: c.ngl.s $fcc2, $f31, $f23 +0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23 +0x46 0x26 0xc4 0x3f # CHECK: c.ngt.d $fcc4, $f24, $f6 +0x46 0x0d 0x45 0x3f # CHECK: c.ngt.s $fcc5, $f8, $f13 +0x46 0x3e 0x82 0x36 # CHECK: c.ole.d $fcc2, $f16, $f30 +0x46 0x14 0x3b 0x36 # CHECK: c.ole.s $fcc3, $f7, $f20 +0x46 0x3c 0x94 0x34 # CHECK: c.olt.d $fcc4, $f18, $f28 +0x46 0x07 0xa6 0x34 # CHECK: c.olt.s $fcc6, $f20, $f7 +0x46 0x28 0xf4 0x3a # CHECK: c.seq.d $fcc4, $f30, $f8 +0x46 0x19 0x0f 0x3a # CHECK: c.seq.s $fcc7, $f1, $f25 +0x46 0x38 0x64 0x33 # CHECK: c.ueq.d $fcc4, $f12, $f24 +0x46 0x1e 0x1e 0x33 # CHECK: c.ueq.s $fcc6, $f3, $f30 +0x46 0x32 0xc7 0x37 # CHECK: c.ule.d $fcc7, $f24, $f18 +0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30 +0x46 0x30 0x36 0x35 # CHECK: c.ult.d $fcc6, $f6, $f16 +0x46 0x0a 0xc7 0x35 # CHECK: c.ult.s $fcc7, $f24, $f10 +0x46 0x38 0xb6 0x31 # CHECK: c.un.d $fcc6, $f22, $f24 +0x46 0x04 0xf1 0x31 # CHECK: c.un.s $fcc1, $f30, $f4 0x46 0x20 0x73 0x0e # CHECK: ceil.w.d $f12, $f14 0x46 0x00 0x39 0x8e # CHECK: ceil.w.s $f6, $f7 0x44 0x46 0x38 0x00 # CHECK: cfc1 $6, $7 Index: test/MC/Disassembler/Mips/mips32/valid-xfail-mips32.txt =================================================================== --- test/MC/Disassembler/Mips/mips32/valid-xfail-mips32.txt +++ /dev/null @@ -1,30 +0,0 @@ -# RUN: llvm-mc %s -triple=mips-unknown-linux -disassemble | FileCheck %s -# XFAIL: * -0x46 0x2f 0x79 0x32 # CHECK: c.eq.d $fcc1, $f15, $f15 -0x46 0x11 0xc5 0x32 # CHECK: c.eq.s $fcc5, $f24, $f17 -0x46 0x35 0x5c 0x30 # CHECK: c.f.d $fcc4, $f11, $f21 -0x46 0x07 0xf4 0x30 # CHECK: c.f.s $fcc4, $f30, $f7 -0x46 0x21 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f1 -0x46 0x04 0xc6 0x3e # CHECK: c.le.s $fcc6, $f24, $f4 -0x46 0x23 0x4b 0x3c # CHECK: c.lt.d $fcc3, $f9, $f3 -0x46 0x0e 0x8a 0x3c # CHECK: c.lt.s $fcc2, $f17, $f14 -0x46 0x30 0xad 0x3d # CHECK: c.nge.d $fcc5, $f21, $f16 -0x46 0x08 0x5b 0x3d # CHECK: c.nge.s $fcc3, $f11, $f8 -0x46 0x17 0xfa 0x3b # CHECK: c.ngl.s $fcc2, $f31, $f23 -0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23 -0x46 0x27 0xc4 0x3f # CHECK: c.ngt.d $fcc4, $f24, $f7 -0x46 0x0d 0x45 0x3f # CHECK: c.ngt.s $fcc5, $f8, $f13 -0x46 0x3f 0x82 0x36 # CHECK: c.ole.d $fcc2, $f16, $f31 -0x46 0x14 0x3b 0x36 # CHECK: c.ole.s $fcc3, $f7, $f20 -0x46 0x3c 0x9c 0x34 # CHECK: c.olt.d $fcc4, $f19, $f28 -0x46 0x07 0xa6 0x34 # CHECK: c.olt.s $fcc6, $f20, $f7 -0x46 0x27 0xfc 0x3a # CHECK: c.seq.d $fcc4, $f31, $f7 -0x46 0x19 0x0f 0x3a # CHECK: c.seq.s $fcc7, $f1, $f25 -0x46 0x39 0x6c 0x33 # CHECK: c.ueq.d $fcc4, $f13, $f25 -0x46 0x1e 0x1e 0x33 # CHECK: c.ueq.s $fcc6, $f3, $f30 -0x46 0x32 0xcf 0x37 # CHECK: c.ule.d $fcc7, $f25, $f18 -0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30 -0x46 0x31 0x36 0x35 # CHECK: c.ult.d $fcc6, $f6, $f17 -0x46 0x0a 0xc7 0x35 # CHECK: c.ult.s $fcc7, $f24, $f10 -0x46 0x38 0xbe 0x31 # CHECK: c.un.d $fcc6, $f23, $f24 -0x46 0x04 0xf1 0x31 # CHECK: c.un.s $fcc1, $f30, $f4 Index: test/MC/Disassembler/Mips/mips32r2/valid-mips32r2-le.txt =================================================================== --- test/MC/Disassembler/Mips/mips32r2/valid-mips32r2-le.txt +++ test/MC/Disassembler/Mips/mips32r2/valid-mips32r2-le.txt @@ -52,6 +52,34 @@ 0x35 0x30 0x07 0x46 # CHECK: c.ult.s $f6, $f7 0x31 0x60 0x2e 0x46 # CHECK: c.un.d $f12, $f14 0x31 0x30 0x07 0x46 # CHECK: c.un.s $f6, $f7 +0x32 0x71 0x2e 0x46 # CHECK: c.eq.d $fcc1, $f14, $f14 +0x32 0xc5 0x11 0x46 # CHECK: c.eq.s $fcc5, $f24, $f17 +0x30 0x54 0x34 0x46 # CHECK: c.f.d $fcc4, $f10, $f20 +0x30 0xf4 0x07 0x46 # CHECK: c.f.s $fcc4, $f30, $f7 +0x3e 0x94 0x22 0x46 # CHECK: c.le.d $fcc4, $f18, $f2 +0x3e 0xc6 0x04 0x46 # CHECK: c.le.s $fcc6, $f24, $f4 +0x3c 0x43 0x22 0x46 # CHECK: c.lt.d $fcc3, $f8, $f2 +0x3c 0x8a 0x0e 0x46 # CHECK: c.lt.s $fcc2, $f17, $f14 +0x3d 0xa5 0x30 0x46 # CHECK: c.nge.d $fcc5, $f20, $f16 +0x3d 0x5b 0x08 0x46 # CHECK: c.nge.s $fcc3, $f11, $f8 +0x3b 0xfa 0x17 0x46 # CHECK: c.ngl.s $fcc2, $f31, $f23 +0x39 0x92 0x17 0x46 # CHECK: c.ngle.s $fcc2, $f18, $f23 +0x3f 0xc4 0x26 0x46 # CHECK: c.ngt.d $fcc4, $f24, $f6 +0x3f 0x45 0x0d 0x46 # CHECK: c.ngt.s $fcc5, $f8, $f13 +0x36 0x82 0x3e 0x46 # CHECK: c.ole.d $fcc2, $f16, $f30 +0x36 0x3b 0x14 0x46 # CHECK: c.ole.s $fcc3, $f7, $f20 +0x34 0x94 0x3c 0x46 # CHECK: c.olt.d $fcc4, $f18, $f28 +0x34 0xa6 0x07 0x46 # CHECK: c.olt.s $fcc6, $f20, $f7 +0x3a 0xf4 0x28 0x46 # CHECK: c.seq.d $fcc4, $f30, $f8 +0x3a 0x0f 0x19 0x46 # CHECK: c.seq.s $fcc7, $f1, $f25 +0x33 0x64 0x38 0x46 # CHECK: c.ueq.d $fcc4, $f12, $f24 +0x33 0x1e 0x1e 0x46 # CHECK: c.ueq.s $fcc6, $f3, $f30 +0x37 0xc7 0x32 0x46 # CHECK: c.ule.d $fcc7, $f24, $f18 +0x37 0xaf 0x1e 0x46 # CHECK: c.ule.s $fcc7, $f21, $f30 +0x35 0x36 0x30 0x46 # CHECK: c.ult.d $fcc6, $f6, $f16 +0x35 0xc7 0x0a 0x46 # CHECK: c.ult.s $fcc7, $f24, $f10 +0x31 0xb6 0x38 0x46 # CHECK: c.un.d $fcc6, $f22, $f24 +0x31 0xf1 0x04 0x46 # CHECK: c.un.s $fcc1, $f30, $f4 0x0e 0x73 0x20 0x46 # CHECK: ceil.w.d $f12, $f14 0x8e 0x39 0x00 0x46 # CHECK: ceil.w.s $f6, $f7 0x00 0x38 0x46 0x44 # CHECK: cfc1 $6, $7 Index: test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt =================================================================== --- test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt +++ test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt @@ -52,6 +52,34 @@ 0x46 0x07 0x30 0x35 # CHECK: c.ult.s $f6, $f7 0x46 0x2e 0x60 0x31 # CHECK: c.un.d $f12, $f14 0x46 0x07 0x30 0x31 # CHECK: c.un.s $f6, $f7 +0x46 0x2e 0x71 0x32 # CHECK: c.eq.d $fcc1, $f14, $f14 +0x46 0x11 0xc5 0x32 # CHECK: c.eq.s $fcc5, $f24, $f17 +0x46 0x34 0x54 0x30 # CHECK: c.f.d $fcc4, $f10, $f20 +0x46 0x07 0xf4 0x30 # CHECK: c.f.s $fcc4, $f30, $f7 +0x46 0x22 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f2 +0x46 0x04 0xc6 0x3e # CHECK: c.le.s $fcc6, $f24, $f4 +0x46 0x22 0x43 0x3c # CHECK: c.lt.d $fcc3, $f8, $f2 +0x46 0x0e 0x8a 0x3c # CHECK: c.lt.s $fcc2, $f17, $f14 +0x46 0x30 0xa5 0x3d # CHECK: c.nge.d $fcc5, $f20, $f16 +0x46 0x08 0x5b 0x3d # CHECK: c.nge.s $fcc3, $f11, $f8 +0x46 0x17 0xfa 0x3b # CHECK: c.ngl.s $fcc2, $f31, $f23 +0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23 +0x46 0x26 0xc4 0x3f # CHECK: c.ngt.d $fcc4, $f24, $f6 +0x46 0x0d 0x45 0x3f # CHECK: c.ngt.s $fcc5, $f8, $f13 +0x46 0x3e 0x82 0x36 # CHECK: c.ole.d $fcc2, $f16, $f30 +0x46 0x14 0x3b 0x36 # CHECK: c.ole.s $fcc3, $f7, $f20 +0x46 0x3c 0x94 0x34 # CHECK: c.olt.d $fcc4, $f18, $f28 +0x46 0x07 0xa6 0x34 # CHECK: c.olt.s $fcc6, $f20, $f7 +0x46 0x28 0xf4 0x3a # CHECK: c.seq.d $fcc4, $f30, $f8 +0x46 0x19 0x0f 0x3a # CHECK: c.seq.s $fcc7, $f1, $f25 +0x46 0x38 0x64 0x33 # CHECK: c.ueq.d $fcc4, $f12, $f24 +0x46 0x1e 0x1e 0x33 # CHECK: c.ueq.s $fcc6, $f3, $f30 +0x46 0x32 0xc7 0x37 # CHECK: c.ule.d $fcc7, $f24, $f18 +0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30 +0x46 0x30 0x36 0x35 # CHECK: c.ult.d $fcc6, $f6, $f16 +0x46 0x0a 0xc7 0x35 # CHECK: c.ult.s $fcc7, $f24, $f10 +0x46 0x38 0xb6 0x31 # CHECK: c.un.d $fcc6, $f22, $f24 +0x46 0x04 0xf1 0x31 # CHECK: c.un.s $fcc1, $f30, $f4 0x46 0x20 0x73 0x0e # CHECK: ceil.w.d $f12, $f14 0x46 0x00 0x39 0x8e # CHECK: ceil.w.s $f6, $f7 0x44 0x46 0x38 0x00 # CHECK: cfc1 $6, $7 Index: test/MC/Disassembler/Mips/mips32r2/valid-xfail-mips32r2.txt =================================================================== --- test/MC/Disassembler/Mips/mips32r2/valid-xfail-mips32r2.txt +++ test/MC/Disassembler/Mips/mips32r2/valid-xfail-mips32r2.txt @@ -1,33 +1,5 @@ # RUN: llvm-mc %s -triple=mips-unknown-linux -disassemble -mcpu=mips32r2 | FileCheck %s # XFAIL: * -0x46 0x2f 0x79 0x32 # CHECK: c.eq.d $fcc1, $f15, $f15 -0x46 0x11 0xc5 0x32 # CHECK: c.eq.s $fcc5, $f24, $f17 -0x46 0x35 0x5c 0x30 # CHECK: c.f.d $fcc4, $f11, $f21 -0x46 0x07 0xf4 0x30 # CHECK: c.f.s $fcc4, $f30, $f7 -0x46 0x21 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f1 -0x46 0x04 0xc6 0x3e # CHECK: c.le.s $fcc6, $f24, $f4 -0x46 0x23 0x4b 0x3c # CHECK: c.lt.d $fcc3, $f9, $f3 -0x46 0x0e 0x8a 0x3c # CHECK: c.lt.s $fcc2, $f17, $f14 -0x46 0x30 0xad 0x3d # CHECK: c.nge.d $fcc5, $f21, $f16 -0x46 0x08 0x5b 0x3d # CHECK: c.nge.s $fcc3, $f11, $f8 -0x46 0x17 0xfa 0x3b # CHECK: c.ngl.s $fcc2, $f31, $f23 -0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23 -0x46 0x27 0xc4 0x3f # CHECK: c.ngt.d $fcc4, $f24, $f7 -0x46 0x0d 0x45 0x3f # CHECK: c.ngt.s $fcc5, $f8, $f13 -0x46 0x3f 0x82 0x36 # CHECK: c.ole.d $fcc2, $f16, $f31 -0x46 0x14 0x3b 0x36 # CHECK: c.ole.s $fcc3, $f7, $f20 -0x46 0x3c 0x9c 0x34 # CHECK: c.olt.d $fcc4, $f19, $f28 -0x46 0x07 0xa6 0x34 # CHECK: c.olt.s $fcc6, $f20, $f7 -0x46 0x27 0xfc 0x3a # CHECK: c.seq.d $fcc4, $f31, $f7 -0x46 0x19 0x0f 0x3a # CHECK: c.seq.s $fcc7, $f1, $f25 -0x46 0x39 0x6c 0x33 # CHECK: c.ueq.d $fcc4, $f13, $f25 -0x46 0x1e 0x1e 0x33 # CHECK: c.ueq.s $fcc6, $f3, $f30 -0x46 0x32 0xcf 0x37 # CHECK: c.ule.d $fcc7, $f25, $f18 -0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30 -0x46 0x31 0x36 0x35 # CHECK: c.ult.d $fcc6, $f6, $f17 -0x46 0x0a 0xc7 0x35 # CHECK: c.ult.s $fcc7, $f24, $f10 -0x46 0x38 0xbe 0x31 # CHECK: c.un.d $fcc6, $f23, $f24 -0x46 0x04 0xf1 0x31 # CHECK: c.un.s $fcc1, $f30, $f4 0x46 0xc0 0x45 0x85 # CHECK: abs.ps $f22, $f8 0x46 0xcc 0xc6 0x00 # CHECK: add.ps $f24, $f24, $f12 0x46 0xca 0x04 0x32 # CHECK: c.eq.ps $fcc4, $f0, $f10 Index: test/MC/Disassembler/Mips/mips4/valid-mips4-el.txt =================================================================== --- test/MC/Disassembler/Mips/mips4/valid-mips4-el.txt +++ test/MC/Disassembler/Mips/mips4/valid-mips4-el.txt @@ -38,6 +38,34 @@ 0x39 0x00 0x30 0x46 # CHECK: c.ngle.d $f0, $f16 0x38 0xf0 0x20 0x46 # CHECK: c.sf.d $f30, $f0 0x38 0x70 0x16 0x46 # CHECK: c.sf.s $f14, $f22 +0x32 0x71 0x2e 0x46 # CHECK: c.eq.d $fcc1, $f14, $f14 +0x32 0xc5 0x11 0x46 # CHECK: c.eq.s $fcc5, $f24, $f17 +0x30 0x54 0x34 0x46 # CHECK: c.f.d $fcc4, $f10, $f20 +0x30 0xf4 0x07 0x46 # CHECK: c.f.s $fcc4, $f30, $f7 +0x3e 0x94 0x22 0x46 # CHECK: c.le.d $fcc4, $f18, $f2 +0x3e 0xc6 0x04 0x46 # CHECK: c.le.s $fcc6, $f24, $f4 +0x3c 0x43 0x22 0x46 # CHECK: c.lt.d $fcc3, $f8, $f2 +0x3c 0x8a 0x0e 0x46 # CHECK: c.lt.s $fcc2, $f17, $f14 +0x3d 0xa5 0x30 0x46 # CHECK: c.nge.d $fcc5, $f20, $f16 +0x3d 0x5b 0x08 0x46 # CHECK: c.nge.s $fcc3, $f11, $f8 +0x3b 0xfa 0x17 0x46 # CHECK: c.ngl.s $fcc2, $f31, $f23 +0x39 0x92 0x17 0x46 # CHECK: c.ngle.s $fcc2, $f18, $f23 +0x3f 0xc4 0x26 0x46 # CHECK: c.ngt.d $fcc4, $f24, $f6 +0x3f 0x45 0x0d 0x46 # CHECK: c.ngt.s $fcc5, $f8, $f13 +0x36 0x82 0x3e 0x46 # CHECK: c.ole.d $fcc2, $f16, $f30 +0x36 0x3b 0x14 0x46 # CHECK: c.ole.s $fcc3, $f7, $f20 +0x34 0x94 0x3c 0x46 # CHECK: c.olt.d $fcc4, $f18, $f28 +0x34 0xa6 0x07 0x46 # CHECK: c.olt.s $fcc6, $f20, $f7 +0x3a 0xf4 0x28 0x46 # CHECK: c.seq.d $fcc4, $f30, $f8 +0x3a 0x0f 0x19 0x46 # CHECK: c.seq.s $fcc7, $f1, $f25 +0x33 0x64 0x38 0x46 # CHECK: c.ueq.d $fcc4, $f12, $f24 +0x33 0x1e 0x1e 0x46 # CHECK: c.ueq.s $fcc6, $f3, $f30 +0x37 0xc7 0x32 0x46 # CHECK: c.ule.d $fcc7, $f24, $f18 +0x37 0xaf 0x1e 0x46 # CHECK: c.ule.s $fcc7, $f21, $f30 +0x35 0x36 0x30 0x46 # CHECK: c.ult.d $fcc6, $f6, $f16 +0x35 0xc7 0x0a 0x46 # CHECK: c.ult.s $fcc7, $f24, $f10 +0x31 0xb6 0x38 0x46 # CHECK: c.un.d $fcc6, $f22, $f24 +0x31 0xf1 0x04 0x46 # CHECK: c.un.s $fcc1, $f30, $f4 0x4a 0x18 0x20 0x46 # CHECK: ceil.l.d $f1, $f3 0x8a 0x6c 0x00 0x46 # CHECK: ceil.l.s $f18, $f13 0xce 0xc2 0x20 0x46 # CHECK: ceil.w.d $f11, $f24 Index: test/MC/Disassembler/Mips/mips4/valid-mips4.txt =================================================================== --- test/MC/Disassembler/Mips/mips4/valid-mips4.txt +++ test/MC/Disassembler/Mips/mips4/valid-mips4.txt @@ -38,7 +38,34 @@ 0x46 0x30 0x00 0x39 # CHECK: c.ngle.d $f0, $f16 0x46 0x20 0xf0 0x38 # CHECK: c.sf.d $f30, $f0 0x46 0x16 0x70 0x38 # CHECK: c.sf.s $f14, $f22 -0x46 0x20 0x18 0x4a # CHECK: ceil.l.d $f1, $f3 +0x46 0x2f 0x79 0x32 # CHECK: c.eq.d $fcc1, $f15, $f15 +0x46 0x11 0xc5 0x32 # CHECK: c.eq.s $fcc5, $f24, $f17 +0x46 0x35 0x5c 0x30 # CHECK: c.f.d $fcc4, $f11, $f21 +0x46 0x07 0xf4 0x30 # CHECK: c.f.s $fcc4, $f30, $f7 +0x46 0x21 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f1 +0x46 0x04 0xc6 0x3e # CHECK: c.le.s $fcc6, $f24, $f4 +0x46 0x23 0x4b 0x3c # CHECK: c.lt.d $fcc3, $f9, $f3 +0x46 0x0e 0x8a 0x3c # CHECK: c.lt.s $fcc2, $f17, $f14 +0x46 0x30 0xad 0x3d # CHECK: c.nge.d $fcc5, $f21, $f16 +0x46 0x08 0x5b 0x3d # CHECK: c.nge.s $fcc3, $f11, $f8 +0x46 0x17 0xfa 0x3b # CHECK: c.ngl.s $fcc2, $f31, $f23 +0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23 +0x46 0x27 0xc4 0x3f # CHECK: c.ngt.d $fcc4, $f24, $f7 +0x46 0x0d 0x45 0x3f # CHECK: c.ngt.s $fcc5, $f8, $f13 +0x46 0x3f 0x82 0x36 # CHECK: c.ole.d $fcc2, $f16, $f31 +0x46 0x14 0x3b 0x36 # CHECK: c.ole.s $fcc3, $f7, $f20 +0x46 0x3c 0x9c 0x34 # CHECK: c.olt.d $fcc4, $f19, $f28 +0x46 0x07 0xa6 0x34 # CHECK: c.olt.s $fcc6, $f20, $f7 +0x46 0x27 0xfc 0x3a # CHECK: c.seq.d $fcc4, $f31, $f7 +0x46 0x19 0x0f 0x3a # CHECK: c.seq.s $fcc7, $f1, $f25 +0x46 0x39 0x6c 0x33 # CHECK: c.ueq.d $fcc4, $f13, $f25 +0x46 0x1e 0x1e 0x33 # CHECK: c.ueq.s $fcc6, $f3, $f30 +0x46 0x32 0xcf 0x37 # CHECK: c.ule.d $fcc7, $f25, $f18 +0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30 +0x46 0x31 0x36 0x35 # CHECK: c.ult.d $fcc6, $f6, $f17 +0x46 0x0a 0xc7 0x35 # CHECK: c.ult.s $fcc7, $f24, $f10 +0x46 0x38 0xbe 0x31 # CHECK: c.un.d $fcc6, $f23, $f24 +0x46 0x04 0xf1 0x31 # CHECK: c.un.s $fcc1, $f30, $f4 0x46 0x00 0x6c 0x8a # CHECK: ceil.l.s $f18, $f13 0x46 0x20 0xc2 0xce # CHECK: ceil.w.d $f11, $f24 0x46 0x00 0xa1 0x8e # CHECK: ceil.w.s $f6, $f20 Index: test/MC/Disassembler/Mips/mips4/valid-xfail-mips4.txt =================================================================== --- test/MC/Disassembler/Mips/mips4/valid-xfail-mips4.txt +++ test/MC/Disassembler/Mips/mips4/valid-xfail-mips4.txt @@ -1,33 +1,5 @@ # RUN: llvm-mc %s -triple=mips64-unknown-linux -disassemble -mcpu=mips4 | FileCheck %s # XFAIL: * -0x46 0x2f 0x79 0x32 # CHECK: c.eq.d $fcc1, $f15, $f15 -0x46 0x11 0xc5 0x32 # CHECK: c.eq.s $fcc5, $f24, $f17 -0x46 0x35 0x5c 0x30 # CHECK: c.f.d $fcc4, $f11, $f21 -0x46 0x07 0xf4 0x30 # CHECK: c.f.s $fcc4, $f30, $f7 -0x46 0x21 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f1 -0x46 0x04 0xc6 0x3e # CHECK: c.le.s $fcc6, $f24, $f4 -0x46 0x23 0x4b 0x3c # CHECK: c.lt.d $fcc3, $f9, $f3 -0x46 0x0e 0x8a 0x3c # CHECK: c.lt.s $fcc2, $f17, $f14 -0x46 0x30 0xad 0x3d # CHECK: c.nge.d $fcc5, $f21, $f16 -0x46 0x08 0x5b 0x3d # CHECK: c.nge.s $fcc3, $f11, $f8 -0x46 0x17 0xfa 0x3b # CHECK: c.ngl.s $fcc2, $f31, $f23 -0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23 -0x46 0x27 0xc4 0x3f # CHECK: c.ngt.d $fcc4, $f24, $f7 -0x46 0x0d 0x45 0x3f # CHECK: c.ngt.s $fcc5, $f8, $f13 -0x46 0x3f 0x82 0x36 # CHECK: c.ole.d $fcc2, $f16, $f31 -0x46 0x14 0x3b 0x36 # CHECK: c.ole.s $fcc3, $f7, $f20 -0x46 0x3c 0x9c 0x34 # CHECK: c.olt.d $fcc4, $f19, $f28 -0x46 0x07 0xa6 0x34 # CHECK: c.olt.s $fcc6, $f20, $f7 -0x46 0x27 0xfc 0x3a # CHECK: c.seq.d $fcc4, $f31, $f7 -0x46 0x19 0x0f 0x3a # CHECK: c.seq.s $fcc7, $f1, $f25 -0x46 0x39 0x6c 0x33 # CHECK: c.ueq.d $fcc4, $f13, $f25 -0x46 0x1e 0x1e 0x33 # CHECK: c.ueq.s $fcc6, $f3, $f30 -0x46 0x32 0xcf 0x37 # CHECK: c.ule.d $fcc7, $f25, $f18 -0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30 -0x46 0x31 0x36 0x35 # CHECK: c.ult.d $fcc6, $f6, $f17 -0x46 0x0a 0xc7 0x35 # CHECK: c.ult.s $fcc7, $f24, $f10 -0x46 0x38 0xbe 0x31 # CHECK: c.un.d $fcc6, $f23, $f24 -0x46 0x04 0xf1 0x31 # CHECK: c.un.s $fcc1, $f30, $f4 0x4e 0x74 0xd4 0xa1 # CHECK: madd.d $f18, $f19, $f26, $f20 0x4f 0xf9 0x98 0x60 # CHECK: madd.s $f1, $f31, $f19, $f25 0x4c 0x32 0xfa 0xa9 # CHECK: msub.d $f10, $f1, $f31, $f18 Index: test/MC/Disassembler/Mips/mips64/valid-mips64-el.txt =================================================================== --- test/MC/Disassembler/Mips/mips64/valid-mips64-el.txt +++ test/MC/Disassembler/Mips/mips64/valid-mips64-el.txt @@ -52,6 +52,34 @@ 0x35 0x30 0x07 0x46 # CHECK: c.ult.s $f6, $f7 0x31 0x60 0x2e 0x46 # CHECK: c.un.d $f12, $f14 0x31 0x30 0x07 0x46 # CHECK: c.un.s $f6, $f7 +0x32 0x71 0x2e 0x46 # CHECK: c.eq.d $fcc1, $f14, $f14 +0x32 0xc5 0x11 0x46 # CHECK: c.eq.s $fcc5, $f24, $f17 +0x30 0x54 0x34 0x46 # CHECK: c.f.d $fcc4, $f10, $f20 +0x30 0xf4 0x07 0x46 # CHECK: c.f.s $fcc4, $f30, $f7 +0x3e 0x94 0x22 0x46 # CHECK: c.le.d $fcc4, $f18, $f2 +0x3e 0xc6 0x04 0x46 # CHECK: c.le.s $fcc6, $f24, $f4 +0x3c 0x43 0x22 0x46 # CHECK: c.lt.d $fcc3, $f8, $f2 +0x3c 0x8a 0x0e 0x46 # CHECK: c.lt.s $fcc2, $f17, $f14 +0x3d 0xa5 0x30 0x46 # CHECK: c.nge.d $fcc5, $f20, $f16 +0x3d 0x5b 0x08 0x46 # CHECK: c.nge.s $fcc3, $f11, $f8 +0x3b 0xfa 0x17 0x46 # CHECK: c.ngl.s $fcc2, $f31, $f23 +0x39 0x92 0x17 0x46 # CHECK: c.ngle.s $fcc2, $f18, $f23 +0x3f 0xc4 0x26 0x46 # CHECK: c.ngt.d $fcc4, $f24, $f6 +0x3f 0x45 0x0d 0x46 # CHECK: c.ngt.s $fcc5, $f8, $f13 +0x36 0x82 0x3e 0x46 # CHECK: c.ole.d $fcc2, $f16, $f30 +0x36 0x3b 0x14 0x46 # CHECK: c.ole.s $fcc3, $f7, $f20 +0x34 0x94 0x3c 0x46 # CHECK: c.olt.d $fcc4, $f18, $f28 +0x34 0xa6 0x07 0x46 # CHECK: c.olt.s $fcc6, $f20, $f7 +0x3a 0xf4 0x28 0x46 # CHECK: c.seq.d $fcc4, $f30, $f8 +0x3a 0x0f 0x19 0x46 # CHECK: c.seq.s $fcc7, $f1, $f25 +0x33 0x64 0x38 0x46 # CHECK: c.ueq.d $fcc4, $f12, $f24 +0x33 0x1e 0x1e 0x46 # CHECK: c.ueq.s $fcc6, $f3, $f30 +0x37 0xc7 0x32 0x46 # CHECK: c.ule.d $fcc7, $f24, $f18 +0x37 0xaf 0x1e 0x46 # CHECK: c.ule.s $fcc7, $f21, $f30 +0x35 0x36 0x30 0x46 # CHECK: c.ult.d $fcc6, $f6, $f16 +0x35 0xc7 0x0a 0x46 # CHECK: c.ult.s $fcc7, $f24, $f10 +0x31 0xb6 0x38 0x46 # CHECK: c.un.d $fcc6, $f22, $f24 +0x31 0xf1 0x04 0x46 # CHECK: c.un.s $fcc1, $f30, $f4 0x0e 0x73 0x20 0x46 # CHECK: ceil.w.d $f12, $f14 0x8e 0x39 0x00 0x46 # CHECK: ceil.w.s $f6, $f7 0x4a 0x18 0x20 0x46 # CHECK: ceil.l.d $f1, $f3 Index: test/MC/Disassembler/Mips/mips64/valid-mips64-xfail.txt =================================================================== --- test/MC/Disassembler/Mips/mips64/valid-mips64-xfail.txt +++ test/MC/Disassembler/Mips/mips64/valid-mips64-xfail.txt @@ -1,33 +1,5 @@ # RUN: llvm-mc %s -triple=mips-unknown-linux -disassemble | FileCheck %s # XFAIL: * -0x46 0x2f 0x79 0x32 # CHECK: c.eq.d $fcc1, $f15, $f15 -0x46 0x11 0xc5 0x32 # CHECK: c.eq.s $fcc5, $f24, $f17 -0x46 0x35 0x5c 0x30 # CHECK: c.f.d $fcc4, $f11, $f21 -0x46 0x07 0xf4 0x30 # CHECK: c.f.s $fcc4, $f30, $f7 -0x46 0x21 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f1 -0x46 0x04 0xc6 0x3e # CHECK: c.le.s $fcc6, $f24, $f4 -0x46 0x23 0x4b 0x3c # CHECK: c.lt.d $fcc3, $f9, $f3 -0x46 0x0e 0x8a 0x3c # CHECK: c.lt.s $fcc2, $f17, $f14 -0x46 0x30 0xad 0x3d # CHECK: c.nge.d $fcc5, $f21, $f16 -0x46 0x08 0x5b 0x3d # CHECK: c.nge.s $fcc3, $f11, $f8 -0x46 0x17 0xfa 0x3b # CHECK: c.ngl.s $fcc2, $f31, $f23 -0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23 -0x46 0x27 0xc4 0x3f # CHECK: c.ngt.d $fcc4, $f24, $f7 -0x46 0x0d 0x45 0x3f # CHECK: c.ngt.s $fcc5, $f8, $f13 -0x46 0x3f 0x82 0x36 # CHECK: c.ole.d $fcc2, $f16, $f31 -0x46 0x14 0x3b 0x36 # CHECK: c.ole.s $fcc3, $f7, $f20 -0x46 0x3c 0x9c 0x34 # CHECK: c.olt.d $fcc4, $f19, $f28 -0x46 0x07 0xa6 0x34 # CHECK: c.olt.s $fcc6, $f20, $f7 -0x46 0x27 0xfc 0x3a # CHECK: c.seq.d $fcc4, $f31, $f7 -0x46 0x19 0x0f 0x3a # CHECK: c.seq.s $fcc7, $f1, $f25 -0x46 0x39 0x6c 0x33 # CHECK: c.ueq.d $fcc4, $f13, $f25 -0x46 0x1e 0x1e 0x33 # CHECK: c.ueq.s $fcc6, $f3, $f30 -0x46 0x32 0xcf 0x37 # CHECK: c.ule.d $fcc7, $f25, $f18 -0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30 -0x46 0x31 0x36 0x35 # CHECK: c.ult.d $fcc6, $f6, $f17 -0x46 0x0a 0xc7 0x35 # CHECK: c.ult.s $fcc7, $f24, $f10 -0x46 0x38 0xbe 0x31 # CHECK: c.un.d $fcc6, $f23, $f24 -0x46 0x04 0xf1 0x31 # CHECK: c.un.s $fcc1, $f30, $f4 0x46 0xc0 0x45 0x85 # CHECK: abs.ps $f22, $f8 0x46 0xcd 0xde 0x40 # CHECK: add.ps $f25, $f27, $f13 0x4d 0x9e 0x93 0x1e # CHECK: alnv.ps $f12, $f18, $f30, $8 Index: test/MC/Disassembler/Mips/mips64/valid-mips64.txt =================================================================== --- test/MC/Disassembler/Mips/mips64/valid-mips64.txt +++ test/MC/Disassembler/Mips/mips64/valid-mips64.txt @@ -44,6 +44,34 @@ 0x46 0x07 0x30 0x3a # CHECK: c.seq.s $f6, $f7 0x46 0x2e 0x60 0x38 # CHECK: c.sf.d $f12, $f14 0x46 0x07 0x30 0x38 # CHECK: c.sf.s $f6, $f7 +0x46 0x2f 0x79 0x32 # CHECK: c.eq.d $fcc1, $f15, $f15 +0x46 0x11 0xc5 0x32 # CHECK: c.eq.s $fcc5, $f24, $f17 +0x46 0x35 0x5c 0x30 # CHECK: c.f.d $fcc4, $f11, $f21 +0x46 0x07 0xf4 0x30 # CHECK: c.f.s $fcc4, $f30, $f7 +0x46 0x21 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f1 +0x46 0x04 0xc6 0x3e # CHECK: c.le.s $fcc6, $f24, $f4 +0x46 0x23 0x4b 0x3c # CHECK: c.lt.d $fcc3, $f9, $f3 +0x46 0x0e 0x8a 0x3c # CHECK: c.lt.s $fcc2, $f17, $f14 +0x46 0x30 0xad 0x3d # CHECK: c.nge.d $fcc5, $f21, $f16 +0x46 0x08 0x5b 0x3d # CHECK: c.nge.s $fcc3, $f11, $f8 +0x46 0x17 0xfa 0x3b # CHECK: c.ngl.s $fcc2, $f31, $f23 +0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23 +0x46 0x27 0xc4 0x3f # CHECK: c.ngt.d $fcc4, $f24, $f7 +0x46 0x0d 0x45 0x3f # CHECK: c.ngt.s $fcc5, $f8, $f13 +0x46 0x3f 0x82 0x36 # CHECK: c.ole.d $fcc2, $f16, $f31 +0x46 0x14 0x3b 0x36 # CHECK: c.ole.s $fcc3, $f7, $f20 +0x46 0x3c 0x9c 0x34 # CHECK: c.olt.d $fcc4, $f19, $f28 +0x46 0x07 0xa6 0x34 # CHECK: c.olt.s $fcc6, $f20, $f7 +0x46 0x27 0xfc 0x3a # CHECK: c.seq.d $fcc4, $f31, $f7 +0x46 0x19 0x0f 0x3a # CHECK: c.seq.s $fcc7, $f1, $f25 +0x46 0x39 0x6c 0x33 # CHECK: c.ueq.d $fcc4, $f13, $f25 +0x46 0x1e 0x1e 0x33 # CHECK: c.ueq.s $fcc6, $f3, $f30 +0x46 0x32 0xcf 0x37 # CHECK: c.ule.d $fcc7, $f25, $f18 +0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30 +0x46 0x31 0x36 0x35 # CHECK: c.ult.d $fcc6, $f6, $f17 +0x46 0x0a 0xc7 0x35 # CHECK: c.ult.s $fcc7, $f24, $f10 +0x46 0x38 0xbe 0x31 # CHECK: c.un.d $fcc6, $f23, $f24 +0x46 0x04 0xf1 0x31 # CHECK: c.un.s $fcc1, $f30, $f4 0x46 0x2e 0x60 0x33 # CHECK: c.ueq.d $f12, $f14 0x46 0x12 0xe0 0x33 # CHECK: c.ueq.s $f28, $f18 0x46 0x2e 0x60 0x37 # CHECK: c.ule.d $f12, $f14 Index: test/MC/Disassembler/Mips/mips64r2/valid-mips64r2-el.txt =================================================================== --- test/MC/Disassembler/Mips/mips64r2/valid-mips64r2-el.txt +++ test/MC/Disassembler/Mips/mips64r2/valid-mips64r2-el.txt @@ -53,6 +53,34 @@ 0x35 0x30 0x07 0x46 # CHECK: c.ult.s $f6, $f7 0x31 0x60 0x2e 0x46 # CHECK: c.un.d $f12, $f14 0x31 0x30 0x07 0x46 # CHECK: c.un.s $f6, $f7 +0x32 0x71 0x2e 0x46 # CHECK: c.eq.d $fcc1, $f14, $f14 +0x32 0xc5 0x11 0x46 # CHECK: c.eq.s $fcc5, $f24, $f17 +0x30 0x54 0x34 0x46 # CHECK: c.f.d $fcc4, $f10, $f20 +0x30 0xf4 0x07 0x46 # CHECK: c.f.s $fcc4, $f30, $f7 +0x3e 0x94 0x22 0x46 # CHECK: c.le.d $fcc4, $f18, $f2 +0x3e 0xc6 0x04 0x46 # CHECK: c.le.s $fcc6, $f24, $f4 +0x3c 0x43 0x22 0x46 # CHECK: c.lt.d $fcc3, $f8, $f2 +0x3c 0x8a 0x0e 0x46 # CHECK: c.lt.s $fcc2, $f17, $f14 +0x3d 0xa5 0x30 0x46 # CHECK: c.nge.d $fcc5, $f20, $f16 +0x3d 0x5b 0x08 0x46 # CHECK: c.nge.s $fcc3, $f11, $f8 +0x3b 0xfa 0x17 0x46 # CHECK: c.ngl.s $fcc2, $f31, $f23 +0x39 0x92 0x17 0x46 # CHECK: c.ngle.s $fcc2, $f18, $f23 +0x3f 0xc4 0x26 0x46 # CHECK: c.ngt.d $fcc4, $f24, $f6 +0x3f 0x45 0x0d 0x46 # CHECK: c.ngt.s $fcc5, $f8, $f13 +0x36 0x82 0x3e 0x46 # CHECK: c.ole.d $fcc2, $f16, $f30 +0x36 0x3b 0x14 0x46 # CHECK: c.ole.s $fcc3, $f7, $f20 +0x34 0x94 0x3c 0x46 # CHECK: c.olt.d $fcc4, $f18, $f28 +0x34 0xa6 0x07 0x46 # CHECK: c.olt.s $fcc6, $f20, $f7 +0x3a 0xf4 0x28 0x46 # CHECK: c.seq.d $fcc4, $f30, $f8 +0x3a 0x0f 0x19 0x46 # CHECK: c.seq.s $fcc7, $f1, $f25 +0x33 0x64 0x38 0x46 # CHECK: c.ueq.d $fcc4, $f12, $f24 +0x33 0x1e 0x1e 0x46 # CHECK: c.ueq.s $fcc6, $f3, $f30 +0x37 0xc7 0x32 0x46 # CHECK: c.ule.d $fcc7, $f24, $f18 +0x37 0xaf 0x1e 0x46 # CHECK: c.ule.s $fcc7, $f21, $f30 +0x35 0x36 0x30 0x46 # CHECK: c.ult.d $fcc6, $f6, $f16 +0x35 0xc7 0x0a 0x46 # CHECK: c.ult.s $fcc7, $f24, $f10 +0x31 0xb6 0x38 0x46 # CHECK: c.un.d $fcc6, $f22, $f24 +0x31 0xf1 0x04 0x46 # CHECK: c.un.s $fcc1, $f30, $f4 0x4a 0x18 0x20 0x46 # CHECK: ceil.l.d $f1, $f3 0x8a 0x6c 0x00 0x46 # CHECK: ceil.l.s $f18, $f13 0x0e 0x73 0x20 0x46 # CHECK: ceil.w.d $f12, $f14 Index: test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt =================================================================== --- test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt +++ test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt @@ -53,6 +53,34 @@ 0x46 0x07 0x30 0x35 # CHECK: c.ult.s $f6, $f7 0x46 0x2e 0x60 0x31 # CHECK: c.un.d $f12, $f14 0x46 0x07 0x30 0x31 # CHECK: c.un.s $f6, $f7 +0x46 0x2f 0x79 0x32 # CHECK: c.eq.d $fcc1, $f15, $f15 +0x46 0x11 0xc5 0x32 # CHECK: c.eq.s $fcc5, $f24, $f17 +0x46 0x35 0x5c 0x30 # CHECK: c.f.d $fcc4, $f11, $f21 +0x46 0x07 0xf4 0x30 # CHECK: c.f.s $fcc4, $f30, $f7 +0x46 0x21 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f1 +0x46 0x04 0xc6 0x3e # CHECK: c.le.s $fcc6, $f24, $f4 +0x46 0x23 0x4b 0x3c # CHECK: c.lt.d $fcc3, $f9, $f3 +0x46 0x0e 0x8a 0x3c # CHECK: c.lt.s $fcc2, $f17, $f14 +0x46 0x30 0xad 0x3d # CHECK: c.nge.d $fcc5, $f21, $f16 +0x46 0x08 0x5b 0x3d # CHECK: c.nge.s $fcc3, $f11, $f8 +0x46 0x17 0xfa 0x3b # CHECK: c.ngl.s $fcc2, $f31, $f23 +0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23 +0x46 0x27 0xc4 0x3f # CHECK: c.ngt.d $fcc4, $f24, $f7 +0x46 0x0d 0x45 0x3f # CHECK: c.ngt.s $fcc5, $f8, $f13 +0x46 0x3f 0x82 0x36 # CHECK: c.ole.d $fcc2, $f16, $f31 +0x46 0x14 0x3b 0x36 # CHECK: c.ole.s $fcc3, $f7, $f20 +0x46 0x3c 0x9c 0x34 # CHECK: c.olt.d $fcc4, $f19, $f28 +0x46 0x07 0xa6 0x34 # CHECK: c.olt.s $fcc6, $f20, $f7 +0x46 0x27 0xfc 0x3a # CHECK: c.seq.d $fcc4, $f31, $f7 +0x46 0x19 0x0f 0x3a # CHECK: c.seq.s $fcc7, $f1, $f25 +0x46 0x39 0x6c 0x33 # CHECK: c.ueq.d $fcc4, $f13, $f25 +0x46 0x1e 0x1e 0x33 # CHECK: c.ueq.s $fcc6, $f3, $f30 +0x46 0x32 0xcf 0x37 # CHECK: c.ule.d $fcc7, $f25, $f18 +0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30 +0x46 0x31 0x36 0x35 # CHECK: c.ult.d $fcc6, $f6, $f17 +0x46 0x0a 0xc7 0x35 # CHECK: c.ult.s $fcc7, $f24, $f10 +0x46 0x38 0xbe 0x31 # CHECK: c.un.d $fcc6, $f23, $f24 +0x46 0x04 0xf1 0x31 # CHECK: c.un.s $fcc1, $f30, $f4 0x46 0x20 0x18 0x4a # CHECK: ceil.l.d $f1, $f3 0x46 0x00 0x6c 0x8a # CHECK: ceil.l.s $f18, $f13 0x46 0x20 0x73 0x0e # CHECK: ceil.w.d $f12, $f14 Index: test/MC/Disassembler/Mips/mips64r2/valid-xfail-mips64r2.txt =================================================================== --- test/MC/Disassembler/Mips/mips64r2/valid-xfail-mips64r2.txt +++ test/MC/Disassembler/Mips/mips64r2/valid-xfail-mips64r2.txt @@ -1,33 +1,5 @@ # RUN: llvm-mc %s -triple=mips-unknown-linux -disassemble -mcpu=mips32r2 | FileCheck %s # XFAIL: * -0x46 0x2f 0x79 0x32 # CHECK: c.eq.d $fcc1, $f15, $f15 -0x46 0x11 0xc5 0x32 # CHECK: c.eq.s $fcc5, $f24, $f17 -0x46 0x35 0x5c 0x30 # CHECK: c.f.d $fcc4, $f11, $f21 -0x46 0x07 0xf4 0x30 # CHECK: c.f.s $fcc4, $f30, $f7 -0x46 0x21 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f1 -0x46 0x04 0xc6 0x3e # CHECK: c.le.s $fcc6, $f24, $f4 -0x46 0x23 0x4b 0x3c # CHECK: c.lt.d $fcc3, $f9, $f3 -0x46 0x0e 0x8a 0x3c # CHECK: c.lt.s $fcc2, $f17, $f14 -0x46 0x30 0xad 0x3d # CHECK: c.nge.d $fcc5, $f21, $f16 -0x46 0x08 0x5b 0x3d # CHECK: c.nge.s $fcc3, $f11, $f8 -0x46 0x17 0xfa 0x3b # CHECK: c.ngl.s $fcc2, $f31, $f23 -0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23 -0x46 0x27 0xc4 0x3f # CHECK: c.ngt.d $fcc4, $f24, $f7 -0x46 0x0d 0x45 0x3f # CHECK: c.ngt.s $fcc5, $f8, $f13 -0x46 0x3f 0x82 0x36 # CHECK: c.ole.d $fcc2, $f16, $f31 -0x46 0x14 0x3b 0x36 # CHECK: c.ole.s $fcc3, $f7, $f20 -0x46 0x3c 0x9c 0x34 # CHECK: c.olt.d $fcc4, $f19, $f28 -0x46 0x07 0xa6 0x34 # CHECK: c.olt.s $fcc6, $f20, $f7 -0x46 0x27 0xfc 0x3a # CHECK: c.seq.d $fcc4, $f31, $f7 -0x46 0x19 0x0f 0x3a # CHECK: c.seq.s $fcc7, $f1, $f25 -0x46 0x39 0x6c 0x33 # CHECK: c.ueq.d $fcc4, $f13, $f25 -0x46 0x1e 0x1e 0x33 # CHECK: c.ueq.s $fcc6, $f3, $f30 -0x46 0x32 0xcf 0x37 # CHECK: c.ule.d $fcc7, $f25, $f18 -0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30 -0x46 0x31 0x36 0x35 # CHECK: c.ult.d $fcc6, $f6, $f17 -0x46 0x0a 0xc7 0x35 # CHECK: c.ult.s $fcc7, $f24, $f10 -0x46 0x38 0xbe 0x31 # CHECK: c.un.d $fcc6, $f23, $f24 -0x46 0x04 0xf1 0x31 # CHECK: c.un.s $fcc1, $f30, $f4 0x46 0xc0 0x45 0x85 # CHECK: abs.ps $f22, $f8 0x46 0xcc 0xc6 0x00 # CHECK: add.ps $f24, $f24, $f12 0x46 0xca 0x04 0x32 # CHECK: c.eq.ps $fcc4, $f0, $f10 Index: test/MC/Mips/mips32/valid-xfail.s =================================================================== --- test/MC/Mips/mips32/valid-xfail.s +++ test/MC/Mips/mips32/valid-xfail.s @@ -7,32 +7,4 @@ # XFAIL: * .set noat - c.eq.d $fcc1,$f15,$f15 - c.eq.s $fcc5,$f24,$f17 - c.f.d $fcc4,$f11,$f21 - c.f.s $fcc4,$f30,$f7 - c.le.d $fcc4,$f18,$f1 - c.le.s $fcc6,$f24,$f4 - c.lt.d $fcc3,$f9,$f3 - c.lt.s $fcc2,$f17,$f14 - c.nge.d $fcc5,$f21,$f16 - c.nge.s $fcc3,$f11,$f8 - c.ngl.s $fcc2,$f31,$f23 - c.ngle.s $fcc2,$f18,$f23 - c.ngt.d $fcc4,$f24,$f7 - c.ngt.s $fcc5,$f8,$f13 - c.ole.d $fcc2,$f16,$f31 - c.ole.s $fcc3,$f7,$f20 - c.olt.d $fcc4,$f19,$f28 - c.olt.s $fcc6,$f20,$f7 - c.seq.d $fcc4,$f31,$f7 - c.seq.s $fcc7,$f1,$f25 - c.ueq.d $fcc4,$f13,$f25 - c.ueq.s $fcc6,$f3,$f30 - c.ule.d $fcc7,$f25,$f18 - c.ule.s $fcc7,$f21,$f30 - c.ult.d $fcc6,$f6,$f17 - c.ult.s $fcc7,$f24,$f10 - c.un.d $fcc6,$f23,$f24 - c.un.s $fcc1,$f30,$f4 rorv $13,$a3,$s5 Index: test/MC/Mips/mips32/valid.s =================================================================== --- test/MC/Mips/mips32/valid.s +++ test/MC/Mips/mips32/valid.s @@ -45,6 +45,34 @@ c.ngle.d $f0,$f16 c.sf.d $f30,$f0 c.sf.s $f14,$f22 + c.eq.d $fcc1,$f15,$f15 + c.eq.s $fcc5,$f24,$f17 + c.f.d $fcc4,$f11,$f21 + c.f.s $fcc4,$f30,$f7 + c.le.d $fcc4,$f18,$f1 + c.le.s $fcc6,$f24,$f4 + c.lt.d $fcc3,$f9,$f3 + c.lt.s $fcc2,$f17,$f14 + c.nge.d $fcc5,$f21,$f16 + c.nge.s $fcc3,$f11,$f8 + c.ngl.s $fcc2,$f31,$f23 + c.ngle.s $fcc2,$f18,$f23 + c.ngt.d $fcc4,$f24,$f7 + c.ngt.s $fcc5,$f8,$f13 + c.ole.d $fcc2,$f16,$f31 + c.ole.s $fcc3,$f7,$f20 + c.olt.d $fcc4,$f19,$f28 + c.olt.s $fcc6,$f20,$f7 + c.seq.d $fcc4,$f31,$f7 + c.seq.s $fcc7,$f1,$f25 + c.ueq.d $fcc4,$f13,$f25 + c.ueq.s $fcc6,$f3,$f30 + c.ule.d $fcc7,$f25,$f18 + c.ule.s $fcc7,$f21,$f30 + c.ult.d $fcc6,$f6,$f17 + c.ult.s $fcc7,$f24,$f10 + c.un.d $fcc6,$f23,$f24 + c.un.s $fcc1,$f30,$f4 ceil.w.d $f11,$f25 ceil.w.s $f6,$f20 cfc1 $s1,$21 Index: test/MC/Mips/mips32r2/valid-xfail.s =================================================================== --- test/MC/Mips/mips32r2/valid-xfail.s +++ test/MC/Mips/mips32r2/valid-xfail.s @@ -33,50 +33,22 @@ bmnz.v $w15,$w2,$w28 bmz.v $w13,$w11,$w21 bsel.v $w28,$w7,$w0 - c.eq.d $fcc1,$f15,$f15 - c.eq.ps $fcc5,$f0,$f9 - c.eq.s $fcc5,$f24,$f17 - c.f.d $fcc4,$f11,$f21 - c.f.ps $fcc6,$f11,$f11 - c.f.s $fcc4,$f30,$f7 - c.le.d $fcc4,$f18,$f1 - c.le.ps $fcc1,$f7,$f20 - c.le.s $fcc6,$f24,$f4 - c.lt.d $fcc3,$f9,$f3 - c.lt.ps $f19,$f5 - c.lt.s $fcc2,$f17,$f14 - c.nge.d $fcc5,$f21,$f16 - c.nge.ps $f1,$f26 - c.nge.s $fcc3,$f11,$f8 - c.ngl.ps $f21,$f30 - c.ngl.s $fcc2,$f31,$f23 - c.ngle.ps $fcc7,$f12,$f20 - c.ngle.s $fcc2,$f18,$f23 - c.ngt.d $fcc4,$f24,$f7 - c.ngt.ps $fcc5,$f30,$f6 - c.ngt.s $fcc5,$f8,$f13 - c.ole.d $fcc2,$f16,$f31 - c.ole.ps $fcc7,$f21,$f8 - c.ole.s $fcc3,$f7,$f20 - c.olt.d $fcc4,$f19,$f28 - c.olt.ps $fcc3,$f7,$f16 - c.olt.s $fcc6,$f20,$f7 - c.seq.d $fcc4,$f31,$f7 - c.seq.ps $fcc6,$f31,$f14 - c.seq.s $fcc7,$f1,$f25 - c.sf.ps $fcc6,$f4,$f6 - c.ueq.d $fcc4,$f13,$f25 - c.ueq.ps $fcc1,$f5,$f29 - c.ueq.s $fcc6,$f3,$f30 - c.ule.d $fcc7,$f25,$f18 - c.ule.ps $fcc6,$f17,$f3 - c.ule.s $fcc7,$f21,$f30 - c.ult.d $fcc6,$f6,$f17 - c.ult.ps $fcc7,$f14,$f0 - c.ult.s $fcc7,$f24,$f10 - c.un.d $fcc6,$f23,$f24 c.un.ps $fcc4,$f2,$f26 - c.un.s $fcc1,$f30,$f4 + c.ult.ps $fcc7,$f14,$f0 + c.ule.ps $fcc6,$f17,$f3 + c.ueq.ps $fcc1,$f5,$f29 + c.sf.ps $fcc6,$f4,$f6 + c.seq.ps $fcc6,$f31,$f14 + c.olt.ps $fcc3,$f7,$f16 + c.ole.ps $fcc7,$f21,$f8 + c.ngt.ps $fcc5,$f30,$f6 + c.ngle.ps $fcc7,$f12,$f20 + c.ngl.ps $f21,$f30 + c.nge.ps $f1,$f26 + c.lt.ps $f19,$f5 + c.le.ps $fcc1,$f7,$f20 + c.f.ps $fcc6,$f11,$f11 + c.eq.ps $fcc5,$f0,$f9 ceil.l.d $f1,$f3 ceil.l.s $f18,$f13 cfcmsa $s6,$19 Index: test/MC/Mips/mips32r2/valid.s =================================================================== --- test/MC/Mips/mips32r2/valid.s +++ test/MC/Mips/mips32r2/valid.s @@ -45,6 +45,34 @@ c.ngle.d $f0,$f16 c.sf.d $f30,$f0 c.sf.s $f14,$f22 + c.eq.d $fcc1,$f15,$f15 + c.eq.s $fcc5,$f24,$f17 + c.f.d $fcc4,$f11,$f21 + c.f.s $fcc4,$f30,$f7 + c.le.d $fcc4,$f18,$f1 + c.le.s $fcc6,$f24,$f4 + c.lt.d $fcc3,$f9,$f3 + c.lt.s $fcc2,$f17,$f14 + c.nge.d $fcc5,$f21,$f16 + c.nge.s $fcc3,$f11,$f8 + c.ngl.s $fcc2,$f31,$f23 + c.ngle.s $fcc2,$f18,$f23 + c.ngt.d $fcc4,$f24,$f7 + c.ngt.s $fcc5,$f8,$f13 + c.ole.d $fcc2,$f16,$f31 + c.ole.s $fcc3,$f7,$f20 + c.olt.d $fcc4,$f19,$f28 + c.olt.s $fcc6,$f20,$f7 + c.seq.d $fcc4,$f31,$f7 + c.seq.s $fcc7,$f1,$f25 + c.ueq.d $fcc4,$f13,$f25 + c.ueq.s $fcc6,$f3,$f30 + c.ule.d $fcc7,$f25,$f18 + c.ule.s $fcc7,$f21,$f30 + c.ult.d $fcc6,$f6,$f17 + c.ult.s $fcc7,$f24,$f10 + c.un.d $fcc6,$f23,$f24 + c.un.s $fcc1,$f30,$f4 ceil.w.d $f11,$f25 ceil.w.s $f6,$f20 cfc1 $s1,$21 Index: test/MC/Mips/mips4/valid-xfail.s =================================================================== --- test/MC/Mips/mips4/valid-xfail.s +++ test/MC/Mips/mips4/valid-xfail.s @@ -7,34 +7,6 @@ # XFAIL: * .set noat - c.eq.d $fcc1,$f15,$f15 - c.eq.s $fcc5,$f24,$f17 - c.f.d $fcc4,$f11,$f21 - c.f.s $fcc4,$f30,$f7 - c.le.d $fcc4,$f18,$f1 - c.le.s $fcc6,$f24,$f4 - c.lt.d $fcc3,$f9,$f3 - c.lt.s $fcc2,$f17,$f14 - c.nge.d $fcc5,$f21,$f16 - c.nge.s $fcc3,$f11,$f8 - c.ngl.s $fcc2,$f31,$f23 - c.ngle.s $fcc2,$f18,$f23 - c.ngt.d $fcc4,$f24,$f7 - c.ngt.s $fcc5,$f8,$f13 - c.ole.d $fcc2,$f16,$f31 - c.ole.s $fcc3,$f7,$f20 - c.olt.d $fcc4,$f19,$f28 - c.olt.s $fcc6,$f20,$f7 - c.seq.d $fcc4,$f31,$f7 - c.seq.s $fcc7,$f1,$f25 - c.ueq.d $fcc4,$f13,$f25 - c.ueq.s $fcc6,$f3,$f30 - c.ule.d $fcc7,$f25,$f18 - c.ule.s $fcc7,$f21,$f30 - c.ult.d $fcc6,$f6,$f17 - c.ult.s $fcc7,$f24,$f10 - c.un.d $fcc6,$f23,$f24 - c.un.s $fcc1,$f30,$f4 madd.d $f18,$f19,$f26,$f20 madd.s $f1,$f31,$f19,$f25 msub.d $f10,$f1,$f31,$f18 Index: test/MC/Mips/mips4/valid.s =================================================================== --- test/MC/Mips/mips4/valid.s +++ test/MC/Mips/mips4/valid.s @@ -45,6 +45,34 @@ c.ngle.d $f0,$f16 c.sf.d $f30,$f0 c.sf.s $f14,$f22 + c.eq.d $fcc1,$f15,$f15 + c.eq.s $fcc5,$f24,$f17 + c.f.d $fcc4,$f11,$f21 + c.f.s $fcc4,$f30,$f7 + c.le.d $fcc4,$f18,$f1 + c.le.s $fcc6,$f24,$f4 + c.lt.d $fcc3,$f9,$f3 + c.lt.s $fcc2,$f17,$f14 + c.nge.d $fcc5,$f21,$f16 + c.nge.s $fcc3,$f11,$f8 + c.ngl.s $fcc2,$f31,$f23 + c.ngle.s $fcc2,$f18,$f23 + c.ngt.d $fcc4,$f24,$f7 + c.ngt.s $fcc5,$f8,$f13 + c.ole.d $fcc2,$f16,$f31 + c.ole.s $fcc3,$f7,$f20 + c.olt.d $fcc4,$f19,$f28 + c.olt.s $fcc6,$f20,$f7 + c.seq.d $fcc4,$f31,$f7 + c.seq.s $fcc7,$f1,$f25 + c.ueq.d $fcc4,$f13,$f25 + c.ueq.s $fcc6,$f3,$f30 + c.ule.d $fcc7,$f25,$f18 + c.ule.s $fcc7,$f21,$f30 + c.ult.d $fcc6,$f6,$f17 + c.ult.s $fcc7,$f24,$f10 + c.un.d $fcc6,$f23,$f24 + c.un.s $fcc1,$f30,$f4 ceil.l.d $f1,$f3 ceil.l.s $f18,$f13 ceil.w.d $f11,$f25 Index: test/MC/Mips/mips5/valid-xfail.s =================================================================== --- test/MC/Mips/mips5/valid-xfail.s +++ test/MC/Mips/mips5/valid-xfail.s @@ -10,50 +10,22 @@ abs.ps $f22,$f8 add.ps $f25,$f27,$f13 alnv.ps $f12,$f18,$f30,$12 - c.eq.d $fcc1,$f15,$f15 c.eq.ps $fcc5,$f0,$f9 - c.eq.s $fcc5,$f24,$f17 - c.f.d $fcc4,$f11,$f21 c.f.ps $fcc6,$f11,$f11 - c.f.s $fcc4,$f30,$f7 - c.le.d $fcc4,$f18,$f1 c.le.ps $fcc1,$f7,$f20 - c.le.s $fcc6,$f24,$f4 - c.lt.d $fcc3,$f9,$f3 c.lt.ps $f19,$f5 - c.lt.s $fcc2,$f17,$f14 - c.nge.d $fcc5,$f21,$f16 c.nge.ps $f1,$f26 - c.nge.s $fcc3,$f11,$f8 c.ngl.ps $f21,$f30 - c.ngl.s $fcc2,$f31,$f23 c.ngle.ps $fcc7,$f12,$f20 - c.ngle.s $fcc2,$f18,$f23 - c.ngt.d $fcc4,$f24,$f7 c.ngt.ps $fcc5,$f30,$f6 - c.ngt.s $fcc5,$f8,$f13 - c.ole.d $fcc2,$f16,$f31 c.ole.ps $fcc7,$f21,$f8 - c.ole.s $fcc3,$f7,$f20 - c.olt.d $fcc4,$f19,$f28 c.olt.ps $fcc3,$f7,$f16 - c.olt.s $fcc6,$f20,$f7 - c.seq.d $fcc4,$f31,$f7 c.seq.ps $fcc6,$f31,$f14 - c.seq.s $fcc7,$f1,$f25 c.sf.ps $fcc6,$f4,$f6 - c.ueq.d $fcc4,$f13,$f25 c.ueq.ps $fcc1,$f5,$f29 - c.ueq.s $fcc6,$f3,$f30 - c.ule.d $fcc7,$f25,$f18 c.ule.ps $fcc6,$f17,$f3 - c.ule.s $fcc7,$f21,$f30 - c.ult.d $fcc6,$f6,$f17 c.ult.ps $fcc7,$f14,$f0 - c.ult.s $fcc7,$f24,$f10 - c.un.d $fcc6,$f23,$f24 c.un.ps $fcc4,$f2,$f26 - c.un.s $fcc1,$f30,$f4 cvt.ps.s $f3,$f18,$f19 cvt.s.pl $f30,$f1 cvt.s.pu $f14,$f25 Index: test/MC/Mips/mips5/valid.s =================================================================== --- test/MC/Mips/mips5/valid.s +++ test/MC/Mips/mips5/valid.s @@ -45,6 +45,34 @@ c.ngle.d $f0,$f16 c.sf.d $f30,$f0 c.sf.s $f14,$f22 + c.eq.d $fcc1,$f15,$f15 + c.eq.s $fcc5,$f24,$f17 + c.f.d $fcc4,$f11,$f21 + c.f.s $fcc4,$f30,$f7 + c.le.d $fcc4,$f18,$f1 + c.le.s $fcc6,$f24,$f4 + c.lt.d $fcc3,$f9,$f3 + c.lt.s $fcc2,$f17,$f14 + c.nge.d $fcc5,$f21,$f16 + c.nge.s $fcc3,$f11,$f8 + c.ngl.s $fcc2,$f31,$f23 + c.ngle.s $fcc2,$f18,$f23 + c.ngt.d $fcc4,$f24,$f7 + c.ngt.s $fcc5,$f8,$f13 + c.ole.d $fcc2,$f16,$f31 + c.ole.s $fcc3,$f7,$f20 + c.olt.d $fcc4,$f19,$f28 + c.olt.s $fcc6,$f20,$f7 + c.seq.d $fcc4,$f31,$f7 + c.seq.s $fcc7,$f1,$f25 + c.ueq.d $fcc4,$f13,$f25 + c.ueq.s $fcc6,$f3,$f30 + c.ule.d $fcc7,$f25,$f18 + c.ule.s $fcc7,$f21,$f30 + c.ult.d $fcc6,$f6,$f17 + c.ult.s $fcc7,$f24,$f10 + c.un.d $fcc6,$f23,$f24 + c.un.s $fcc1,$f30,$f4 ceil.l.d $f1,$f3 ceil.l.s $f18,$f13 ceil.w.d $f11,$f25 Index: test/MC/Mips/mips64/valid-xfail.s =================================================================== --- test/MC/Mips/mips64/valid-xfail.s +++ test/MC/Mips/mips64/valid-xfail.s @@ -13,50 +13,22 @@ alnv.ob $v31,$v23,$v30,$at alnv.ob $v8,$v17,$v30,$a1 alnv.ps $f12,$f18,$f30,$12 - c.eq.d $fcc1,$f15,$f15 c.eq.ps $fcc5,$f0,$f9 - c.eq.s $fcc5,$f24,$f17 - c.f.d $fcc4,$f11,$f21 c.f.ps $fcc6,$f11,$f11 - c.f.s $fcc4,$f30,$f7 - c.le.d $fcc4,$f18,$f1 c.le.ps $fcc1,$f7,$f20 - c.le.s $fcc6,$f24,$f4 - c.lt.d $fcc3,$f9,$f3 c.lt.ps $f19,$f5 - c.lt.s $fcc2,$f17,$f14 - c.nge.d $fcc5,$f21,$f16 c.nge.ps $f1,$f26 - c.nge.s $fcc3,$f11,$f8 c.ngl.ps $f21,$f30 - c.ngl.s $fcc2,$f31,$f23 c.ngle.ps $fcc7,$f12,$f20 - c.ngle.s $fcc2,$f18,$f23 - c.ngt.d $fcc4,$f24,$f7 c.ngt.ps $fcc5,$f30,$f6 - c.ngt.s $fcc5,$f8,$f13 - c.ole.d $fcc2,$f16,$f31 c.ole.ps $fcc7,$f21,$f8 - c.ole.s $fcc3,$f7,$f20 - c.olt.d $fcc4,$f19,$f28 c.olt.ps $fcc3,$f7,$f16 - c.olt.s $fcc6,$f20,$f7 - c.seq.d $fcc4,$f31,$f7 c.seq.ps $fcc6,$f31,$f14 - c.seq.s $fcc7,$f1,$f25 c.sf.ps $fcc6,$f4,$f6 - c.ueq.d $fcc4,$f13,$f25 c.ueq.ps $fcc1,$f5,$f29 - c.ueq.s $fcc6,$f3,$f30 - c.ule.d $fcc7,$f25,$f18 c.ule.ps $fcc6,$f17,$f3 - c.ule.s $fcc7,$f21,$f30 - c.ult.d $fcc6,$f6,$f17 c.ult.ps $fcc7,$f14,$f0 - c.ult.s $fcc7,$f24,$f10 - c.un.d $fcc6,$f23,$f24 c.un.ps $fcc4,$f2,$f26 - c.un.s $fcc1,$f30,$f4 cvt.ps.s $f3,$f18,$f19 cvt.s.pl $f30,$f1 cvt.s.pu $f14,$f25 Index: test/MC/Mips/mips64/valid.s =================================================================== --- test/MC/Mips/mips64/valid.s +++ test/MC/Mips/mips64/valid.s @@ -45,6 +45,34 @@ c.ngle.d $f0,$f16 c.sf.d $f30,$f0 c.sf.s $f14,$f22 + c.eq.d $fcc1,$f15,$f15 + c.eq.s $fcc5,$f24,$f17 + c.f.d $fcc4,$f11,$f21 + c.f.s $fcc4,$f30,$f7 + c.le.d $fcc4,$f18,$f1 + c.le.s $fcc6,$f24,$f4 + c.lt.d $fcc3,$f9,$f3 + c.lt.s $fcc2,$f17,$f14 + c.nge.d $fcc5,$f21,$f16 + c.nge.s $fcc3,$f11,$f8 + c.ngl.s $fcc2,$f31,$f23 + c.ngle.s $fcc2,$f18,$f23 + c.ngt.d $fcc4,$f24,$f7 + c.ngt.s $fcc5,$f8,$f13 + c.ole.d $fcc2,$f16,$f31 + c.ole.s $fcc3,$f7,$f20 + c.olt.d $fcc4,$f19,$f28 + c.olt.s $fcc6,$f20,$f7 + c.seq.d $fcc4,$f31,$f7 + c.seq.s $fcc7,$f1,$f25 + c.ueq.d $fcc4,$f13,$f25 + c.ueq.s $fcc6,$f3,$f30 + c.ule.d $fcc7,$f25,$f18 + c.ule.s $fcc7,$f21,$f30 + c.ult.d $fcc6,$f6,$f17 + c.ult.s $fcc7,$f24,$f10 + c.un.d $fcc6,$f23,$f24 + c.un.s $fcc1,$f30,$f4 ceil.l.d $f1,$f3 ceil.l.s $f18,$f13 ceil.w.d $f11,$f25 Index: test/MC/Mips/mips64r2/valid-xfail.s =================================================================== --- test/MC/Mips/mips64r2/valid-xfail.s +++ test/MC/Mips/mips64r2/valid-xfail.s @@ -36,50 +36,22 @@ bmnz.v $w15,$w2,$w28 bmz.v $w13,$w11,$w21 bsel.v $w28,$w7,$w0 - c.eq.d $fcc1,$f15,$f15 c.eq.ps $fcc5,$f0,$f9 - c.eq.s $fcc5,$f24,$f17 - c.f.d $fcc4,$f11,$f21 c.f.ps $fcc6,$f11,$f11 - c.f.s $fcc4,$f30,$f7 - c.le.d $fcc4,$f18,$f1 c.le.ps $fcc1,$f7,$f20 - c.le.s $fcc6,$f24,$f4 - c.lt.d $fcc3,$f9,$f3 c.lt.ps $f19,$f5 - c.lt.s $fcc2,$f17,$f14 - c.nge.d $fcc5,$f21,$f16 c.nge.ps $f1,$f26 - c.nge.s $fcc3,$f11,$f8 c.ngl.ps $f21,$f30 - c.ngl.s $fcc2,$f31,$f23 c.ngle.ps $fcc7,$f12,$f20 - c.ngle.s $fcc2,$f18,$f23 - c.ngt.d $fcc4,$f24,$f7 c.ngt.ps $fcc5,$f30,$f6 - c.ngt.s $fcc5,$f8,$f13 - c.ole.d $fcc2,$f16,$f31 c.ole.ps $fcc7,$f21,$f8 - c.ole.s $fcc3,$f7,$f20 - c.olt.d $fcc4,$f19,$f28 c.olt.ps $fcc3,$f7,$f16 - c.olt.s $fcc6,$f20,$f7 - c.seq.d $fcc4,$f31,$f7 c.seq.ps $fcc6,$f31,$f14 - c.seq.s $fcc7,$f1,$f25 c.sf.ps $fcc6,$f4,$f6 - c.ueq.d $fcc4,$f13,$f25 c.ueq.ps $fcc1,$f5,$f29 - c.ueq.s $fcc6,$f3,$f30 - c.ule.d $fcc7,$f25,$f18 c.ule.ps $fcc6,$f17,$f3 - c.ule.s $fcc7,$f21,$f30 - c.ult.d $fcc6,$f6,$f17 c.ult.ps $fcc7,$f14,$f0 - c.ult.s $fcc7,$f24,$f10 - c.un.d $fcc6,$f23,$f24 c.un.ps $fcc4,$f2,$f26 - c.un.s $fcc1,$f30,$f4 cvt.ps.s $f3,$f18,$f19 cmp.eq.ph $s7,$14 cmp.le.ph $8,$14 Index: test/MC/Mips/mips64r2/valid.s =================================================================== --- test/MC/Mips/mips64r2/valid.s +++ test/MC/Mips/mips64r2/valid.s @@ -45,6 +45,34 @@ c.ngle.d $f0,$f16 c.sf.d $f30,$f0 c.sf.s $f14,$f22 + c.eq.d $fcc1,$f15,$f15 + c.eq.s $fcc5,$f24,$f17 + c.f.d $fcc4,$f11,$f21 + c.f.s $fcc4,$f30,$f7 + c.le.d $fcc4,$f18,$f1 + c.le.s $fcc6,$f24,$f4 + c.lt.d $fcc3,$f9,$f3 + c.lt.s $fcc2,$f17,$f14 + c.nge.d $fcc5,$f21,$f16 + c.nge.s $fcc3,$f11,$f8 + c.ngl.s $fcc2,$f31,$f23 + c.ngle.s $fcc2,$f18,$f23 + c.ngt.d $fcc4,$f24,$f7 + c.ngt.s $fcc5,$f8,$f13 + c.ole.d $fcc2,$f16,$f31 + c.ole.s $fcc3,$f7,$f20 + c.olt.d $fcc4,$f19,$f28 + c.olt.s $fcc6,$f20,$f7 + c.seq.d $fcc4,$f31,$f7 + c.seq.s $fcc7,$f1,$f25 + c.ueq.d $fcc4,$f13,$f25 + c.ueq.s $fcc6,$f3,$f30 + c.ule.d $fcc7,$f25,$f18 + c.ule.s $fcc7,$f21,$f30 + c.ult.d $fcc6,$f6,$f17 + c.ult.s $fcc7,$f24,$f10 + c.un.d $fcc6,$f23,$f24 + c.un.s $fcc1,$f30,$f4 ceil.l.d $f1,$f3 ceil.l.s $f18,$f13 ceil.w.d $f11,$f25