Index: lib/Target/Mips/MicroMips32r6InstrFormats.td =================================================================== --- lib/Target/Mips/MicroMips32r6InstrFormats.td +++ lib/Target/Mips/MicroMips32r6InstrFormats.td @@ -17,13 +17,6 @@ string DecoderNamespace = "MicroMipsR6"; } -// Class used for microMIPS32r6 instructions. -class MicroMipsR6Inst16 : PredicateControl { - string DecoderNamespace = "MicroMipsR6"; - let InsnPredicates = [HasMips32r6]; - let EncodingPredicates = [InMicroMips]; -} - //===----------------------------------------------------------------------===// // // Disambiguators @@ -51,7 +44,7 @@ let Inst{9-0} = offset; } -class BEQZC_BNEZC_FM_MM16R6 op> : MicroMipsR6Inst16 { +class BEQZC_BNEZC_FM_MM16R6 op> { bits<3> rs; bits<7> offset; @@ -699,7 +692,7 @@ let Inst{5-0} = 0b111011; } -class POOL16A_ADDU16_FM_MMR6 : MicroMipsR6Inst16 { +class POOL16A_ADDU16_FM_MMR6 { bits<3> rs; bits<3> rt; bits<3> rd; @@ -713,7 +706,7 @@ let Inst{0} = 0; } -class POOL16C_AND16_FM_MMR6 : MicroMipsR6Inst16 { +class POOL16C_AND16_FM_MMR6 { bits<3> rt; bits<3> rs; @@ -725,7 +718,7 @@ let Inst{3-0} = 0b0001; } -class POOL16C_NOT16_FM_MMR6 : MicroMipsR6Inst16 { +class POOL16C_NOT16_FM_MMR6 { bits<3> rt; bits<3> rs; @@ -737,7 +730,7 @@ let Inst{3-0} = 0b0000; } -class POOL16C_MOVEP16_FM_MMR6 : MicroMipsR6Inst16 { +class POOL16C_MOVEP16_FM_MMR6 { bits<3> dst_regs; bits<3> rt; bits<3> rs; @@ -752,7 +745,7 @@ let Inst{1-0} = rs{1-0}; } -class POOL16C_OR16_XOR16_FM_MMR6 op> : MicroMipsR6Inst16 { +class POOL16C_OR16_XOR16_FM_MMR6 op> { bits<3> rt; bits<3> rs; @@ -787,7 +780,8 @@ let Inst{0} = 0b1; } -class POOL32A_WRPGPR_WSBH_FM_MMR6 funct> : MipsR6Inst { +class POOL32A_WRPGPR_WSBH_FM_MMR6 funct> + : MMR6Arch, MipsR6Inst { bits<5> rt; bits<5> rs; Index: lib/Target/Mips/MicroMips32r6InstrInfo.td =================================================================== --- lib/Target/Mips/MicroMips32r6InstrInfo.td +++ lib/Target/Mips/MicroMips32r6InstrInfo.td @@ -147,8 +147,8 @@ class SW16_MMR6_ENC : LOAD_STORE_FM_MM16<0x3a>; class SWM16_MMR6_ENC : POOL16C_LWM_SWM_FM_MM16R6<0xa>; class SWSP_MMR6_ENC : LOAD_STORE_SP_FM_MM16<0x32>; -class WRPGPR_MMR6_ENC : POOL32A_WRPGPR_WSBH_FM_MMR6<0x3c5>; -class WSBH_MMR6_ENC : POOL32A_WRPGPR_WSBH_FM_MMR6<0x1ec>; +class WRPGPR_MMR6_ENC : POOL32A_WRPGPR_WSBH_FM_MMR6<"wrpgpr", 0x3c5>; +class WSBH_MMR6_ENC : POOL32A_WRPGPR_WSBH_FM_MMR6<"wsbh", 0x1ec>; class LB_MMR6_ENC : LB32_FM_MMR6; class LBU_MMR6_ENC : LBU32_FM_MMR6; class PAUSE_MMR6_ENC : POOL32A_PAUSE_FM_MMR6<"pause", 0b00101>; @@ -205,11 +205,11 @@ class BNVC_MMR6_ENC : POP37_BNVC_FM_MMR6<"bnvc">; class ADDU16_MMR6_ENC : POOL16A_ADDU16_FM_MMR6; class AND16_MMR6_ENC : POOL16C_AND16_FM_MMR6; -class ANDI16_MMR6_ENC : ANDI_FM_MM16<0b001011>, MicroMipsR6Inst16; +class ANDI16_MMR6_ENC : ANDI_FM_MM16<0b001011>; class NOT16_MMR6_ENC : POOL16C_NOT16_FM_MMR6; class OR16_MMR6_ENC : POOL16C_OR16_XOR16_FM_MMR6<0b1001>; -class SLL16_MMR6_ENC : SHIFT_FM_MM16<0>, MicroMipsR6Inst16; -class SRL16_MMR6_ENC : SHIFT_FM_MM16<1>, MicroMipsR6Inst16; +class SLL16_MMR6_ENC : SHIFT_FM_MM16<0>; +class SRL16_MMR6_ENC : SHIFT_FM_MM16<1>; class BREAK16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b011011>; class LI16_MMR6_ENC : LI_FM_MM16; class MOVE16_MMR6_ENC : MOVE_FM_MM16<0b000011>; @@ -367,7 +367,7 @@ class BC16_MMR6_DESC : MicroMipsInst16<(outs), (ins brtarget10_mm:$offset), !strconcat("bc16", "\t$offset"), [], II_BC, FrmI>, - MMR6Arch<"bc16">, MicroMipsR6Inst16 { + MMR6Arch<"bc16"> { let isBranch = 1; let isTerminator = 1; let isBarrier = 1; @@ -377,7 +377,8 @@ } class BEQZC_BNEZC_MM16R6_DESC_BASE - : CBranchZeroMM, MMR6Arch { + : CBranchZeroMM, + MMR6Arch { let isBranch = 1; let isTerminator = 1; let hasDelaySlot = 0; @@ -454,7 +455,7 @@ class JALRC16_MMR6_DESC_BASE : MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [(MipsJmpLink RO:$rs)], II_JALR, FrmR>, - MMR6Arch, MicroMipsR6Inst16 { + MMR6Arch { let isCall = 1; let hasDelaySlot = 0; let Defs = [RA]; @@ -488,7 +489,7 @@ class JRC16_MMR6_DESC_BASE : MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], II_JR, FrmR>, - MMR6Arch, MicroMipsR6Inst16 { + MMR6Arch { let hasDelaySlot = 0; let isBranch = 1; let isIndirectBranch = 1; @@ -498,7 +499,7 @@ class JRCADDIUSP_MMR6_DESC : MicroMipsInst16<(outs), (ins uimm5_lsl2:$imm), "jrcaddiusp\t$imm", [], II_JRADDIUSP, FrmR>, - MMR6Arch<"jrcaddiusp">, MicroMipsR6Inst16 { + MMR6Arch<"jrcaddiusp"> { let hasDelaySlot = 0; let isTerminator = 1; let isBarrier = 1; @@ -636,7 +637,7 @@ InstrItinClass Itinerary = II_SW; } class WRPGPR_WSBH_MMR6_DESC_BASE : MMR6Arch { + InstrItinClass Itin> { dag InOperandList = (ins RO:$rs); dag OutOperandList = (outs RO:$rt); string AsmString = !strconcat(instr_asm, "\t$rt, $rs"); @@ -1096,17 +1097,14 @@ MMR6Arch<"sll16">; class SRL16_MMR6_DESC : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>, MMR6Arch<"srl16">; -class BREAK16_MMR6_DESC : BrkSdbbp16MM<"break16", II_BREAK>, MMR6Arch<"break16">, - MicroMipsR6Inst16; +class BREAK16_MMR6_DESC : BrkSdbbp16MM<"break16", II_BREAK>, MMR6Arch<"break16">; class LI16_MMR6_DESC : LoadImmMM16<"li16", li16_imm, GPRMM16Opnd>, - MMR6Arch<"li16">, MicroMipsR6Inst16, IsAsCheapAsAMove; -class MOVE16_MMR6_DESC : MoveMM16<"move16", GPR32Opnd>, MMR6Arch<"move16">, - MicroMipsR6Inst16; + MMR6Arch<"li16">, IsAsCheapAsAMove; +class MOVE16_MMR6_DESC : MoveMM16<"move16", GPR32Opnd>, MMR6Arch<"move16">; class MOVEP_MMR6_DESC : MovePMM16<"movep", GPRMM16OpndMoveP>, MMR6Arch<"movep">; -class SDBBP16_MMR6_DESC : BrkSdbbp16MM<"sdbbp16", II_SDBBP>, MMR6Arch<"sdbbp16">, - MicroMipsR6Inst16; +class SDBBP16_MMR6_DESC : BrkSdbbp16MM<"sdbbp16", II_SDBBP>, MMR6Arch<"sdbbp16">; class SUBU16_MMR6_DESC : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>, - MMR6Arch<"subu16">, MicroMipsR6Inst16 { + MMR6Arch<"subu16"> { int AddedComplexity = 1; } class XOR16_MMR6_DESC : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR>, @@ -1166,7 +1164,7 @@ : MicroMipsInst16<(outs reglist16:$rt), (ins mem_mm_4sp:$addr), !strconcat("lwm16", "\t$rt, $addr"), [], II_LWM, FrmI>, - MMR6Arch<"lwm16">, MicroMipsR6Inst16 { + MMR6Arch<"lwm16"> { let DecoderMethod = "DecodeMemMMReglistImm4Lsl2"; let mayLoad = 1; ComplexPattern Addr = addr; @@ -1176,7 +1174,7 @@ : MicroMipsInst16<(outs), (ins reglist16:$rt, mem_mm_4sp:$addr), !strconcat("swm16", "\t$rt, $addr"), [], II_SWM, FrmI>, - MMR6Arch<"swm16">, MicroMipsR6Inst16 { + MMR6Arch<"swm16"> { let DecoderMethod = "DecodeMemMMReglistImm4Lsl2"; let mayStore = 1; ComplexPattern Addr = addr; @@ -1187,7 +1185,7 @@ Operand MemOpnd> : MicroMipsInst16<(outs), (ins RTOpnd:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI>, - MMR6Arch, MicroMipsR6Inst16 { + MMR6Arch { let DecoderMethod = "DecodeMemMMImm4"; let mayStore = 1; } @@ -1201,7 +1199,7 @@ class SWSP_MMR6_DESC : MicroMipsInst16<(outs), (ins GPR32Opnd:$rt, mem_mm_sp_imm5_lsl2:$offset), !strconcat("sw", "\t$rt, $offset"), [], II_SW, FrmI>, - MMR6Arch<"sw">, MicroMipsR6Inst16 { + MMR6Arch<"sw"> { let DecoderMethod = "DecodeMemMMSPImm5Lsl2"; let mayStore = 1; } @@ -1370,6 +1368,7 @@ ISA_MICROMIPS32R6, ASE_GINV; def GINVT_MMR6 : R6MMR6Rel, GINVT_MMR6_ENC, GINVT_MMR6_DESC, ISA_MICROMIPS32R6, ASE_GINV; +let FastISelShouldIgnore = 1 in def JALRC16_MMR6 : R6MMR6Rel, JALRC16_MMR6_DESC, JALRC16_MMR6_ENC, ISA_MICROMIPS32R6; def JIALC_MMR6 : R6MMR6Rel, JIALC_MMR6_ENC, JIALC_MMR6_DESC, ISA_MICROMIPS32R6; Index: lib/Target/Mips/MicroMipsDSPInstrFormats.td =================================================================== --- lib/Target/Mips/MicroMipsDSPInstrFormats.td +++ lib/Target/Mips/MicroMipsDSPInstrFormats.td @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// class MMDSPInst - : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>, PredicateControl { + : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> { let ASEPredicate = [HasDSP]; let AdditionalPredicates = [InMicroMips]; string BaseOpcode = opstr; Index: lib/Target/Mips/MicroMipsInstrFormats.td =================================================================== --- lib/Target/Mips/MicroMipsInstrFormats.td +++ lib/Target/Mips/MicroMipsInstrFormats.td @@ -7,8 +7,8 @@ // This class does not depend on the instruction size. // class MicroMipsInstBase pattern, - InstrItinClass itin, Format f> : Instruction -{ + InstrItinClass itin, Format f> : Instruction, + PredicateControl { let Namespace = "Mips"; let DecoderNamespace = "MicroMips"; @@ -19,7 +19,7 @@ let Pattern = pattern; let Itinerary = itin; - let Predicates = [InMicroMips]; + let EncodingPredicates = [InMicroMips]; Format Form = f; } @@ -961,7 +961,7 @@ let Inst{11-0} = addr{11-0}; } -class LWM_FM_MM16 funct> : MMArch, PredicateControl { +class LWM_FM_MM16 funct> : MMArch { bits<2> rt; bits<4> addr; Index: lib/Target/Mips/MicroMipsInstrInfo.td =================================================================== --- lib/Target/Mips/MicroMipsInstrInfo.td +++ lib/Target/Mips/MicroMipsInstrInfo.td @@ -422,7 +422,7 @@ // 16-bit Jump and Link (Call) class JumpLinkRegMM16 : MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), - [(MipsJmpLink RO:$rs)], II_JALR, FrmR>, PredicateControl { + [(MipsJmpLink RO:$rs)], II_JALR, FrmR> { let isCall = 1; let hasDelaySlot = 1; let Defs = [RA]; @@ -612,28 +612,28 @@ let FastISelShouldIgnore = 1 in { def ADDU16_MM : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>, - ARITH_FM_MM16<0>, ISA_MICROMIPS_NOT_32R6; + ARITH_FM_MM16<0>, ISA_MICROMIPS32_NOT_MIPS32R6; def AND16_MM : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>, - LOGIC_FM_MM16<0x2>, ISA_MICROMIPS_NOT_32R6; + LOGIC_FM_MM16<0x2>, ISA_MICROMIPS32_NOT_MIPS32R6; } def ANDI16_MM : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>, ANDI_FM_MM16<0x0b>, - ISA_MICROMIPS_NOT_32R6; + ISA_MICROMIPS32_NOT_MIPS32R6; def NOT16_MM : NotMM16<"not16", GPRMM16Opnd>, LOGIC_FM_MM16<0x0>, - ISA_MICROMIPS_NOT_32R6; + ISA_MICROMIPS32_NOT_MIPS32R6; let FastISelShouldIgnore = 1 in def OR16_MM : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>, LOGIC_FM_MM16<0x3>, - ISA_MICROMIPS_NOT_32R6; + ISA_MICROMIPS32_NOT_MIPS32R6; def SLL16_MM : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>, - SHIFT_FM_MM16<0>, ISA_MICROMIPS_NOT_32R6; + SHIFT_FM_MM16<0>, ISA_MICROMIPS32_NOT_MIPS32R6; def SRL16_MM : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>, - SHIFT_FM_MM16<1>, ISA_MICROMIPS_NOT_32R6; + SHIFT_FM_MM16<1>, ISA_MICROMIPS32_NOT_MIPS32R6; let FastISelShouldIgnore = 1 in { def SUBU16_MM : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>, - ARITH_FM_MM16<1>, ISA_MICROMIPS_NOT_32R6; + ARITH_FM_MM16<1>, ISA_MICROMIPS32_NOT_MIPS32R6; def XOR16_MM : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>, - LOGIC_FM_MM16<0x1>, ISA_MICROMIPS_NOT_32R6; + LOGIC_FM_MM16<0x1>, ISA_MICROMIPS32_NOT_MIPS32R6; } def LBU16_MM : LoadMM16<"lbu16", GPRMM16Opnd, zextloadi8, II_LBU, mem_mm_4>, LOAD_STORE_FM_MM16<0x02>; @@ -659,12 +659,12 @@ def ADDIUS5_MM : AddImmUS5<"addius5", GPR32Opnd>, ADDIUS5_FM_MM16; def ADDIUSP_MM : AddImmUSP<"addiusp">, ADDIUSP_FM_MM16; def MFHI16_MM : MoveFromHILOMM<"mfhi16", GPR32Opnd, AC0>, - MFHILO_FM_MM16<0x10>; + MFHILO_FM_MM16<0x10>, ISA_MICROMIPS32_NOT_MIPS32R6; def MFLO16_MM : MoveFromHILOMM<"mflo16", GPR32Opnd, AC0>, - MFHILO_FM_MM16<0x12>; + MFHILO_FM_MM16<0x12>, ISA_MICROMIPS32_NOT_MIPS32R6; def MOVE16_MM : MoveMM16<"move", GPR32Opnd>, MOVE_FM_MM16<0x03>; def MOVEP_MM : MovePMM16<"movep", GPRMM16OpndMoveP>, MOVEP_FM_MM16, - ISA_MICROMIPS_NOT_32R6; + ISA_MICROMIPS32_NOT_MIPS32R6; def LI16_MM : LoadImmMM16<"li16", li16_imm, GPRMM16Opnd>, LI_FM_MM16, IsAsCheapAsAMove; def JALR16_MM : JumpLinkRegMM16<"jalr", GPR32Opnd>, JALR_FM_MM16<0x0e>, @@ -679,9 +679,9 @@ BEQNEZ_FM_MM16<0x2b>; def B16_MM : UncondBranchMM16<"b16">, B16_FM; def BREAK16_MM : BrkSdbbp16MM<"break16", II_BREAK>, BRKSDBBP16_FM_MM<0x28>, - ISA_MICROMIPS_NOT_32R6; + ISA_MICROMIPS32_NOT_MIPS32R6; def SDBBP16_MM : BrkSdbbp16MM<"sdbbp16", II_SDBBP>, BRKSDBBP16_FM_MM<0x2C>, - ISA_MICROMIPS_NOT_32R6; + ISA_MICROMIPS32_NOT_MIPS32R6; let DecoderNamespace = "MicroMips" in { /// Load and Store Instructions - multiple Index: lib/Target/Mips/Mips32r6InstrFormats.td =================================================================== --- lib/Target/Mips/Mips32r6InstrFormats.td +++ lib/Target/Mips/Mips32r6InstrFormats.td @@ -30,8 +30,7 @@ string BaseOpcode = opstr; } -class MipsR6Inst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>, - PredicateControl { +class MipsR6Inst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> { let DecoderNamespace = "Mips32r6_64r6"; let EncodingPredicates = [HasStdEnc]; } Index: lib/Target/Mips/MipsDSPInstrFormats.td =================================================================== --- lib/Target/Mips/MipsDSPInstrFormats.td +++ lib/Target/Mips/MipsDSPInstrFormats.td @@ -45,7 +45,7 @@ def REGIMM_OPCODE : Field6<0b000001>; class DSPInst - : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>, PredicateControl { + : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> { let ASEPredicate = [HasDSP]; string BaseOpcode = opstr; string Arch = "dsp"; Index: lib/Target/Mips/MipsEVAInstrFormats.td =================================================================== --- lib/Target/Mips/MipsEVAInstrFormats.td +++ lib/Target/Mips/MipsEVAInstrFormats.td @@ -12,7 +12,7 @@ //===----------------------------------------------------------------------===// class MipsEVAInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>, - PredicateControl, StdArch { + StdArch { let DecoderNamespace = "Mips"; let EncodingPredicates = [HasStdEnc]; } Index: lib/Target/Mips/MipsInstrFormats.td =================================================================== --- lib/Target/Mips/MipsInstrFormats.td +++ lib/Target/Mips/MipsInstrFormats.td @@ -70,7 +70,7 @@ // Generic Mips Format class MipsInst pattern, - InstrItinClass itin, Format f>: Instruction + InstrItinClass itin, Format f>: Instruction, PredicateControl { field bits<32> Inst; Format Form = f; @@ -119,7 +119,7 @@ // Mips32/64 Instruction Format class InstSE pattern, InstrItinClass itin, Format f, string opstr = ""> : - MipsInst, PredicateControl { + MipsInst { let EncodingPredicates = [HasStdEnc]; string BaseOpcode = opstr; string Arch; @@ -128,7 +128,7 @@ // Mips Pseudo Instructions Format class MipsPseudo pattern, InstrItinClass itin = IIPseudo> : - MipsInst, PredicateControl { + MipsInst { let isCodeGenOnly = 1; let isPseudo = 1; } @@ -144,7 +144,7 @@ // These are aliases that require C++ handling to convert to the target // instruction, while InstAliases can be handled directly by tblgen. class MipsAsmPseudoInst: - MipsInst, PredicateControl { + MipsInst { let isPseudo = 1; let Pattern = []; } Index: lib/Target/Mips/MipsMSAInstrFormats.td =================================================================== --- lib/Target/Mips/MipsMSAInstrFormats.td +++ lib/Target/Mips/MipsMSAInstrFormats.td @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// class MSAInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>, - PredicateControl, ASE_MSA { + ASE_MSA { let EncodingPredicates = [HasStdEnc]; let Inst{31-26} = 0b011110; } Index: lib/Target/Mips/MipsMTInstrFormats.td =================================================================== --- lib/Target/Mips/MipsMTInstrFormats.td +++ lib/Target/Mips/MipsMTInstrFormats.td @@ -15,8 +15,7 @@ // //===----------------------------------------------------------------------===// -class MipsMTInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>, - PredicateControl { +class MipsMTInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> { let DecoderNamespace = "Mips"; let EncodingPredicates = [HasStdEnc]; }