Index: lib/CodeGen/MachineInstr.cpp
===================================================================
--- lib/CodeGen/MachineInstr.cpp
+++ lib/CodeGen/MachineInstr.cpp
@@ -224,6 +224,22 @@
     }
   }
 
+  // Let implicit operands (added by e.g. regalloc) that are not part of MCID
+  // remain at the end of the list. This is important for targets with a
+  // SchedModel in the cases where an opcode is changed to a very similar
+  // instruction that also defines e.g. the CC register. To later look up the
+  // latency of this register correctly, this operand must be placed in
+  // accordance with the MCID order of operands.
+  auto isMCIDImplReg = [&] (unsigned Reg) {
+    return (MCID->hasImplicitDefOfPhysReg(Reg) ||
+            MCID->hasImplicitUseOfPhysReg(Reg));
+  };
+  if (isImpReg && isMCIDImplReg(Op.getReg())) {
+        while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()
+               && !isMCIDImplReg(Operands[OpNo-1].getReg()))
+          --OpNo;
+  }
+
 #ifndef NDEBUG
   bool isMetaDataOp = Op.getType() == MachineOperand::MO_Metadata;
   // OpNo now points as the desired insertion point.  Unless this is a variadic