Index: lib/Target/X86/X86InstrInfo.td =================================================================== --- lib/Target/X86/X86InstrInfo.td +++ lib/Target/X86/X86InstrInfo.td @@ -2429,6 +2429,7 @@ } let Predicates = [HasBMI2] in { + // x & ((1 << y) - 1) def : Pat<(and GR32:$src, (add (shl 1, GR8:$lz), -1)), (BZHI32rr GR32:$src, (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>; @@ -2445,12 +2446,36 @@ (BZHI64rm addr:$src, (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>; + // x & ~(-1 << y) + def : Pat<(and GR32:$src, (xor (shl -1, GR8:$lz), -1)), + (BZHI32rr GR32:$src, + (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>; + + def : Pat<(and (loadi32 addr:$src), (xor (shl -1, GR8:$lz), -1)), + (BZHI32rm addr:$src, + (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>; + + def : Pat<(and GR64:$src, (xor (shl -1, GR8:$lz), -1)), + (BZHI64rr GR64:$src, + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>; + + def : Pat<(and (loadi64 addr:$src), (xor (shl -1, GR8:$lz), -1)), + (BZHI64rm addr:$src, + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>; + // x & (-1 >> (32 - y)) def : Pat<(and GR32:$src, (srl -1, (i8 (trunc (sub 32, GR32:$lz))))), (BZHI32rr GR32:$src, GR32:$lz)>; def : Pat<(and (loadi32 addr:$src), (srl -1, (i8 (trunc (sub 32, GR32:$lz))))), (BZHI32rm addr:$src, GR32:$lz)>; + def : Pat<(and GR32:$src, (srl -1, (sub 32, GR8:$lz))), + (BZHI32rr GR32:$src, + (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>; + def : Pat<(and (loadi32 addr:$src), (srl -1, (sub 32, GR8:$lz))), + (BZHI32rm addr:$src, + (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>; + // x & (-1 >> (64 - y)) def : Pat<(and GR64:$src, (srl -1, (i8 (trunc (sub 64, GR32:$lz))))), (BZHI64rr GR64:$src, @@ -2459,6 +2484,13 @@ (BZHI64rm addr:$src, (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$lz, sub_32bit))>; + def : Pat<(and GR64:$src, (srl -1, (sub 64, GR8:$lz))), + (BZHI64rr GR64:$src, + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>; + def : Pat<(and (loadi64 addr:$src), (srl -1, (sub 64, GR8:$lz))), + (BZHI64rm addr:$src, + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>; + // x << (32 - y) >> (32 - y) def : Pat<(srl (shl GR32:$src, (i8 (trunc (sub 32, GR32:$lz)))), (i8 (trunc (sub 32, GR32:$lz)))), @@ -2467,6 +2499,13 @@ (i8 (trunc (sub 32, GR32:$lz)))), (BZHI32rm addr:$src, GR32:$lz)>; + def : Pat<(srl (shl GR32:$src, (sub 32, GR8:$lz)), (sub 32, GR8:$lz)), + (BZHI32rr GR32:$src, + (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>; + def : Pat<(srl (shl (loadi32 addr:$src), (sub 32, GR8:$lz)), (sub 32, GR8:$lz)), + (BZHI32rm addr:$src, + (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>; + // x << (64 - y) >> (64 - y) def : Pat<(srl (shl GR64:$src, (i8 (trunc (sub 64, GR32:$lz)))), (i8 (trunc (sub 64, GR32:$lz)))), @@ -2476,6 +2515,13 @@ (i8 (trunc (sub 64, GR32:$lz)))), (BZHI64rm addr:$src, (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$lz, sub_32bit))>; + + def : Pat<(srl (shl GR64:$src, (sub 64, GR8:$lz)), (sub 64, GR8:$lz)), + (BZHI64rr GR64:$src, + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>; + def : Pat<(srl (shl (loadi64 addr:$src), (sub 64, GR8:$lz)), (sub 64, GR8:$lz)), + (BZHI64rm addr:$src, + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>; } // HasBMI2 multiclass bmi_pdep_pext