Index: lib/Target/X86/X86ScheduleBtVer2.td =================================================================== --- lib/Target/X86/X86ScheduleBtVer2.td +++ lib/Target/X86/X86ScheduleBtVer2.td @@ -543,5 +543,48 @@ let NumMicroOps = 37; } def : InstRW<[JWriteJVZEROUPPER], (instrs VZEROUPPER)>; + } // SchedModel +//////////////////////////////////////////////////////////////////////////////// +// MCInstPredicate definitions used by variant scheduling classes. +// TODO: predicate definitions that are common to many X86 models should go +// to X86Schedule.td. +//////////////////////////////////////////////////////////////////////////////// + +def JZeroIdiomPredicate : CheckAll<[ + CheckSameRegOperand<0, 1>, + CheckSameRegOperand<0, 2> +]>; + +def JPackedIntXOR : CheckOpcode<[PXORrr, VPXORrr]>; + +/////////////////////////////////////////////////////////////////////////////// +// SchedWriteVariant definitions. +/////////////////////////////////////////////////////////////////////////////// + +let SchedModel = BtVer2Model in { + +def JWriteZeroLatency : SchedWriteRes<[]> { + let Latency = 0; +} + +// Vector XOR instructions that use the same register for both source and +// destination do not have a real dependency on the previous contents of the +// register, and thus, do not have to wait before completing. They can be +// optimized out at register renaming stage. +// Reference: Section 10.8 of the "Software Optimization Guide for AMD Family +// 15h Processors". +// Reference: Agner's Fog "The microarchitecture of Intel, AMD and VIA CPUs", +// Section 21.8 [Dependency-breaking instructions]. + +def JWriteZeroIdiom : SchedWriteVariant<[ + SchedVar, [JWriteZeroLatency]>, + SchedVar, [WriteVecLogicX]>, + SchedVar, [WriteFLogic]> +]>; + +def : InstRW<[JWriteZeroIdiom], (instrs XORPSrr, VXORPSrr, PXORrr, + XORPDrr, VXORPDrr, VPXORrr)>; + +} // SchedModel Index: test/CodeGen/X86/sse-schedule.ll =================================================================== --- test/CodeGen/X86/sse-schedule.ll +++ test/CodeGen/X86/sse-schedule.ll @@ -6225,7 +6225,7 @@ ; ; BTVER2-SSE-LABEL: test_fnop: ; BTVER2-SSE: # %bb.0: -; BTVER2-SSE-NEXT: xorps %xmm0, %xmm0 # sched: [1:0.50] +; BTVER2-SSE-NEXT: xorps %xmm0, %xmm0 # sched: [0:?] ; BTVER2-SSE-NEXT: #APP ; BTVER2-SSE-NEXT: nop # sched: [1:0.50] ; BTVER2-SSE-NEXT: #NO_APP @@ -6233,7 +6233,7 @@ ; ; BTVER2-LABEL: test_fnop: ; BTVER2: # %bb.0: -; BTVER2-NEXT: vxorps %xmm0, %xmm0, %xmm0 # sched: [1:0.50] +; BTVER2-NEXT: vxorps %xmm0, %xmm0, %xmm0 # sched: [0:?] ; BTVER2-NEXT: #APP ; BTVER2-NEXT: nop # sched: [1:0.50] ; BTVER2-NEXT: #NO_APP Index: test/tools/llvm-mca/X86/BtVer2/zero-idioms.s =================================================================== --- /dev/null +++ test/tools/llvm-mca/X86/BtVer2/zero-idioms.s @@ -0,0 +1,62 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 < %s | FileCheck %s + +xorps %xmm0, %xmm0 +xorpd %xmm1, %xmm1 +vxorps %xmm2, %xmm2, %xmm2 +vxorpd %xmm1, %xmm1, %xmm1 +pxor %xmm2, %xmm2 +vpxor %xmm3, %xmm3, %xmm3 + +# CHECK: Iterations: 100 +# CHECK-NEXT: Instructions: 600 +# CHECK-NEXT: Total Cycles: 301 +# CHECK-NEXT: Dispatch Width: 2 +# CHECK-NEXT: IPC: 1.99 +# CHECK-NEXT: Block RThroughput: 3.0 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 0 - xorps %xmm0, %xmm0 +# CHECK-NEXT: 1 0 - xorpd %xmm1, %xmm1 +# CHECK-NEXT: 1 0 - vxorps %xmm2, %xmm2, %xmm2 +# CHECK-NEXT: 1 0 - vxorpd %xmm1, %xmm1, %xmm1 +# CHECK-NEXT: 1 0 - pxor %xmm2, %xmm2 +# CHECK-NEXT: 1 0 - vpxor %xmm3, %xmm3, %xmm3 + +# CHECK: Resources: +# CHECK-NEXT: [0] - JALU0 +# CHECK-NEXT: [1] - JALU1 +# CHECK-NEXT: [2] - JDiv +# CHECK-NEXT: [3] - JFPA +# CHECK-NEXT: [4] - JFPM +# CHECK-NEXT: [5] - JFPU0 +# CHECK-NEXT: [6] - JFPU1 +# CHECK-NEXT: [7] - JLAGU +# CHECK-NEXT: [8] - JMul +# CHECK-NEXT: [9] - JSAGU +# CHECK-NEXT: [10] - JSTC +# CHECK-NEXT: [11] - JVALU0 +# CHECK-NEXT: [12] - JVALU1 +# CHECK-NEXT: [13] - JVIMUL + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] +# CHECK-NEXT: - - - - - - - - - - - - - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] Instructions: +# CHECK-NEXT: - - - - - - - - - - - - - - xorps %xmm0, %xmm0 +# CHECK-NEXT: - - - - - - - - - - - - - - xorpd %xmm1, %xmm1 +# CHECK-NEXT: - - - - - - - - - - - - - - vxorps %xmm2, %xmm2, %xmm2 +# CHECK-NEXT: - - - - - - - - - - - - - - vxorpd %xmm1, %xmm1, %xmm1 +# CHECK-NEXT: - - - - - - - - - - - - - - pxor %xmm2, %xmm2 +# CHECK-NEXT: - - - - - - - - - - - - - - vpxor %xmm3, %xmm3, %xmm3 + Index: tools/llvm-mca/InstrBuilder.h =================================================================== --- tools/llvm-mca/InstrBuilder.h +++ tools/llvm-mca/InstrBuilder.h @@ -39,10 +39,10 @@ const llvm::MCInstrInfo &MCII; llvm::SmallVector ProcResourceMasks; - llvm::DenseMap> Descriptors; + llvm::DenseMap> + Descriptors; const InstrDesc &createInstrDescImpl(const llvm::MCInst &MCI); - InstrBuilder(const InstrBuilder &) = delete; InstrBuilder &operator=(const InstrBuilder &) = delete; Index: tools/llvm-mca/InstrBuilder.cpp =================================================================== --- tools/llvm-mca/InstrBuilder.cpp +++ tools/llvm-mca/InstrBuilder.cpp @@ -378,18 +378,20 @@ // Then obtain the scheduling class information from the instruction. unsigned SchedClassID = MCDesc.getSchedClass(); - const MCSchedClassDesc &SCDesc = *SM.getSchedClassDesc(SchedClassID); + unsigned CPUID = SM.getProcessorID(); + + // Try to solve variant scheduling classes. + while (SchedClassID && SM.getSchedClassDesc(SchedClassID)->isVariant()) + SchedClassID = STI.resolveVariantSchedClass(SchedClassID, &MCI, CPUID); + + if (!SchedClassID) + llvm::report_fatal_error("unable to resolve this variant class."); // Create a new empty descriptor. std::unique_ptr ID = llvm::make_unique(); - if (SCDesc.isVariant()) { - WithColor::warning() << "don't know how to model variant opcodes.\n"; - WithColor::note() << "assume 1 micro opcode.\n"; - ID->NumMicroOps = 1U; - } else { - ID->NumMicroOps = SCDesc.NumMicroOps; - } + const MCSchedClassDesc &SCDesc = *SM.getSchedClassDesc(SchedClassID); + ID->NumMicroOps = SCDesc.NumMicroOps; if (MCDesc.isCall()) { // We don't correctly model calls. @@ -417,14 +419,15 @@ LLVM_DEBUG(dbgs() << "\t\tNumMicroOps=" << ID->NumMicroOps << '\n'); // Now add the new descriptor. - Descriptors[Opcode] = std::move(ID); - return *Descriptors[Opcode]; + SchedClassID = MCDesc.getSchedClass(); + Descriptors[&MCI] = std::move(ID); + return *Descriptors[&MCI]; } const InstrDesc &InstrBuilder::getOrCreateInstrDesc(const MCInst &MCI) { - if (Descriptors.find_as(MCI.getOpcode()) == Descriptors.end()) + if (Descriptors.find(&MCI) == Descriptors.end()) return createInstrDescImpl(MCI); - return *Descriptors[MCI.getOpcode()]; + return *Descriptors[&MCI]; } std::unique_ptr Index: tools/llvm-mca/InstructionInfoView.cpp =================================================================== --- tools/llvm-mca/InstructionInfoView.cpp +++ tools/llvm-mca/InstructionInfoView.cpp @@ -36,8 +36,17 @@ for (unsigned I = 0, E = Instructions; I < E; ++I) { const MCInst &Inst = Source.getMCInstFromIndex(I); const MCInstrDesc &MCDesc = MCII.get(Inst.getOpcode()); - const MCSchedClassDesc &SCDesc = - *SM.getSchedClassDesc(MCDesc.getSchedClass()); + + // Obtain the scheduling class information from the instruction. + unsigned SchedClassID = MCDesc.getSchedClass(); + unsigned CPUID = SM.getProcessorID(); + + // Try to solve variant scheduling classes. + while (SchedClassID && SM.getSchedClassDesc(SchedClassID)->isVariant()) + SchedClassID = STI.resolveVariantSchedClass(SchedClassID, &Inst, CPUID); + + assert(SchedClassID && "Unable to solve this variant scheduling class!"); + const MCSchedClassDesc &SCDesc = *SM.getSchedClassDesc(SchedClassID); unsigned NumMicroOpcodes = SCDesc.NumMicroOps; unsigned Latency = MCSchedModel::computeInstrLatency(STI, SCDesc);