Index: llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td =================================================================== --- llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -15,14 +15,26 @@ defm ADD_ZZZ : sve_int_bin_cons_arit_0<0b000, "add">; defm SUB_ZZZ : sve_int_bin_cons_arit_0<0b001, "sub">; - defm AND_ZI : sve_int_log_imm<0b10, "and", "bic">; + def AND_ZZZ : sve_int_bin_cons_log<0b00, "and">; + def ORR_ZZZ : sve_int_bin_cons_log<0b01, "orr">; + def EOR_ZZZ : sve_int_bin_cons_log<0b10, "eor">; + def BIC_ZZZ : sve_int_bin_cons_log<0b11, "bic">; defm ADD_ZPmZ : sve_int_bin_pred_arit_0<0b000, "add">; defm SUB_ZPmZ : sve_int_bin_pred_arit_0<0b001, "sub">; + defm ORR_ZPmZ : sve_int_bin_pred_log<0b000, "orr">; + defm EOR_ZPmZ : sve_int_bin_pred_log<0b001, "eor">; + defm AND_ZPmZ : sve_int_bin_pred_log<0b010, "and">; + defm BIC_ZPmZ : sve_int_bin_pred_log<0b011, "bic">; + defm ADD_ZI : sve_int_arith_imm0<0b000, "add">; defm SUB_ZI : sve_int_arith_imm0<0b001, "sub">; + defm ORR_ZI : sve_int_log_imm<0b00, "orr", "orn">; + defm EOR_ZI : sve_int_log_imm<0b01, "eor", "eon">; + defm AND_ZI : sve_int_log_imm<0b10, "and", "bic">; + // Splat immediate (unpredicated) defm DUP_ZI : sve_int_dup_imm<"dup">; @@ -459,4 +471,9 @@ defm LSR_ZZI : sve_int_bin_cons_shift_b_right<0b01, "lsr">; defm LSL_ZZI : sve_int_bin_cons_shift_b_left< 0b11, "lsl">; + + + // InstAliases + def : InstAlias<"mov $Zd, $Zn", + (ORR_ZZZ ZPR64:$Zd, ZPR64:$Zn, ZPR64:$Zn), 1>; } Index: llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td =================================================================== --- llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td +++ llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td @@ -399,6 +399,13 @@ let Constraints = "$Zdn = $_Zdn"; } +multiclass sve_int_bin_pred_log opc, string asm> { + def _B : sve_int_bin_pred_arit_log<0b00, 0b11, opc, asm, ZPR8>; + def _H : sve_int_bin_pred_arit_log<0b01, 0b11, opc, asm, ZPR16>; + def _S : sve_int_bin_pred_arit_log<0b10, 0b11, opc, asm, ZPR32>; + def _D : sve_int_bin_pred_arit_log<0b11, 0b11, opc, asm, ZPR64>; +} + multiclass sve_int_bin_pred_arit_0 opc, string asm> { def _B : sve_int_bin_pred_arit_log<0b00, 0b00, opc, asm, ZPR8>; def _H : sve_int_bin_pred_arit_log<0b01, 0b00, opc, asm, ZPR16>; @@ -470,6 +477,28 @@ def _D : sve_int_arith_imm0<0b11, opc, asm, ZPR64, addsub_imm8_opt_lsl_i64>; } + +//===----------------------------------------------------------------------===// +// SVE Bitwise Logical - Unpredicated Group +//===----------------------------------------------------------------------===// + +class sve_int_bin_cons_log opc, string asm> +: I<(outs ZPR64:$Zd), (ins ZPR64:$Zn, ZPR64:$Zm), + asm, "\t$Zd, $Zn, $Zm", + "", + []>, Sched<[]> { + bits<5> Zd; + bits<5> Zm; + bits<5> Zn; + let Inst{31-24} = 0b00000100; + let Inst{23-22} = opc{1-0}; + let Inst{21} = 0b1; + let Inst{20-16} = Zm; + let Inst{15-10} = 0b001100; + let Inst{9-5} = Zn; + let Inst{4-0} = Zd; +} + //===----------------------------------------------------------------------===// //SVE Index Generation Group //===----------------------------------------------------------------------===// Index: llvm/trunk/test/MC/AArch64/SVE/and-diagnostics.s =================================================================== --- llvm/trunk/test/MC/AArch64/SVE/and-diagnostics.s +++ llvm/trunk/test/MC/AArch64/SVE/and-diagnostics.s @@ -46,7 +46,22 @@ // CHECK-NEXT: and z7.d, z8.d, #254 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: -bic z7.d, z8.d, #254 +and z0.d, p0/m, z1.d, z2.d // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register -// CHECK-NEXT: bic z7.d, z8.d, #254 +// CHECK-NEXT: and z0.d, p0/m, z1.d, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// Element size specifiers should match. +and z21.d, z5.d, z26.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: and z21.d, z5.d, z26.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Predicate out of restricted predicate range + +and z0.d, p8/z, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: and z0.d, p8/z, z0.d, z1.d // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/trunk/test/MC/AArch64/SVE/and.s =================================================================== --- llvm/trunk/test/MC/AArch64/SVE/and.s +++ llvm/trunk/test/MC/AArch64/SVE/and.s @@ -13,44 +13,80 @@ // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: a5 2e 80 05 -bic z5.b, z5.b, #0x06 -// CHECK-INST: and z5.b, z5.b, #0xf9 -// CHECK-ENCODING: [0xa5,0x2e,0x80,0x05] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: a5 2e 80 05 - and z23.h, z23.h, #0xfff9 // CHECK-INST: and z23.h, z23.h, #0xfff9 // CHECK-ENCODING: [0xb7,0x6d,0x80,0x05] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: b7 6d 80 05 -bic z23.h, z23.h, #0x0006 -// CHECK-INST: and z23.h, z23.h, #0xfff9 -// CHECK-ENCODING: [0xb7,0x6d,0x80,0x05] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: b7 6d 80 05 - and z0.s, z0.s, #0xfffffff9 // CHECK-INST: and z0.s, z0.s, #0xfffffff9 // CHECK-ENCODING: [0xa0,0xeb,0x80,0x05] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: a0 eb 80 05 -bic z0.s, z0.s, #0x00000006 -// CHECK-INST: and z0.s, z0.s, #0xfffffff9 -// CHECK-ENCODING: [0xa0,0xeb,0x80,0x05] -// CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: a0 eb 80 05 - and z0.d, z0.d, #0xfffffffffffffff9 // CHECK-INST: and z0.d, z0.d, #0xfffffffffffffff9 // CHECK-ENCODING: [0xa0,0xef,0x83,0x05] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: a0 ef 83 05 -bic z0.d, z0.d, #0x0000000000000006 -// CHECK-INST: and z0.d, z0.d, #0xfffffffffffffff9 -// CHECK-ENCODING: [0xa0,0xef,0x83,0x05] +and z5.b, z5.b, #0x6 +// CHECK-INST: and z5.b, z5.b, #0x6 +// CHECK-ENCODING: [0x25,0x3e,0x80,0x05] // CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: a0 ef 83 05 +// CHECK-UNKNOWN: 25 3e 80 05 + +and z23.h, z23.h, #0x6 +// CHECK-INST: and z23.h, z23.h, #0x6 +// CHECK-ENCODING: [0x37,0x7c,0x80,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 37 7c 80 05 + +and z0.s, z0.s, #0x6 +// CHECK-INST: and z0.s, z0.s, #0x6 +// CHECK-ENCODING: [0x20,0xf8,0x80,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 f8 80 05 + +and z0.d, z0.d, #0x6 +// CHECK-INST: and z0.d, z0.d, #0x6 +// CHECK-ENCODING: [0x20,0xf8,0x83,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 f8 83 05 + +and z0.d, z0.d, z0.d +// CHECK-INST: and z0.d, z0.d, z0.d +// CHECK-ENCODING: [0x00,0x30,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 30 20 04 + +and z23.d, z13.d, z8.d +// CHECK-INST: and z23.d, z13.d, z8.d +// CHECK-ENCODING: [0xb7,0x31,0x28,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: b7 31 28 04 + +and z31.b, p7/m, z31.b, z31.b +// CHECK-INST: and z31.b, p7/m, z31.b, z31.b +// CHECK-ENCODING: [0xff,0x1f,0x1a,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 1f 1a 04 + +and z31.h, p7/m, z31.h, z31.h +// CHECK-INST: and z31.h, p7/m, z31.h, z31.h +// CHECK-ENCODING: [0xff,0x1f,0x5a,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 1f 5a 04 + +and z31.s, p7/m, z31.s, z31.s +// CHECK-INST: and z31.s, p7/m, z31.s, z31.s +// CHECK-ENCODING: [0xff,0x1f,0x9a,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 1f 9a 04 + +and z31.d, p7/m, z31.d, z31.d +// CHECK-INST: and z31.d, p7/m, z31.d, z31.d +// CHECK-ENCODING: [0xff,0x1f,0xda,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 1f da 04 Index: llvm/trunk/test/MC/AArch64/SVE/bic-diagnostics.s =================================================================== --- llvm/trunk/test/MC/AArch64/SVE/bic-diagnostics.s +++ llvm/trunk/test/MC/AArch64/SVE/bic-diagnostics.s @@ -0,0 +1,67 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Immediate not compatible with encode/decode function. + +bic z5.b, z5.b, #0xfa +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate +// CHECK-NEXT: bic z5.b, z5.b, #0xfa +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bic z5.b, z5.b, #0xfff9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate +// CHECK-NEXT: bic z5.b, z5.b, #0xfff9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bic z5.h, z5.h, #0xfffa +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate +// CHECK-NEXT: bic z5.h, z5.h, #0xfffa +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bic z5.h, z5.h, #0xfffffff9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate +// CHECK-NEXT: bic z5.h, z5.h, #0xfffffff9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bic z5.s, z5.s, #0xfffffffa +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate +// CHECK-NEXT: bic z5.s, z5.s, #0xfffffffa +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bic z5.s, z5.s, #0xffffffffffffff9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate +// CHECK-NEXT: bic z5.s, z5.s, #0xffffffffffffff9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bic z15.d, z15.d, #0xfffffffffffffffa +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate +// CHECK-NEXT: bic z15.d, z15.d, #0xfffffffffffffffa +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +bic z7.d, z8.d, #254 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: bic z7.d, z8.d, #254 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bic z0.d, p0/m, z1.d, z2.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: bic z0.d, p0/m, z1.d, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// Element size specifiers should match. +bic z21.d, z5.d, z26.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: bic z21.d, z5.d, z26.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Predicate out of restricted predicate range + +bic z0.d, p8/z, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: bic z0.d, p8/z, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/trunk/test/MC/AArch64/SVE/bic.s =================================================================== --- llvm/trunk/test/MC/AArch64/SVE/bic.s +++ llvm/trunk/test/MC/AArch64/SVE/bic.s @@ -0,0 +1,92 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +bic z5.b, z5.b, #0xf9 +// CHECK-INST: and z5.b, z5.b, #0x6 +// CHECK-ENCODING: [0x25,0x3e,0x80,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 25 3e 80 05 + +bic z23.h, z23.h, #0xfff9 +// CHECK-INST: and z23.h, z23.h, #0x6 +// CHECK-ENCODING: [0x37,0x7c,0x80,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 37 7c 80 05 + +bic z0.s, z0.s, #0xfffffff9 +// CHECK-INST: and z0.s, z0.s, #0x6 +// CHECK-ENCODING: [0x20,0xf8,0x80,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 f8 80 05 + +bic z0.d, z0.d, #0xfffffffffffffff9 +// CHECK-INST: and z0.d, z0.d, #0x6 +// CHECK-ENCODING: [0x20,0xf8,0x83,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 f8 83 05 + +bic z5.b, z5.b, #0x6 +// CHECK-INST: and z5.b, z5.b, #0xf9 +// CHECK-ENCODING: [0xa5,0x2e,0x80,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: a5 2e 80 05 + +bic z23.h, z23.h, #0x6 +// CHECK-INST: and z23.h, z23.h, #0xfff9 +// CHECK-ENCODING: [0xb7,0x6d,0x80,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: b7 6d 80 05 + +bic z0.s, z0.s, #0x6 +// CHECK-INST: and z0.s, z0.s, #0xfffffff9 +// CHECK-ENCODING: [0xa0,0xeb,0x80,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: a0 eb 80 05 + +bic z0.d, z0.d, #0x6 +// CHECK-INST: and z0.d, z0.d, #0xfffffffffffffff9 +// CHECK-ENCODING: [0xa0,0xef,0x83,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: a0 ef 83 05 + +bic z0.d, z0.d, z0.d +// CHECK-INST: bic z0.d, z0.d, z0.d +// CHECK-ENCODING: [0x00,0x30,0xe0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 30 e0 04 + +bic z23.d, z13.d, z8.d +// CHECK-INST: bic z23.d, z13.d, z8.d +// CHECK-ENCODING: [0xb7,0x31,0xe8,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: b7 31 e8 04 + +bic z31.b, p7/m, z31.b, z31.b +// CHECK-INST: bic z31.b, p7/m, z31.b, z31.b +// CHECK-ENCODING: [0xff,0x1f,0x1b,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 1f 1b 04 + +bic z31.h, p7/m, z31.h, z31.h +// CHECK-INST: bic z31.h, p7/m, z31.h, z31.h +// CHECK-ENCODING: [0xff,0x1f,0x5b,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 1f 5b 04 + +bic z31.s, p7/m, z31.s, z31.s +// CHECK-INST: bic z31.s, p7/m, z31.s, z31.s +// CHECK-ENCODING: [0xff,0x1f,0x9b,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 1f 9b 04 + +bic z31.d, p7/m, z31.d, z31.d +// CHECK-INST: bic z31.d, p7/m, z31.d, z31.d +// CHECK-ENCODING: [0xff,0x1f,0xdb,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 1f db 04 Index: llvm/trunk/test/MC/AArch64/SVE/eon-diagnostics.s =================================================================== --- llvm/trunk/test/MC/AArch64/SVE/eon-diagnostics.s +++ llvm/trunk/test/MC/AArch64/SVE/eon-diagnostics.s @@ -0,0 +1,52 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Immediate not compatible with encode/decode function. + +eon z5.b, z5.b, #0xfa +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate +// CHECK-NEXT: eon z5.b, z5.b, #0xfa +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +eon z5.b, z5.b, #0xfff9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate +// CHECK-NEXT: eon z5.b, z5.b, #0xfff9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +eon z5.h, z5.h, #0xfffa +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate +// CHECK-NEXT: eon z5.h, z5.h, #0xfffa +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +eon z5.h, z5.h, #0xfffffff9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate +// CHECK-NEXT: eon z5.h, z5.h, #0xfffffff9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +eon z5.s, z5.s, #0xfffffffa +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate +// CHECK-NEXT: eon z5.s, z5.s, #0xfffffffa +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +eon z5.s, z5.s, #0xffffffffffffff9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate +// CHECK-NEXT: eon z5.s, z5.s, #0xffffffffffffff9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +eon z15.d, z15.d, #0xfffffffffffffffa +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate +// CHECK-NEXT: eon z15.d, z15.d, #0xfffffffffffffffa +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +eon z7.d, z8.d, #254 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: eon z7.d, z8.d, #254 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +eon z7.d, z8.d, #254 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: eon z7.d, z8.d, #254 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/trunk/test/MC/AArch64/SVE/eon.s =================================================================== --- llvm/trunk/test/MC/AArch64/SVE/eon.s +++ llvm/trunk/test/MC/AArch64/SVE/eon.s @@ -0,0 +1,56 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +eon z5.b, z5.b, #0xf9 +// CHECK-INST: eor z5.b, z5.b, #0x6 +// CHECK-ENCODING: [0x25,0x3e,0x40,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 25 3e 40 05 + +eon z23.h, z23.h, #0xfff9 +// CHECK-INST: eor z23.h, z23.h, #0x6 +// CHECK-ENCODING: [0x37,0x7c,0x40,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 37 7c 40 05 + +eon z0.s, z0.s, #0xfffffff9 +// CHECK-INST: eor z0.s, z0.s, #0x6 +// CHECK-ENCODING: [0x20,0xf8,0x40,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 f8 40 05 + +eon z0.d, z0.d, #0xfffffffffffffff9 +// CHECK-INST: eor z0.d, z0.d, #0x6 +// CHECK-ENCODING: [0x20,0xf8,0x43,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 f8 43 05 + +eon z5.b, z5.b, #0x6 +// CHECK-INST: eor z5.b, z5.b, #0xf9 +// CHECK-ENCODING: [0xa5,0x2e,0x40,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: a5 2e 40 05 + +eon z23.h, z23.h, #0x6 +// CHECK-INST: eor z23.h, z23.h, #0xfff9 +// CHECK-ENCODING: [0xb7,0x6d,0x40,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: b7 6d 40 05 + +eon z0.s, z0.s, #0x6 +// CHECK-INST: eor z0.s, z0.s, #0xfffffff9 +// CHECK-ENCODING: [0xa0,0xeb,0x40,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: a0 eb 40 05 + +eon z0.d, z0.d, #0x6 +// CHECK-INST: eor z0.d, z0.d, #0xfffffffffffffff9 +// CHECK-ENCODING: [0xa0,0xef,0x43,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: a0 ef 43 05 Index: llvm/trunk/test/MC/AArch64/SVE/eor-diagnostics.s =================================================================== --- llvm/trunk/test/MC/AArch64/SVE/eor-diagnostics.s +++ llvm/trunk/test/MC/AArch64/SVE/eor-diagnostics.s @@ -0,0 +1,67 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Immediate not compatible with encode/decode function. + +eor z5.b, z5.b, #0xfa +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate +// CHECK-NEXT: eor z5.b, z5.b, #0xfa +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +eor z5.b, z5.b, #0xfff9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate +// CHECK-NEXT: eor z5.b, z5.b, #0xfff9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +eor z5.h, z5.h, #0xfffa +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate +// CHECK-NEXT: eor z5.h, z5.h, #0xfffa +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +eor z5.h, z5.h, #0xfffffff9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate +// CHECK-NEXT: eor z5.h, z5.h, #0xfffffff9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +eor z5.s, z5.s, #0xfffffffa +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate +// CHECK-NEXT: eor z5.s, z5.s, #0xfffffffa +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +eor z5.s, z5.s, #0xffffffffffffff9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate +// CHECK-NEXT: eor z5.s, z5.s, #0xffffffffffffff9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +eor z15.d, z15.d, #0xfffffffffffffffa +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate +// CHECK-NEXT: eor z15.d, z15.d, #0xfffffffffffffffa +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +eor z7.d, z8.d, #254 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: eor z7.d, z8.d, #254 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +eor z0.d, p0/m, z1.d, z2.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: eor z0.d, p0/m, z1.d, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// Element size specifiers should match. +eor z21.d, z5.d, z26.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: eor z21.d, z5.d, z26.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Predicate out of restricted predicate range + +eor z0.d, p8/z, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: eor z0.d, p8/z, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/trunk/test/MC/AArch64/SVE/eor.s =================================================================== --- llvm/trunk/test/MC/AArch64/SVE/eor.s +++ llvm/trunk/test/MC/AArch64/SVE/eor.s @@ -0,0 +1,92 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +eor z5.b, z5.b, #0xf9 +// CHECK-INST: eor z5.b, z5.b, #0xf9 +// CHECK-ENCODING: [0xa5,0x2e,0x40,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: a5 2e 40 05 + +eor z23.h, z23.h, #0xfff9 +// CHECK-INST: eor z23.h, z23.h, #0xfff9 +// CHECK-ENCODING: [0xb7,0x6d,0x40,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: b7 6d 40 05 + +eor z0.s, z0.s, #0xfffffff9 +// CHECK-INST: eor z0.s, z0.s, #0xfffffff9 +// CHECK-ENCODING: [0xa0,0xeb,0x40,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: a0 eb 40 05 + +eor z0.d, z0.d, #0xfffffffffffffff9 +// CHECK-INST: eor z0.d, z0.d, #0xfffffffffffffff9 +// CHECK-ENCODING: [0xa0,0xef,0x43,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: a0 ef 43 05 + +eor z5.b, z5.b, #0x6 +// CHECK-INST: eor z5.b, z5.b, #0x6 +// CHECK-ENCODING: [0x25,0x3e,0x40,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 25 3e 40 05 + +eor z23.h, z23.h, #0x6 +// CHECK-INST: eor z23.h, z23.h, #0x6 +// CHECK-ENCODING: [0x37,0x7c,0x40,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 37 7c 40 05 + +eor z0.s, z0.s, #0x6 +// CHECK-INST: eor z0.s, z0.s, #0x6 +// CHECK-ENCODING: [0x20,0xf8,0x40,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 f8 40 05 + +eor z0.d, z0.d, #0x6 +// CHECK-INST: eor z0.d, z0.d, #0x6 +// CHECK-ENCODING: [0x20,0xf8,0x43,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 f8 43 05 + +eor z23.d, z13.d, z8.d +// CHECK-INST: eor z23.d, z13.d, z8.d +// CHECK-ENCODING: [0xb7,0x31,0xa8,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: b7 31 a8 04 + +eor z0.d, z0.d, z0.d +// CHECK-INST: eor z0.d, z0.d, z0.d +// CHECK-ENCODING: [0x00,0x30,0xa0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 30 a0 04 + +eor z31.s, p7/m, z31.s, z31.s +// CHECK-INST: eor z31.s, p7/m, z31.s, z31.s +// CHECK-ENCODING: [0xff,0x1f,0x99,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 1f 99 04 + +eor z31.h, p7/m, z31.h, z31.h +// CHECK-INST: eor z31.h, p7/m, z31.h, z31.h +// CHECK-ENCODING: [0xff,0x1f,0x59,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 1f 59 04 + +eor z31.d, p7/m, z31.d, z31.d +// CHECK-INST: eor z31.d, p7/m, z31.d, z31.d +// CHECK-ENCODING: [0xff,0x1f,0xd9,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 1f d9 04 + +eor z31.b, p7/m, z31.b, z31.b +// CHECK-INST: eor z31.b, p7/m, z31.b, z31.b +// CHECK-ENCODING: [0xff,0x1f,0x19,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 1f 19 04 Index: llvm/trunk/test/MC/AArch64/SVE/mov-diagnostics.s =================================================================== --- llvm/trunk/test/MC/AArch64/SVE/mov-diagnostics.s +++ llvm/trunk/test/MC/AArch64/SVE/mov-diagnostics.s @@ -20,6 +20,24 @@ // --------------------------------------------------------------------------// +// Unpredicated mov of Z register only allowed for .d + +mov z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: mov z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +mov z0.h, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: mov z0.h, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +mov z0.s, z1.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: mov z0.s, z1.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// // Invalid immediates mov z0.b, #0, lsl #8 // #0, lsl #8 is not valid for .b Index: llvm/trunk/test/MC/AArch64/SVE/mov.s =================================================================== --- llvm/trunk/test/MC/AArch64/SVE/mov.s +++ llvm/trunk/test/MC/AArch64/SVE/mov.s @@ -55,6 +55,18 @@ // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff 3b 20 05 +mov z0.d, z0.d +// CHECK-INST: mov z0.d, z0.d +// CHECK-ENCODING: [0x00,0x30,0x60,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 30 60 04 + +mov z31.d, z0.d +// CHECK-INST: mov z31.d, z0.d +// CHECK-ENCODING: [0x1f,0x30,0x60,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 1f 30 60 04 + mov z5.b, #-128 // CHECK-INST: mov z5.b, #-128 // CHECK-ENCODING: [0x05,0xd0,0x38,0x25] Index: llvm/trunk/test/MC/AArch64/SVE/orn-diagnostics.s =================================================================== --- llvm/trunk/test/MC/AArch64/SVE/orn-diagnostics.s +++ llvm/trunk/test/MC/AArch64/SVE/orn-diagnostics.s @@ -0,0 +1,52 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Immediate not compatible with encode/decode function. + +orn z5.b, z5.b, #0xfa +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate +// CHECK-NEXT: orn z5.b, z5.b, #0xfa +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +orn z5.b, z5.b, #0xfff9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate +// CHECK-NEXT: orn z5.b, z5.b, #0xfff9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +orn z5.h, z5.h, #0xfffa +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate +// CHECK-NEXT: orn z5.h, z5.h, #0xfffa +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +orn z5.h, z5.h, #0xfffffff9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate +// CHECK-NEXT: orn z5.h, z5.h, #0xfffffff9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +orn z5.s, z5.s, #0xfffffffa +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate +// CHECK-NEXT: orn z5.s, z5.s, #0xfffffffa +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +orn z5.s, z5.s, #0xffffffffffffff9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate +// CHECK-NEXT: orn z5.s, z5.s, #0xffffffffffffff9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +orn z15.d, z15.d, #0xfffffffffffffffa +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate +// CHECK-NEXT: orn z15.d, z15.d, #0xfffffffffffffffa +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +orn z7.d, z8.d, #254 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: orn z7.d, z8.d, #254 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +orn z7.d, z8.d, #254 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: orn z7.d, z8.d, #254 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/trunk/test/MC/AArch64/SVE/orn.s =================================================================== --- llvm/trunk/test/MC/AArch64/SVE/orn.s +++ llvm/trunk/test/MC/AArch64/SVE/orn.s @@ -0,0 +1,56 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +orn z5.b, z5.b, #0xf9 +// CHECK-INST: orr z5.b, z5.b, #0x6 +// CHECK-ENCODING: [0x25,0x3e,0x00,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 25 3e 00 05 + +orn z23.h, z23.h, #0xfff9 +// CHECK-INST: orr z23.h, z23.h, #0x6 +// CHECK-ENCODING: [0x37,0x7c,0x00,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 37 7c 00 05 + +orn z0.s, z0.s, #0xfffffff9 +// CHECK-INST: orr z0.s, z0.s, #0x6 +// CHECK-ENCODING: [0x20,0xf8,0x00,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 f8 00 05 + +orn z0.d, z0.d, #0xfffffffffffffff9 +// CHECK-INST: orr z0.d, z0.d, #0x6 +// CHECK-ENCODING: [0x20,0xf8,0x03,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 f8 03 05 + +orn z5.b, z5.b, #0x6 +// CHECK-INST: orr z5.b, z5.b, #0xf9 +// CHECK-ENCODING: [0xa5,0x2e,0x00,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: a5 2e 00 05 + +orn z23.h, z23.h, #0x6 +// CHECK-INST: orr z23.h, z23.h, #0xfff9 +// CHECK-ENCODING: [0xb7,0x6d,0x00,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: b7 6d 00 05 + +orn z0.s, z0.s, #0x6 +// CHECK-INST: orr z0.s, z0.s, #0xfffffff9 +// CHECK-ENCODING: [0xa0,0xeb,0x00,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: a0 eb 00 05 + +orn z0.d, z0.d, #0x6 +// CHECK-INST: orr z0.d, z0.d, #0xfffffffffffffff9 +// CHECK-ENCODING: [0xa0,0xef,0x03,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: a0 ef 03 05 Index: llvm/trunk/test/MC/AArch64/SVE/orr-diagnostics.s =================================================================== --- llvm/trunk/test/MC/AArch64/SVE/orr-diagnostics.s +++ llvm/trunk/test/MC/AArch64/SVE/orr-diagnostics.s @@ -0,0 +1,67 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Immediate not compatible with encode/decode function. + +orr z5.b, z5.b, #0xfa +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate +// CHECK-NEXT: orr z5.b, z5.b, #0xfa +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +orr z5.b, z5.b, #0xfff9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate +// CHECK-NEXT: orr z5.b, z5.b, #0xfff9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +orr z5.h, z5.h, #0xfffa +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate +// CHECK-NEXT: orr z5.h, z5.h, #0xfffa +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +orr z5.h, z5.h, #0xfffffff9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate +// CHECK-NEXT: orr z5.h, z5.h, #0xfffffff9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +orr z5.s, z5.s, #0xfffffffa +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate +// CHECK-NEXT: orr z5.s, z5.s, #0xfffffffa +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +orr z5.s, z5.s, #0xffffffffffffff9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate +// CHECK-NEXT: orr z5.s, z5.s, #0xffffffffffffff9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +orr z15.d, z15.d, #0xfffffffffffffffa +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate +// CHECK-NEXT: orr z15.d, z15.d, #0xfffffffffffffffa +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +orr z7.d, z8.d, #254 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: orr z7.d, z8.d, #254 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +orr z0.d, p0/m, z1.d, z2.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: orr z0.d, p0/m, z1.d, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// Element size specifiers should match. +orr z21.d, z5.d, z26.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: orr z21.d, z5.d, z26.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Predicate out of restricted predicate range + +orr z0.d, p8/z, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: orr z0.d, p8/z, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/trunk/test/MC/AArch64/SVE/orr.s =================================================================== --- llvm/trunk/test/MC/AArch64/SVE/orr.s +++ llvm/trunk/test/MC/AArch64/SVE/orr.s @@ -0,0 +1,94 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + + +orr z5.b, z5.b, #0xf9 +// CHECK-INST: orr z5.b, z5.b, #0xf9 +// CHECK-ENCODING: [0xa5,0x2e,0x00,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: a5 2e 00 05 + +orr z23.h, z23.h, #0xfff9 +// CHECK-INST: orr z23.h, z23.h, #0xfff9 +// CHECK-ENCODING: [0xb7,0x6d,0x00,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: b7 6d 00 05 + +orr z0.s, z0.s, #0xfffffff9 +// CHECK-INST: orr z0.s, z0.s, #0xfffffff9 +// CHECK-ENCODING: [0xa0,0xeb,0x00,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: a0 eb 00 05 + +orr z0.d, z0.d, #0xfffffffffffffff9 +// CHECK-INST: orr z0.d, z0.d, #0xfffffffffffffff9 +// CHECK-ENCODING: [0xa0,0xef,0x03,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: a0 ef 03 05 + +orr z5.b, z5.b, #0x6 +// CHECK-INST: orr z5.b, z5.b, #0x6 +// CHECK-ENCODING: [0x25,0x3e,0x00,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 25 3e 00 05 + +orr z23.h, z23.h, #0x6 +// CHECK-INST: orr z23.h, z23.h, #0x6 +// CHECK-ENCODING: [0x37,0x7c,0x00,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 37 7c 00 05 + +orr z0.s, z0.s, #0x6 +// CHECK-INST: orr z0.s, z0.s, #0x6 +// CHECK-ENCODING: [0x20,0xf8,0x00,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 f8 00 05 + +orr z0.d, z0.d, #0x6 +// CHECK-INST: orr z0.d, z0.d, #0x6 +// CHECK-ENCODING: [0x20,0xf8,0x03,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 f8 03 05 + +orr z0.d, z0.d, z0.d // should use mov-alias +// CHECK-INST: mov z0.d, z0.d +// CHECK-ENCODING: [0x00,0x30,0x60,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 30 60 04 + +orr z23.d, z13.d, z8.d // should not use mov-alias +// CHECK-INST: orr z23.d, z13.d, z8.d +// CHECK-ENCODING: [0xb7,0x31,0x68,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: b7 31 68 04 + +orr z31.b, p7/m, z31.b, z31.b +// CHECK-INST: orr z31.b, p7/m, z31.b, z31.b +// CHECK-ENCODING: [0xff,0x1f,0x18,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 1f 18 04 + +orr z31.h, p7/m, z31.h, z31.h +// CHECK-INST: orr z31.h, p7/m, z31.h, z31.h +// CHECK-ENCODING: [0xff,0x1f,0x58,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 1f 58 04 + +orr z31.s, p7/m, z31.s, z31.s +// CHECK-INST: orr z31.s, p7/m, z31.s, z31.s +// CHECK-ENCODING: [0xff,0x1f,0x98,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 1f 98 04 + +orr z31.d, p7/m, z31.d, z31.d +// CHECK-INST: orr z31.d, p7/m, z31.d, z31.d +// CHECK-ENCODING: [0xff,0x1f,0xd8,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 1f d8 04