Index: llvm/trunk/docs/CommandGuide/llvm-exegesis.rst =================================================================== --- llvm/trunk/docs/CommandGuide/llvm-exegesis.rst +++ llvm/trunk/docs/CommandGuide/llvm-exegesis.rst @@ -113,20 +113,10 @@ :program:`llvm-exegesis` will also analyze the clusters to point out inconsistencies in the scheduling information. The output is an html file. For -example, `/tmp/inconsistencies.html` will contain messages like: +example, `/tmp/inconsistencies.html` will contain messages like the following : -.. code-block:: none - - Sched Class EXTRACTPSrr_VEXTRACTPSrr contains instructions with distinct performance characteristics, falling into 2 clusters: - 4,EXTRACTPSrr,,3.00 - 3,VEXTRACTPSrr,,2.01 - - Sched Class WriteCRC32 contains instructions with distinct performance characteristics, falling into 2 clusters: - 4,CRC32r32r16,,3.01 - 4,CRC32r32r32,,3.00 - 11,CRC32r32r8,,4.01 - 4,CRC32r64r64,,3.01 - 4,CRC32r64r8,,3.00 +.. image:: llvm-exegesis-analysis.png + :align: center Note that the scheduling class names will be resolved only when :program:`llvm-exegesis` is compiled in debug mode, else only the class id will Index: llvm/trunk/tools/llvm-exegesis/lib/Analysis.h =================================================================== --- llvm/trunk/tools/llvm-exegesis/lib/Analysis.h +++ llvm/trunk/tools/llvm-exegesis/lib/Analysis.h @@ -42,8 +42,10 @@ private: void printInstructionRowCsv(size_t PointId, llvm::raw_ostream &OS) const; - void printSchedClassHtml(std::vector PointIds, - llvm::raw_ostream &OS) const; + void printSchedClassClustersHtml(std::vector PointIds, + llvm::raw_ostream &OS) const; + void printSchedClassDescHtml(const llvm::MCSchedClassDesc &SCDesc, + llvm::raw_ostream &OS) const; // Builds a map of Sched Class -> indices of points that belong to the sched // class. Index: llvm/trunk/tools/llvm-exegesis/lib/Analysis.cpp =================================================================== --- llvm/trunk/tools/llvm-exegesis/lib/Analysis.cpp +++ llvm/trunk/tools/llvm-exegesis/lib/Analysis.cpp @@ -167,8 +167,8 @@ return PointsPerSchedClass; } -void Analysis::printSchedClassHtml(std::vector PointIds, - llvm::raw_ostream &OS) const { +void Analysis::printSchedClassClustersHtml(std::vector PointIds, + llvm::raw_ostream &OS) const { assert(!PointIds.empty()); // Sort the points by cluster id so that we can display them grouped by // cluster. @@ -178,7 +178,7 @@ Clustering_.getClusterIdForPoint(B); }); const auto &Points = Clustering_.getPoints(); - OS << ""; + OS << "
"; OS << ""; for (const auto &Measurement : Points[PointIds[0]].Measurements) { OS << "
ClusterIdOpcode/Config"; @@ -214,6 +214,120 @@ OS << "
"; } +// Return the non-redundant list of WriteProcRes used by the given sched class. +// The scheduling model for LLVM is such that each instruction has a certain +// number of uops which consume resources which are described by WriteProcRes +// entries. Each entry describe how many cycles are spent on a specific ProcRes +// kind. +// For example, an instruction might have 3 uOps, one dispatching on P0 +// (ProcResIdx=1) and two on P06 (ProcResIdx = 7). +// Note that LLVM additionally denormalizes resource consumption to include +// usage of super resources by subresources. So in practice if there exists a +// P016 (ProcResIdx=10), then the cycles consumed by P0 are also consumed by +// P06 (ProcResIdx = 7) and P016 (ProcResIdx = 10), and the resources consumed +// by P06 are also consumed by P016. In the figure below, parenthesized cycles +// denote implied usage of superresources by subresources: +// P0 P06 P016 +// uOp1 1 (1) (1) +// uOp2 1 (1) +// uOp3 1 (1) +// ============================= +// 1 3 3 +// Eventually we end up with three entries for the WriteProcRes of the +// instruction: +// {ProcResIdx=1, Cycles=1} // P0 +// {ProcResIdx=7, Cycles=3} // P06 +// {ProcResIdx=10, Cycles=3} // P016 +// +// Note that in this case, P016 does not contribute any cycles, so it would +// be removed by this function. +// FIXME: Move this to MCSubtargetInfo and use it in llvm-mca. +static llvm::SmallVector +getNonRedundantWriteProcRes(const llvm::MCSchedClassDesc &SCDesc, + const llvm::MCSubtargetInfo &STI) { + llvm::SmallVector Result; + const auto &SM = STI.getSchedModel(); + const unsigned NumProcRes = SM.getNumProcResourceKinds(); + + // This assumes that the ProcResDescs are sorted in topological order, which + // is guaranteed by the tablegen backend. + llvm::SmallVector ProcResUnitUsage(NumProcRes); + for (const auto *WPR = STI.getWriteProcResBegin(&SCDesc), + *const WPREnd = STI.getWriteProcResEnd(&SCDesc); + WPR != WPREnd; ++WPR) { + const llvm::MCProcResourceDesc *const ProcResDesc = + SM.getProcResource(WPR->ProcResourceIdx); + if (ProcResDesc->SubUnitsIdxBegin == nullptr) { + // This is a ProcResUnit. + Result.push_back({WPR->ProcResourceIdx, WPR->Cycles}); + ProcResUnitUsage[WPR->ProcResourceIdx] += WPR->Cycles; + } else { + // This is a ProcResGroup. First see if it contributes any cycles or if + // it has cycles just from subunits. + float RemainingCycles = WPR->Cycles; + for (const auto *SubResIdx = ProcResDesc->SubUnitsIdxBegin; + SubResIdx != ProcResDesc->SubUnitsIdxBegin + ProcResDesc->NumUnits; + ++SubResIdx) { + RemainingCycles -= ProcResUnitUsage[*SubResIdx]; + } + if (RemainingCycles < 0.01f) { + // The ProcResGroup contributes no cycles of its own. + continue; + } + // The ProcResGroup contributes `RemainingCycles` cycles of its own. + Result.push_back({WPR->ProcResourceIdx, + static_cast(std::round(RemainingCycles))}); + // Spread the remaining cycles over all subunits. + for (const auto *SubResIdx = ProcResDesc->SubUnitsIdxBegin; + SubResIdx != ProcResDesc->SubUnitsIdxBegin + ProcResDesc->NumUnits; + ++SubResIdx) { + ProcResUnitUsage[*SubResIdx] += RemainingCycles / ProcResDesc->NumUnits; + } + } + } + return Result; +} + +void Analysis::printSchedClassDescHtml(const llvm::MCSchedClassDesc &SCDesc, + llvm::raw_ostream &OS) const { + OS << ""; + OS << ""; + if (SCDesc.isValid()) { + OS << ""; + OS << ""; + OS << ""; + // Latencies. + OS << ""; + // WriteProcRes. + OS << ""; + OS << ""; + } else { + OS << ""; + } + OS << "
ValidVariantuOpsLatencyWriteProcRes
✔" << (SCDesc.isVariant() ? "✔" : "✕") << "" << SCDesc.NumMicroOps << "
    "; + for (int I = 0, E = SCDesc.NumWriteLatencyEntries; I < E; ++I) { + const auto *const Entry = + SubtargetInfo_->getWriteLatencyEntry(&SCDesc, I); + OS << "
  • " << Entry->Cycles; + if (SCDesc.NumWriteLatencyEntries > 1) { + // Dismabiguate if more than 1 latency. + OS << " (WriteResourceID " << Entry->WriteResourceID << ")"; + } + OS << "
    • "; + } + OS << "
    "; + for (const auto &WPR : + getNonRedundantWriteProcRes(SCDesc, *SubtargetInfo_)) { + OS << "
  • "; + writeEscaped(OS, SubtargetInfo_->getSchedModel() + .getProcResource(WPR.ProcResourceIdx) + ->Name); + OS << ": " << WPR.Cycles << "
    • "; + } + OS << "
✕
"; +} + static constexpr const char kHtmlHead[] = R"( llvm-exegesis Analysis Results @@ -234,23 +348,29 @@ div.inconsistency { margin-top: 50px; } -table.sched-class { +table { margin-left: 50px; border-collapse: collapse; } -table.sched-class, table.sched-class tr,td,th { +table, table tr,td,th { border: 1px solid #444; } -table.sched-class td { +table ul { + padding-left: 0px; + margin: 0px; + list-style-type: none; +} +table.sched-class-clusters td { padding-left: 10px; padding-right: 10px; padding-top: 10px; padding-bottom: 10px; } -table.sched-class ul { - padding-left: 0px; - margin: 0px; - list-style-type: none; +table.sched-class-desc td { + padding-left: 10px; + padding-right: 10px; + padding-top: 2px; + padding-bottom: 2px; } span.mono { font-family: monospace; @@ -284,12 +404,14 @@ if (ClustersForSchedClass.size() <= 1) continue; // Nothing weird. - OS << "

Sched Class "; -#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) const auto &SchedModel = SubtargetInfo_->getSchedModel(); const llvm::MCSchedClassDesc *const SCDesc = SchedModel.getSchedClassDesc(SchedClassAndPoints.first); + if (!SCDesc) + continue; + OS << "

Sched Class "; +#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) writeEscaped(OS, SCDesc->Name); #else OS << SchedClassAndPoints.first; @@ -297,7 +419,9 @@ OS << " contains instructions with distinct performance " "characteristics, falling into " << ClustersForSchedClass.size() << " clusters:

"; - printSchedClassHtml(SchedClassAndPoints.second, OS); + printSchedClassClustersHtml(SchedClassAndPoints.second, OS); + OS << "

llvm data:

"; + printSchedClassDescHtml(*SCDesc, OS); OS << "
"; }