Index: lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -15844,13 +15844,17 @@
       // Only do this if we won't split any elements.
       if (ExtractSize % EltSize == 0) {
         unsigned NumElems = ExtractSize / EltSize;
-        EVT ExtractVT = EVT::getVectorVT(*DAG.getContext(),
-                                         InVT.getVectorElementType(), NumElems);
+        EVT EltVT = InVT.getVectorElementType();
+        EVT ExtractVT = NumElems == 1 ? EltVT :
+          EVT::getVectorVT(*DAG.getContext(), EltVT, NumElems);
         if ((Level < AfterLegalizeDAG ||
-             TLI.isOperationLegal(ISD::BUILD_VECTOR, ExtractVT)) &&
+             (NumElems == 1 ||
+              TLI.isOperationLegal(ISD::BUILD_VECTOR, ExtractVT))) &&
             (!LegalTypes || TLI.isTypeLegal(ExtractVT))) {
           unsigned IdxVal = (Idx->getZExtValue() * NVT.getScalarSizeInBits()) /
                             EltSize;
+          if (NumElems == 1)
+            return DAG.getBitcast(NVT, V->getOperand(IdxVal));
 
           // Extract the pieces from the original build_vector.
           SDValue BuildVec = DAG.getBuildVector(ExtractVT, SDLoc(N),
Index: test/CodeGen/ARM/2013-05-13-DAGCombiner-undef-mask.ll
===================================================================
--- test/CodeGen/ARM/2013-05-13-DAGCombiner-undef-mask.ll
+++ test/CodeGen/ARM/2013-05-13-DAGCombiner-undef-mask.ll
@@ -1,7 +1,22 @@
-; RUN: llc < %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s | FileCheck %s
 target triple = "armv7-none-linux-gnueabi"
 
+; CHECK-LABEL: {{^}}shuffle:
 define <3 x i64> @shuffle(i1 %dec1, i1 %dec0, <3 x i64> %b) {
+; CHECK-LABEL: shuffle:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    tst r1, #1
+; CHECK-NEXT:    moveq r1, #0
+; CHECK-NEXT:    vmoveq d16, r1, r1
+; CHECK-NEXT:    vldrne d16, [sp]
+; CHECK-NEXT:    tst r2, #1
+; CHECK-NEXT:    moveq r1, #0
+; CHECK-NEXT:    vmoveq d18, r1, r1
+; CHECK-NEXT:    vldrne d18, [sp, #8]
+; CHECK-NEXT:    vorr d17, d18, d18
+; CHECK-NEXT:    vst1.64 {d16, d17}, [r0:128]
+; CHECK-NEXT:    bx lr
 entry:
   %.sink = select i1 %dec1, <3 x i64> %b, <3 x i64> zeroinitializer
   %.sink15 = select i1 %dec0, <3 x i64> %b, <3 x i64> zeroinitializer