Index: llvm/trunk/tools/llvm-mca/Backend.cpp
===================================================================
--- llvm/trunk/tools/llvm-mca/Backend.cpp
+++ llvm/trunk/tools/llvm-mca/Backend.cpp
@@ -38,6 +38,9 @@
   notifyCycleBegin(Cycle);
 
   InstRef IR;
+  Dispatch->preExecute(IR);
+  HWS->cycleEvent(); // TODO: This will eventually be stage-ified.
+
   while (Fetch->execute(IR)) {
     if (!Dispatch->execute(IR))
       break;
@@ -51,9 +54,6 @@
   LLVM_DEBUG(dbgs() << "[E] Cycle begin: " << Cycle << '\n');
   for (HWEventListener *Listener : Listeners)
     Listener->onCycleBegin();
-
-  Dispatch->cycleEvent();
-  HWS->cycleEvent();
 }
 
 void Backend::notifyInstructionEvent(const HWInstructionEvent &Event) {
Index: llvm/trunk/tools/llvm-mca/DispatchStage.h
===================================================================
--- llvm/trunk/tools/llvm-mca/DispatchStage.h
+++ llvm/trunk/tools/llvm-mca/DispatchStage.h
@@ -98,14 +98,8 @@
                                                  this)),
         Owner(B), STI(Subtarget) {}
 
-  void cycleEvent() {
-    RCU->cycleEvent();
-    AvailableEntries =
-        CarryOver >= DispatchWidth ? 0 : DispatchWidth - CarryOver;
-    CarryOver = CarryOver >= DispatchWidth ? CarryOver - DispatchWidth : 0U;
-  }
-
   virtual bool isReady() const override final { return isRCUEmpty(); }
+  virtual void preExecute(const InstRef &IR) override final;
   virtual bool execute(InstRef &IR) override final;
   void notifyInstructionRetired(const InstRef &IR);
   void notifyDispatchStall(const InstRef &IR, unsigned EventType);
Index: llvm/trunk/tools/llvm-mca/DispatchStage.cpp
===================================================================
--- llvm/trunk/tools/llvm-mca/DispatchStage.cpp
+++ llvm/trunk/tools/llvm-mca/DispatchStage.cpp
@@ -142,6 +142,12 @@
   SC->scheduleInstruction(IR);
 }
 
+void DispatchStage::preExecute(const InstRef &IR) {
+  RCU->cycleEvent();
+  AvailableEntries = CarryOver >= DispatchWidth ? 0 : DispatchWidth - CarryOver;
+  CarryOver = CarryOver >= DispatchWidth ? CarryOver - DispatchWidth : 0U;
+}
+
 bool DispatchStage::execute(InstRef &IR) {
   const InstrDesc &Desc = IR.getInstruction()->getDesc();
   if (!isAvailable(Desc.NumMicroOps) || !canDispatch(IR))