Index: lib/Target/AMDGPU/BUFInstructions.td
===================================================================
--- lib/Target/AMDGPU/BUFInstructions.td
+++ lib/Target/AMDGPU/BUFInstructions.td
@@ -209,6 +209,7 @@
   let PseudoInstr = opName # "_" # getAddrName<addrKindCopy>.ret;
   let mayLoad = 1;
   let mayStore = 0;
+  let IsAddr64 = !if(addr64, 1, 0);
 }
 
 multiclass MTBUF_Pseudo_Loads<string opName, RegisterClass vdataClass,
@@ -255,6 +256,7 @@
   let PseudoInstr = opName # "_" # getAddrName<addrKindCopy>.ret;
   let mayLoad = 0;
   let mayStore = 1;
+  let IsAddr64 = !if(addr64, 1, 0);
 }
 
 multiclass MTBUF_Pseudo_Stores<string opName, RegisterClass vdataClass,
@@ -458,6 +460,7 @@
   let Uses = !if(isLds, [EXEC, M0], [EXEC]);
   let has_tfe = !if(isLds, 0, 1);
   let lds = isLds;
+  let IsAddr64 = !if(addr64, 1, 0);
 }
 
 // FIXME: tfe can't be an operand because it requires a separate
@@ -521,6 +524,7 @@
   let mayLoad = 0;
   let mayStore = 1;
   let maybeAtomic = 1;
+  let IsAddr64 = !if(addr64, 1, 0);
 }
 
 multiclass MUBUF_Pseudo_Stores<string opName, RegisterClass vdataClass,
Index: lib/Target/AMDGPU/SIDefines.h
===================================================================
--- lib/Target/AMDGPU/SIDefines.h
+++ lib/Target/AMDGPU/SIDefines.h
@@ -88,7 +88,11 @@
   IsPacked = UINT64_C(1) << 49,
 
   // "d16" bit set or not.
-  D16 = UINT64_C(1) << 50
+  D16 = UINT64_C(1) << 50,
+
+  // Is MUBUF/MTBUF in addr64 mode.
+  IsAddr64 = UINT64_C(1) << 51
+
 };
 
 // v_cmp_class_* etc. use a 10-bit mask for what operation is checked.
Index: lib/Target/AMDGPU/SIInstrFormats.td
===================================================================
--- lib/Target/AMDGPU/SIInstrFormats.td
+++ lib/Target/AMDGPU/SIInstrFormats.td
@@ -121,6 +121,9 @@
   // This bit indicates that this is a D16 instruction.
   field bit D16 = 0;
 
+  // This bit indicates that an MUBUF/MTBUF instruction is addr64.
+  field bit IsAddr64 = 0;
+
   // These need to be kept in sync with the enum in SIInstrFlags.
   let TSFlags{0} = SALU;
   let TSFlags{1} = VALU;
@@ -177,6 +180,7 @@
   let TSFlags{49} = IsPacked;
 
   let TSFlags{50} = D16;
+  let TSFlags{51} = IsAddr64;
 
   let SchedRW = [Write32Bit];
 
Index: lib/Target/AMDGPU/SIInstrInfo.h
===================================================================
--- lib/Target/AMDGPU/SIInstrInfo.h
+++ lib/Target/AMDGPU/SIInstrInfo.h
@@ -470,6 +470,10 @@
     return MI.getDesc().TSFlags & SIInstrFlags::FLAT;
   }
 
+  static bool isAddr64(const MachineInstr &MI) {
+    return MI.getDesc().TSFlags & SIInstrFlags::IsAddr64;
+  }
+
   // Is a FLAT encoded instruction which accesses a specific segment,
   // i.e. global_* or scratch_*.
   static bool isSegmentSpecificFLAT(const MachineInstr &MI) {
Index: lib/Target/AMDGPU/SIInstrInfo.cpp
===================================================================
--- lib/Target/AMDGPU/SIInstrInfo.cpp
+++ lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -3660,12 +3660,13 @@
 
   // Legalize MIMG and MUBUF/MTBUF for shaders.
   //
-  // Shaders only generate MUBUF/MTBUF instructions via intrinsics or via
-  // scratch memory access. In both cases, the legalization never involves
-  // conversion to the addr64 form.
+  // Shaders only generate non-addr64 MUBUF/MTBUF instructions via intrinsics
+  // or via scratch memory access. In both cases, the legalization never
+  // involves conversion to the addr64 form.
   if (isMIMG(MI) ||
       (AMDGPU::isShader(MF.getFunction().getCallingConv()) &&
-       (isMUBUF(MI) || isMTBUF(MI)))) {
+       (isMUBUF(MI) || isMTBUF(MI))
+       && !isAddr64(MI))) {
     MachineOperand *SRsrc = getNamedOperand(MI, AMDGPU::OpName::srsrc);
     if (SRsrc && !RI.isSGPRClass(MRI.getRegClass(SRsrc->getReg()))) {
       unsigned SGPR = readlaneVGPRToSGPR(SRsrc->getReg(), MI, MRI);
Index: test/CodeGen/AMDGPU/shader-addr64-nonuniform.ll
===================================================================
--- /dev/null
+++ test/CodeGen/AMDGPU/shader-addr64-nonuniform.ll
@@ -0,0 +1,17 @@
+; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx700 -verify-machineinstrs <%s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SICI %s
+
+; GCN-LABEL: {{^}}main:
+; GCN-NOT: readfirstlane
+; SICI: buffer_load_dwordx4 {{.*}} addr64
+
+@indexable = internal unnamed_addr addrspace(1) constant [6 x <3 x float>] [<3 x float> <float 1.000000e+00, float 0.000000e+00, float 0.000000e+00>, <3 x float> <float 0.000000e+00, float 1.000000e+00, float 0.000000e+00>, <3 x float> <float 0.000000e+00, float 0.000000e+00, float 1.000000e+00>, <3 x float> <float 0.000000e+00, float 1.000000e+00, float 1.000000e+00>, <3 x float> <float 1.000000e+00, float 0.000000e+00, float 1.000000e+00>, <3 x float> <float 1.000000e+00, float 1.000000e+00, float 0.000000e+00>]
+
+define amdgpu_ps float @main(i32 %arg18) {
+.entry:
+  %tmp31 = sext i32 %arg18 to i64
+  %tmp32 = getelementptr [6 x <3 x float>], [6 x <3 x float>] addrspace(1)* @indexable, i64 0, i64 %tmp31
+  %tmp33 = load <3 x float>, <3 x float> addrspace(1)* %tmp32, align 16
+  %tmp34 = extractelement <3 x float> %tmp33, i32 0
+  ret float %tmp34
+}
+