Index: lib/Target/RISCV/RISCVRegisterInfo.td =================================================================== --- lib/Target/RISCV/RISCVRegisterInfo.td +++ lib/Target/RISCV/RISCVRegisterInfo.td @@ -38,8 +38,16 @@ } // Namespace = "RISCV" // Integer registers +// CostPerUse is set higher for registers that may not be compressible as they +// are not part of GPRC, the most restrictive register class used by the +// compressed instruction set. This will influence the greedy register +// allocator to reduce the use of registers that can't be encoded in 16 bit +// instructions. This affects register allocation even when compressed +// instruction isn't targeted, we see no major negative codegen impact. + let RegAltNameIndices = [ABIRegAltName] in { def X0 : RISCVReg<0, "x0", ["zero"]>, DwarfRegNum<[0]>; + let CostPerUse = 1 in { def X1 : RISCVReg<1, "x1", ["ra"]>, DwarfRegNum<[1]>; def X2 : RISCVReg<2, "x2", ["sp"]>, DwarfRegNum<[2]>; def X3 : RISCVReg<3, "x3", ["gp"]>, DwarfRegNum<[3]>; @@ -47,6 +55,7 @@ def X5 : RISCVReg<5, "x5", ["t0"]>, DwarfRegNum<[5]>; def X6 : RISCVReg<6, "x6", ["t1"]>, DwarfRegNum<[6]>; def X7 : RISCVReg<7, "x7", ["t2"]>, DwarfRegNum<[7]>; + } def X8 : RISCVReg<8, "x8", ["s0"]>, DwarfRegNum<[8]>; def X9 : RISCVReg<9, "x9", ["s1"]>, DwarfRegNum<[9]>; def X10 : RISCVReg<10,"x10", ["a0"]>, DwarfRegNum<[10]>; @@ -55,6 +64,7 @@ def X13 : RISCVReg<13,"x13", ["a3"]>, DwarfRegNum<[13]>; def X14 : RISCVReg<14,"x14", ["a4"]>, DwarfRegNum<[14]>; def X15 : RISCVReg<15,"x15", ["a5"]>, DwarfRegNum<[15]>; + let CostPerUse = 1 in { def X16 : RISCVReg<16,"x16", ["a6"]>, DwarfRegNum<[16]>; def X17 : RISCVReg<17,"x17", ["a7"]>, DwarfRegNum<[17]>; def X18 : RISCVReg<18,"x18", ["s2"]>, DwarfRegNum<[18]>; @@ -71,6 +81,7 @@ def X29 : RISCVReg<29,"x29", ["t4"]>, DwarfRegNum<[29]>; def X30 : RISCVReg<30,"x30", ["t5"]>, DwarfRegNum<[30]>; def X31 : RISCVReg<31,"x31", ["t6"]>, DwarfRegNum<[31]>; + } } def XLenVT : ValueTypeByHwMode<[RV32, RV64, DefaultMode], Index: test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll =================================================================== --- test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll +++ test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll @@ -264,10 +264,10 @@ ; RV32I-NEXT: sw s5, 8(sp) ; RV32I-NEXT: sw s6, 4(sp) ; RV32I-NEXT: sw s7, 0(sp) -; RV32I-NEXT: mv s2, a1 -; RV32I-NEXT: mv s3, a0 +; RV32I-NEXT: mv s3, a1 +; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: addi a0, a0, -1 -; RV32I-NEXT: not a1, s3 +; RV32I-NEXT: not a1, s4 ; RV32I-NEXT: and a0, a1, a0 ; RV32I-NEXT: lui a1, 349525 ; RV32I-NEXT: addi s5, a1, 1365 @@ -275,43 +275,43 @@ ; RV32I-NEXT: and a1, a1, s5 ; RV32I-NEXT: sub a0, a0, a1 ; RV32I-NEXT: lui a1, 209715 -; RV32I-NEXT: addi s6, a1, 819 -; RV32I-NEXT: and a1, a0, s6 +; RV32I-NEXT: addi s1, a1, 819 +; RV32I-NEXT: and a1, a0, s1 ; RV32I-NEXT: srli a0, a0, 2 -; RV32I-NEXT: and a0, a0, s6 +; RV32I-NEXT: and a0, a0, s1 ; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: lui a1, 4112 -; RV32I-NEXT: addi s4, a1, 257 +; RV32I-NEXT: addi s6, a1, 257 ; RV32I-NEXT: lui a1, 61681 ; RV32I-NEXT: addi s7, a1, -241 ; RV32I-NEXT: and a0, a0, s7 -; RV32I-NEXT: mv a1, s4 +; RV32I-NEXT: mv a1, s6 ; RV32I-NEXT: call __mulsi3 -; RV32I-NEXT: mv s1, a0 -; RV32I-NEXT: addi a0, s2, -1 -; RV32I-NEXT: not a1, s2 +; RV32I-NEXT: mv s2, a0 +; RV32I-NEXT: addi a0, s3, -1 +; RV32I-NEXT: not a1, s3 ; RV32I-NEXT: and a0, a1, a0 ; RV32I-NEXT: srli a1, a0, 1 ; RV32I-NEXT: and a1, a1, s5 ; RV32I-NEXT: sub a0, a0, a1 -; RV32I-NEXT: and a1, a0, s6 +; RV32I-NEXT: and a1, a0, s1 ; RV32I-NEXT: srli a0, a0, 2 -; RV32I-NEXT: and a0, a0, s6 +; RV32I-NEXT: and a0, a0, s1 ; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: and a0, a0, s7 -; RV32I-NEXT: mv a1, s4 +; RV32I-NEXT: mv a1, s6 ; RV32I-NEXT: call __mulsi3 -; RV32I-NEXT: bnez s3, .LBB7_2 +; RV32I-NEXT: bnez s4, .LBB7_2 ; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: addi a0, a0, 32 ; RV32I-NEXT: j .LBB7_3 ; RV32I-NEXT: .LBB7_2: -; RV32I-NEXT: srli a0, s1, 24 +; RV32I-NEXT: srli a0, s2, 24 ; RV32I-NEXT: .LBB7_3: ; RV32I-NEXT: mv a1, zero ; RV32I-NEXT: lw s7, 0(sp) @@ -445,10 +445,10 @@ ; RV32I-NEXT: sw s5, 8(sp) ; RV32I-NEXT: sw s6, 4(sp) ; RV32I-NEXT: sw s7, 0(sp) -; RV32I-NEXT: mv s2, a1 -; RV32I-NEXT: mv s3, a0 +; RV32I-NEXT: mv s3, a1 +; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: addi a0, a0, -1 -; RV32I-NEXT: not a1, s3 +; RV32I-NEXT: not a1, s4 ; RV32I-NEXT: and a0, a1, a0 ; RV32I-NEXT: lui a1, 349525 ; RV32I-NEXT: addi s5, a1, 1365 @@ -456,43 +456,43 @@ ; RV32I-NEXT: and a1, a1, s5 ; RV32I-NEXT: sub a0, a0, a1 ; RV32I-NEXT: lui a1, 209715 -; RV32I-NEXT: addi s6, a1, 819 -; RV32I-NEXT: and a1, a0, s6 +; RV32I-NEXT: addi s1, a1, 819 +; RV32I-NEXT: and a1, a0, s1 ; RV32I-NEXT: srli a0, a0, 2 -; RV32I-NEXT: and a0, a0, s6 +; RV32I-NEXT: and a0, a0, s1 ; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: lui a1, 4112 -; RV32I-NEXT: addi s4, a1, 257 +; RV32I-NEXT: addi s6, a1, 257 ; RV32I-NEXT: lui a1, 61681 ; RV32I-NEXT: addi s7, a1, -241 ; RV32I-NEXT: and a0, a0, s7 -; RV32I-NEXT: mv a1, s4 +; RV32I-NEXT: mv a1, s6 ; RV32I-NEXT: call __mulsi3 -; RV32I-NEXT: mv s1, a0 -; RV32I-NEXT: addi a0, s2, -1 -; RV32I-NEXT: not a1, s2 +; RV32I-NEXT: mv s2, a0 +; RV32I-NEXT: addi a0, s3, -1 +; RV32I-NEXT: not a1, s3 ; RV32I-NEXT: and a0, a1, a0 ; RV32I-NEXT: srli a1, a0, 1 ; RV32I-NEXT: and a1, a1, s5 ; RV32I-NEXT: sub a0, a0, a1 -; RV32I-NEXT: and a1, a0, s6 +; RV32I-NEXT: and a1, a0, s1 ; RV32I-NEXT: srli a0, a0, 2 -; RV32I-NEXT: and a0, a0, s6 +; RV32I-NEXT: and a0, a0, s1 ; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: and a0, a0, s7 -; RV32I-NEXT: mv a1, s4 +; RV32I-NEXT: mv a1, s6 ; RV32I-NEXT: call __mulsi3 -; RV32I-NEXT: bnez s3, .LBB11_2 +; RV32I-NEXT: bnez s4, .LBB11_2 ; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: addi a0, a0, 32 ; RV32I-NEXT: j .LBB11_3 ; RV32I-NEXT: .LBB11_2: -; RV32I-NEXT: srli a0, s1, 24 +; RV32I-NEXT: srli a0, s2, 24 ; RV32I-NEXT: .LBB11_3: ; RV32I-NEXT: mv a1, zero ; RV32I-NEXT: lw s7, 0(sp) Index: test/CodeGen/RISCV/calling-conv.ll =================================================================== --- test/CodeGen/RISCV/calling-conv.ll +++ test/CodeGen/RISCV/calling-conv.ll @@ -19,16 +19,16 @@ ; RV32I-FPELIM-NEXT: sw s2, 20(sp) ; RV32I-FPELIM-NEXT: sw s3, 16(sp) ; RV32I-FPELIM-NEXT: sw s4, 12(sp) -; RV32I-FPELIM-NEXT: mv s1, a4 -; RV32I-FPELIM-NEXT: mv s2, a3 -; RV32I-FPELIM-NEXT: mv s3, a1 -; RV32I-FPELIM-NEXT: mv s4, a0 +; RV32I-FPELIM-NEXT: mv s2, a4 +; RV32I-FPELIM-NEXT: mv s3, a3 +; RV32I-FPELIM-NEXT: mv s4, a1 +; RV32I-FPELIM-NEXT: mv s1, a0 ; RV32I-FPELIM-NEXT: mv a0, a5 ; RV32I-FPELIM-NEXT: mv a1, a6 ; RV32I-FPELIM-NEXT: call __fixdfsi -; RV32I-FPELIM-NEXT: add a1, s4, s3 +; RV32I-FPELIM-NEXT: add a1, s1, s4 +; RV32I-FPELIM-NEXT: add a1, a1, s3 ; RV32I-FPELIM-NEXT: add a1, a1, s2 -; RV32I-FPELIM-NEXT: add a1, a1, s1 ; RV32I-FPELIM-NEXT: add a0, a1, a0 ; RV32I-FPELIM-NEXT: lw s4, 12(sp) ; RV32I-FPELIM-NEXT: lw s3, 16(sp) @@ -48,16 +48,16 @@ ; RV32I-WITHFP-NEXT: sw s3, 12(sp) ; RV32I-WITHFP-NEXT: sw s4, 8(sp) ; RV32I-WITHFP-NEXT: addi s0, sp, 32 -; RV32I-WITHFP-NEXT: mv s1, a4 -; RV32I-WITHFP-NEXT: mv s2, a3 -; RV32I-WITHFP-NEXT: mv s3, a1 -; RV32I-WITHFP-NEXT: mv s4, a0 +; RV32I-WITHFP-NEXT: mv s2, a4 +; RV32I-WITHFP-NEXT: mv s3, a3 +; RV32I-WITHFP-NEXT: mv s4, a1 +; RV32I-WITHFP-NEXT: mv s1, a0 ; RV32I-WITHFP-NEXT: mv a0, a5 ; RV32I-WITHFP-NEXT: mv a1, a6 ; RV32I-WITHFP-NEXT: call __fixdfsi -; RV32I-WITHFP-NEXT: add a1, s4, s3 +; RV32I-WITHFP-NEXT: add a1, s1, s4 +; RV32I-WITHFP-NEXT: add a1, a1, s3 ; RV32I-WITHFP-NEXT: add a1, a1, s2 -; RV32I-WITHFP-NEXT: add a1, a1, s1 ; RV32I-WITHFP-NEXT: add a0, a1, a0 ; RV32I-WITHFP-NEXT: lw s4, 8(sp) ; RV32I-WITHFP-NEXT: lw s3, 12(sp) Index: test/CodeGen/RISCV/double-mem.ll =================================================================== --- test/CodeGen/RISCV/double-mem.ll +++ test/CodeGen/RISCV/double-mem.ll @@ -116,12 +116,12 @@ ; RV32IFD-NEXT: sw ra, 28(sp) ; RV32IFD-NEXT: sw s1, 24(sp) ; RV32IFD-NEXT: sw s2, 20(sp) -; RV32IFD-NEXT: mv s1, a1 -; RV32IFD-NEXT: mv s2, a0 +; RV32IFD-NEXT: mv s2, a1 +; RV32IFD-NEXT: mv s1, a0 ; RV32IFD-NEXT: addi a0, sp, 8 ; RV32IFD-NEXT: call notdead -; RV32IFD-NEXT: sw s2, 0(sp) -; RV32IFD-NEXT: sw s1, 4(sp) +; RV32IFD-NEXT: sw s1, 0(sp) +; RV32IFD-NEXT: sw s2, 4(sp) ; RV32IFD-NEXT: fld ft0, 0(sp) ; RV32IFD-NEXT: fld ft1, 8(sp) ; RV32IFD-NEXT: fadd.d ft0, ft1, ft0 Index: test/CodeGen/RISCV/remat.ll =================================================================== --- test/CodeGen/RISCV/remat.ll +++ test/CodeGen/RISCV/remat.ll @@ -45,9 +45,9 @@ ; RV32I-NEXT: lui s7, %hi(i) ; RV32I-NEXT: lui s9, %hi(g) ; RV32I-NEXT: lui s10, %hi(f) -; RV32I-NEXT: lui s11, %hi(e) +; RV32I-NEXT: lui s1, %hi(e) ; RV32I-NEXT: lui s8, %hi(d) -; RV32I-NEXT: addi s1, zero, 32 +; RV32I-NEXT: addi s11, zero, 32 ; RV32I-NEXT: lui s2, %hi(c) ; RV32I-NEXT: lui s4, %hi(b) ; RV32I-NEXT: .LBB0_2: # %for.body @@ -57,11 +57,11 @@ ; RV32I-NEXT: beqz a1, .LBB0_4 ; RV32I-NEXT: # %bb.3: # %if.then ; RV32I-NEXT: # in Loop: Header=BB0_2 Depth=1 -; RV32I-NEXT: lw a4, %lo(e)(s11) +; RV32I-NEXT: lw a4, %lo(e)(s1) ; RV32I-NEXT: lw a3, %lo(d)(s8) ; RV32I-NEXT: lw a2, %lo(c)(s2) ; RV32I-NEXT: lw a1, %lo(b)(s4) -; RV32I-NEXT: mv a5, s1 +; RV32I-NEXT: mv a5, s11 ; RV32I-NEXT: call foo ; RV32I-NEXT: .LBB0_4: # %if.end ; RV32I-NEXT: # in Loop: Header=BB0_2 Depth=1 @@ -70,7 +70,7 @@ ; RV32I-NEXT: # %bb.5: # %if.then3 ; RV32I-NEXT: # in Loop: Header=BB0_2 Depth=1 ; RV32I-NEXT: lw a4, %lo(f)(s10) -; RV32I-NEXT: lw a3, %lo(e)(s11) +; RV32I-NEXT: lw a3, %lo(e)(s1) ; RV32I-NEXT: lw a2, %lo(d)(s8) ; RV32I-NEXT: lw a1, %lo(c)(s2) ; RV32I-NEXT: lw a0, %lo(b)(s4) @@ -84,10 +84,10 @@ ; RV32I-NEXT: # in Loop: Header=BB0_2 Depth=1 ; RV32I-NEXT: lw a4, %lo(g)(s9) ; RV32I-NEXT: lw a3, %lo(f)(s10) -; RV32I-NEXT: lw a2, %lo(e)(s11) +; RV32I-NEXT: lw a2, %lo(e)(s1) ; RV32I-NEXT: lw a1, %lo(d)(s8) ; RV32I-NEXT: lw a0, %lo(c)(s2) -; RV32I-NEXT: mv a5, s1 +; RV32I-NEXT: mv a5, s11 ; RV32I-NEXT: call foo ; RV32I-NEXT: .LBB0_8: # %if.end9 ; RV32I-NEXT: # in Loop: Header=BB0_2 Depth=1 @@ -99,9 +99,9 @@ ; RV32I-NEXT: lw a4, %lo(h)(a0) ; RV32I-NEXT: lw a3, %lo(g)(s9) ; RV32I-NEXT: lw a2, %lo(f)(s10) -; RV32I-NEXT: lw a1, %lo(e)(s11) +; RV32I-NEXT: lw a1, %lo(e)(s1) ; RV32I-NEXT: lw a0, %lo(d)(s8) -; RV32I-NEXT: mv a5, s1 +; RV32I-NEXT: mv a5, s11 ; RV32I-NEXT: call foo ; RV32I-NEXT: .LBB0_10: # %for.inc ; RV32I-NEXT: # in Loop: Header=BB0_2 Depth=1