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Differential D4685

R600/SI: Make argument loads invariant
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Authored by arsenm on Jul 26 2014, 3:26 PM.

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arsenm

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arsenm updated this revision to Diff 11918.Jul 26 2014, 3:26 PM
arsenm retitled this revision from to R600/SI: Make argument loads invariant .
arsenm updated this object.
arsenm edited the test plan for this revision. (Show Details)
arsenm added a subscriber: Unknown Object (MLST).
arsenm accepted this revision.Jul 28 2014, 10:44 AM
arsenm added a reviewer: arsenm.

r214101

This revision is now accepted and ready to land.Jul 28 2014, 10:44 AM
arsenm closed this revision.Jul 28 2014, 10:44 AM

Revision Contents

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lib/
Target/
R600/
26 lines

Diff 11918

lib/Target/R600/SIISelLowering.cpp

Context not available.
} }
SDValue SITargetLowering::LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT, SDValue SITargetLowering::LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
SDLoc DL, SDValue Chain, SDLoc SL, SDValue Chain,
unsigned Offset, bool Signed) const { unsigned Offset, bool Signed) const {
const DataLayout *DL = getDataLayout();
Type *Ty = VT.getTypeForEVT(*DAG.getContext());
MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
PointerType *PtrTy = PointerType::get(VT.getTypeForEVT(*DAG.getContext()), PointerType *PtrTy = PointerType::get(Ty, AMDGPUAS::CONSTANT_ADDRESS);
AMDGPUAS::CONSTANT_ADDRESS); SDValue BasePtr = DAG.getCopyFromReg(Chain, SL,
SDValue BasePtr = DAG.getCopyFromReg(Chain, DL,
MRI.getLiveInVirtReg(AMDGPU::SGPR0_SGPR1), MVT::i64); MRI.getLiveInVirtReg(AMDGPU::SGPR0_SGPR1), MVT::i64);
SDValue Ptr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr, SDValue Ptr = DAG.getNode(ISD::ADD, SL, MVT::i64, BasePtr,
DAG.getConstant(Offset, MVT::i64)); DAG.getConstant(Offset, MVT::i64));
return DAG.getExtLoad(Signed ? ISD::SEXTLOAD : ISD::ZEXTLOAD, DL, VT, Chain, Ptr, SDValue PtrOffset = DAG.getUNDEF(getPointerTy(AMDGPUAS::CONSTANT_ADDRESS));
MachinePointerInfo(UndefValue::get(PtrTy)), MemVT, MachinePointerInfo PtrInfo(UndefValue::get(PtrTy));
false, false, MemVT.getSizeInBits() >> 3);
return DAG.getLoad(ISD::UNINDEXED, Signed ? ISD::SEXTLOAD : ISD::ZEXTLOAD,
VT, SL, Chain, Ptr, PtrOffset, PtrInfo, MemVT,
false, // isVolatile
true, // isNonTemporal
true, // isInvariant
DL->getABITypeAlignment(Ty)); // Alignment
} }
SDValue SITargetLowering::LowerFormalArguments( SDValue SITargetLowering::LowerFormalArguments(
Context not available.