Index: llvm/lib/Target/X86/X86InstrInfo.cpp
===================================================================
--- llvm/lib/Target/X86/X86InstrInfo.cpp
+++ llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -5903,6 +5903,10 @@
   default: return X86::COND_INVALID;
   case X86::SETAr:  case X86::SETAm:  return X86::COND_A;
   case X86::SETAEr: case X86::SETAEm: return X86::COND_AE;
+  case X86::SETB_C8r:
+  case X86::SETB_C16r:
+  case X86::SETB_C32r:
+  case X86::SETB_C64r:
   case X86::SETBr:  case X86::SETBm:  return X86::COND_B;
   case X86::SETBEr: case X86::SETBEm: return X86::COND_BE;
   case X86::SETEr:  case X86::SETEm:  return X86::COND_E;
Index: llvm/test/CodeGen/X86/copy-eflags.ll
===================================================================
--- llvm/test/CodeGen/X86/copy-eflags.ll
+++ llvm/test/CodeGen/X86/copy-eflags.ll
@@ -304,3 +304,21 @@
   %tmp12 = trunc i32 %tmp11 to i16
   br label %bb1
 }
+
+; Use a particular instruction pattern in order to lower to the post-RA pseudo
+; used to lower SETB into an SBB pattern in order to make sure that kind of
+; usage of a copied EFLAGS continues to work.
+define void @PR37431(i32* %arg1, i8* %arg2, i8* %arg3) {
+entry:
+  %tmp = load i32, i32* %arg1
+  %tmp1 = sext i32 %tmp to i64
+  %tmp2 = icmp ugt i64 %tmp1, undef
+  %tmp3 = zext i1 %tmp2 to i8
+  %tmp4 = sub i8 0, %tmp3
+  store i8 %tmp4, i8* %arg2
+  %tmp5 = sext i8 %tmp4 to i32
+  %tmp6 = srem i32 0, %tmp5
+  %tmp7 = trunc i32 %tmp6 to i8
+  store i8 %tmp7, i8* %arg3
+  ret void
+}
\ No newline at end of file