Index: lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp =================================================================== --- lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -7,10 +7,10 @@ // //===----------------------------------------------------------------------===// -#include "MCTargetDesc/RISCVBaseInfo.h" #include "MCTargetDesc/RISCVMCExpr.h" #include "MCTargetDesc/RISCVMCTargetDesc.h" #include "MCTargetDesc/RISCVTargetStreamer.h" +#include "Utils/RISCVBaseInfo.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/StringSwitch.h" #include "llvm/MC/MCContext.h" @@ -83,13 +83,15 @@ #define GET_ASSEMBLER_HEADER #include "RISCVGenAsmMatcher.inc" + OperandMatchResultTy parseCSRSystemRegister(OperandVector &Operands); OperandMatchResultTy parseImmediate(OperandVector &Operands); OperandMatchResultTy parseRegister(OperandVector &Operands, bool AllowParens = false); OperandMatchResultTy parseMemOpBaseReg(OperandVector &Operands); OperandMatchResultTy parseOperandWithModifier(OperandVector &Operands); - bool parseOperand(OperandVector &Operands, bool ForceImmediate); + bool parseOperand(OperandVector &Operands, bool ForceImmediate, + StringRef Mnemonic); bool parseDirectiveOption(); @@ -139,6 +141,7 @@ Token, Register, Immediate, + SystemRegister } Kind; bool IsRV64; @@ -151,11 +154,20 @@ const MCExpr *Val; }; + struct SysRegOp { + const char *Data; + unsigned Length; + unsigned Encoding; + // FIXME: Add the Encoding parsed fields as needed for checks, + // e.g.: read/write or user/supervisor/machine privileges. + }; + SMLoc StartLoc, EndLoc; union { StringRef Tok; RegOp Reg; ImmOp Imm; + struct SysRegOp SysReg; }; RISCVOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {} @@ -176,6 +188,9 @@ case Token: Tok = o.Tok; break; + case SystemRegister: + SysReg = o.SysReg; + break; } } @@ -183,6 +198,7 @@ bool isReg() const override { return Kind == Register; } bool isImm() const override { return Kind == Immediate; } bool isMem() const override { return false; } + bool isSystemRegister() const { return Kind == SystemRegister; } bool evaluateConstantImm(int64_t &Imm, RISCVMCExpr::VariantKind &VK) const { const MCExpr *Val = getImm(); @@ -226,6 +242,10 @@ VK == RISCVMCExpr::VK_RISCV_None; } + bool isCSRSystemRegister() const { + return isSystemRegister(); + } + /// Return true if the operand is a valid for the fence instruction e.g. /// ('iorw'). bool isFenceArg() const { @@ -462,6 +482,11 @@ return Reg.RegNum; } + StringRef getSysReg() const { + assert(Kind == SystemRegister && "Invalid access!"); + return StringRef(SysReg.Data, SysReg.Length); + } + const MCExpr *getImm() const { assert(Kind == Immediate && "Invalid type access!"); return Imm.Val; @@ -484,6 +509,9 @@ case Token: OS << "'" << getToken() << "'"; break; + case SystemRegister: + OS << "'; + break; } } @@ -517,6 +545,18 @@ return Op; } + static std::unique_ptr createSysReg(StringRef Str, SMLoc S, + unsigned Encoding, + bool IsRV64) { + auto Op = make_unique(SystemRegister); + Op->SysReg.Data = Str.data(); + Op->SysReg.Length = Str.size(); + Op->SysReg.Encoding = Encoding; + Op->StartLoc = S; + Op->IsRV64 = IsRV64; + return Op; + } + void addExpr(MCInst &Inst, const MCExpr *Expr) const { assert(Expr && "Expr shouldn't be null!"); int64_t Imm = 0; @@ -563,6 +603,11 @@ Inst.addOperand(MCOperand::createImm(Imm)); } + void addCSRSystemRegisterOperands(MCInst &Inst, unsigned N) const { + assert(N == 1 && "Invalid number of operands!"); + Inst.addOperand(MCOperand::createImm(SysReg.Encoding)); + } + // Returns the rounding mode represented by this RISCVOperand. Should only // be called after checking isFRMArg. RISCVFPRndMode::RoundingMode getRoundingMode() const { @@ -760,6 +805,11 @@ return generateImmOutOfRangeError( Operands, ErrorInfo, -(1 << 20), (1 << 20) - 2, "immediate must be a multiple of 2 bytes in the range"); + case Match_InvalidCSRSystemRegister: { + return generateImmOutOfRangeError( + Operands, ErrorInfo, 0, (1 << 12) - 1, + "operand must be a valid system register name or an integer in the range"); + } case Match_InvalidFenceArg: { SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc(); return Error( @@ -842,6 +892,66 @@ return MatchOperand_Success; } +OperandMatchResultTy RISCVAsmParser::parseCSRSystemRegister( + OperandVector &Operands) { + SMLoc S = getLoc(); + const MCExpr *Res; + + switch (getLexer().getKind()) { + default: + return MatchOperand_NoMatch; + case AsmToken::LParen: + case AsmToken::Minus: + case AsmToken::Plus: + case AsmToken::Integer: + case AsmToken::String: { + if (getParser().parseExpression(Res)) + return MatchOperand_ParseFail; + + auto *CE = dyn_cast(Res); + if (CE) { + int64_t Imm = CE->getValue(); + if (isUInt<12>(Imm)) { + auto SysReg = RISCVSysReg::lookupSysRegByEncoding(CE->getValue()); + // Accept a name or un-named Sys Reg if the range is valid. + Operands.push_back(RISCVOperand::createSysReg( + SysReg ? SysReg->Name : "", S, Imm, isRV64())); + return MatchOperand_Success; + } + } + + Twine Msg = "immediate must be an integer in the range"; + Error(S, Msg + " [" + Twine(0) + ", " + Twine((1 << 12) - 1) + "]"); + return MatchOperand_ParseFail; + } + case AsmToken::Identifier: { + StringRef Identifier; + if (getParser().parseIdentifier(Identifier)) + return MatchOperand_ParseFail; + + auto SysReg = RISCVSysReg::lookupSysRegByName(Identifier); + if (SysReg) { + Operands.push_back(RISCVOperand::createSysReg( + Identifier, S, SysReg->Encoding, isRV64())); + return MatchOperand_Success; + } + + Twine Msg = "operand must be a valid system register name " + "or an integer in the range"; + Error(S, Msg + " [" + Twine(0) + ", " + Twine((1 << 12) - 1) + "]"); + return MatchOperand_ParseFail; + } + case AsmToken::Percent: { + // Discard operand with modifier. + Twine Msg = "immediate must be an integer in the range"; + Error(S, Msg + " [" + Twine(0) + ", " + Twine((1 << 12) - 1) + "]"); + return MatchOperand_ParseFail; + } + } + + return MatchOperand_NoMatch; +} + OperandMatchResultTy RISCVAsmParser::parseImmediate(OperandVector &Operands) { SMLoc S = getLoc(); SMLoc E = SMLoc::getFromPointer(S.getPointer() - 1); @@ -946,7 +1056,19 @@ /// operand as a register, which is needed for pseudoinstructions such as /// call. bool RISCVAsmParser::parseOperand(OperandVector &Operands, - bool ForceImmediate) { + bool ForceImmediate, + StringRef Mnemonic) { + // Check if the current operand has a custom associated parser, if so, try to + // custom parse the operand, or fallback to the general approach. + + OperandMatchResultTy Result = + MatchOperandParserImpl(Operands, Mnemonic, /*ParseForAllFeatures=*/ true); + + if (Result == MatchOperand_Success) + return false; + if (Result == MatchOperand_ParseFail) { + return true; + } // Attempt to parse token as register, unless ForceImmediate. if (!ForceImmediate && parseRegister(Operands, true) == MatchOperand_Success) return false; @@ -976,7 +1098,7 @@ // Parse first operand bool ForceImmediate = (Name == "call" || Name == "tail"); - if (parseOperand(Operands, ForceImmediate)) + if (parseOperand(Operands, ForceImmediate, Name)) return true; // Parse until end of statement, consuming commas between operands @@ -985,7 +1107,7 @@ getLexer().Lex(); // Parse next operand - if (parseOperand(Operands, false)) + if (parseOperand(Operands, false, Name)) return true; } Index: lib/Target/RISCV/CMakeLists.txt =================================================================== --- lib/Target/RISCV/CMakeLists.txt +++ lib/Target/RISCV/CMakeLists.txt @@ -10,6 +10,7 @@ tablegen(LLVM RISCVGenMCPseudoLowering.inc -gen-pseudo-lowering) tablegen(LLVM RISCVGenRegisterInfo.inc -gen-register-info) tablegen(LLVM RISCVGenSubtargetInfo.inc -gen-subtarget) +tablegen(LLVM RISCVGenSystemOperands.inc -gen-searchable-tables) add_public_tablegen_target(RISCVCommonTableGen) @@ -32,3 +33,4 @@ add_subdirectory(InstPrinter) add_subdirectory(MCTargetDesc) add_subdirectory(TargetInfo) +add_subdirectory(Utils) Index: lib/Target/RISCV/InstPrinter/LLVMBuild.txt =================================================================== --- lib/Target/RISCV/InstPrinter/LLVMBuild.txt +++ lib/Target/RISCV/InstPrinter/LLVMBuild.txt @@ -19,5 +19,5 @@ type = Library name = RISCVAsmPrinter parent = RISCV -required_libraries = MC Support +required_libraries = MC RISCVUtils Support add_to_library_groups = RISCV Index: lib/Target/RISCV/InstPrinter/RISCVInstPrinter.h =================================================================== --- lib/Target/RISCV/InstPrinter/RISCVInstPrinter.h +++ lib/Target/RISCV/InstPrinter/RISCVInstPrinter.h @@ -32,6 +32,8 @@ void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O, const char *Modifier = nullptr); + void printCSRSystemRegister(const MCInst *MI, unsigned OpNo, + const MCSubtargetInfo &STI, raw_ostream &O); void printFenceArg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); void printFRMArg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, Index: lib/Target/RISCV/InstPrinter/RISCVInstPrinter.cpp =================================================================== --- lib/Target/RISCV/InstPrinter/RISCVInstPrinter.cpp +++ lib/Target/RISCV/InstPrinter/RISCVInstPrinter.cpp @@ -12,8 +12,8 @@ //===----------------------------------------------------------------------===// #include "RISCVInstPrinter.h" -#include "MCTargetDesc/RISCVBaseInfo.h" #include "MCTargetDesc/RISCVMCExpr.h" +#include "Utils/RISCVBaseInfo.h" #include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCInst.h" @@ -79,6 +79,17 @@ MO.getExpr()->print(O, &MAI); } +void RISCVInstPrinter::printCSRSystemRegister(const MCInst *MI, unsigned OpNo, + const MCSubtargetInfo &STI, + raw_ostream &O) { + unsigned Imm = MI->getOperand(OpNo).getImm(); + auto SysReg = RISCVSysReg::lookupSysRegByEncoding(Imm); + if (SysReg) + O << SysReg->Name; + else + O << Imm; +} + void RISCVInstPrinter::printFenceArg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) { Index: lib/Target/RISCV/LLVMBuild.txt =================================================================== --- lib/Target/RISCV/LLVMBuild.txt +++ lib/Target/RISCV/LLVMBuild.txt @@ -16,7 +16,7 @@ ;===------------------------------------------------------------------------===; [common] -subdirectories = AsmParser Disassembler InstPrinter TargetInfo MCTargetDesc +subdirectories = AsmParser Disassembler InstPrinter TargetInfo MCTargetDesc Utils [component_0] type = TargetGroup @@ -31,5 +31,5 @@ name = RISCVCodeGen parent = RISCV required_libraries = AsmPrinter Core CodeGen MC RISCVAsmPrinter RISCVDesc - RISCVInfo SelectionDAG Support Target + RISCVInfo RISCVUtils SelectionDAG Support Target add_to_library_groups = RISCV Index: lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp =================================================================== --- lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp +++ lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp @@ -11,10 +11,10 @@ // //===----------------------------------------------------------------------===// -#include "MCTargetDesc/RISCVBaseInfo.h" #include "MCTargetDesc/RISCVFixupKinds.h" #include "MCTargetDesc/RISCVMCExpr.h" #include "MCTargetDesc/RISCVMCTargetDesc.h" +#include "Utils/RISCVBaseInfo.h" #include "llvm/ADT/Statistic.h" #include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCCodeEmitter.h" Index: lib/Target/RISCV/RISCV.h =================================================================== --- lib/Target/RISCV/RISCV.h +++ lib/Target/RISCV/RISCV.h @@ -15,7 +15,7 @@ #ifndef LLVM_LIB_TARGET_RISCV_RISCV_H #define LLVM_LIB_TARGET_RISCV_RISCV_H -#include "MCTargetDesc/RISCVBaseInfo.h" +#include "Utils/RISCVBaseInfo.h" namespace llvm { class RISCVTargetMachine; Index: lib/Target/RISCV/RISCV.td =================================================================== --- lib/Target/RISCV/RISCV.td +++ lib/Target/RISCV/RISCV.td @@ -68,6 +68,12 @@ include "RISCVInstrInfo.td" //===----------------------------------------------------------------------===// +// Named operands for CSR instructions. +//===----------------------------------------------------------------------===// + +include "RISCVSystemOperands.td" + +//===----------------------------------------------------------------------===// // RISC-V processors supported. //===----------------------------------------------------------------------===// Index: lib/Target/RISCV/RISCVInstrInfo.td =================================================================== --- lib/Target/RISCV/RISCVInstrInfo.td +++ lib/Target/RISCV/RISCVInstrInfo.td @@ -182,6 +182,18 @@ }]; } +def CSRSystemRegister : AsmOperandClass { + let Name = "CSRSystemRegister"; + let ParserMethod = "parseCSRSystemRegister"; + let DiagnosticType = "InvalidCSRSystemRegister"; +} + +def csr_sysreg : Operand { + let ParserMatchClass = CSRSystemRegister; + let PrintMethod = "printCSRSystemRegister"; + let DecoderMethod = "decodeUImmOperand<12>"; +} + // A parameterized register class alternative to i32imm/i64imm from Target.td. def ixlenimm : Operand { let ParserMatchClass = ImmXLenAsmOperand<"">; @@ -255,13 +267,13 @@ let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in class CSR_ir funct3, string opcodestr> - : RVInstI; let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in class CSR_ii funct3, string opcodestr> : RVInstI; let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in @@ -538,14 +550,14 @@ def : InstAlias<"rdtimeh $rd", (CSRRS GPR:$rd, 0xC81, X0)>; } // Predicates = [IsRV32] -def : InstAlias<"csrr $rd, $csr", (CSRRS GPR:$rd, uimm12:$csr, X0)>; -def : InstAlias<"csrw $csr, $rs", (CSRRW X0, uimm12:$csr, GPR:$rs)>; -def : InstAlias<"csrs $csr, $rs", (CSRRS X0, uimm12:$csr, GPR:$rs)>; -def : InstAlias<"csrc $csr, $rs", (CSRRC X0, uimm12:$csr, GPR:$rs)>; +def : InstAlias<"csrr $rd, $csr", (CSRRS GPR:$rd, csr_sysreg:$csr, X0)>; +def : InstAlias<"csrw $csr, $rs", (CSRRW X0, csr_sysreg:$csr, GPR:$rs)>; +def : InstAlias<"csrs $csr, $rs", (CSRRS X0, csr_sysreg:$csr, GPR:$rs)>; +def : InstAlias<"csrc $csr, $rs", (CSRRC X0, csr_sysreg:$csr, GPR:$rs)>; -def : InstAlias<"csrwi $csr, $imm", (CSRRWI X0, uimm12:$csr, uimm5:$imm)>; -def : InstAlias<"csrsi $csr, $imm", (CSRRSI X0, uimm12:$csr, uimm5:$imm)>; -def : InstAlias<"csrci $csr, $imm", (CSRRCI X0, uimm12:$csr, uimm5:$imm)>; +def : InstAlias<"csrwi $csr, $imm", (CSRRWI X0, csr_sysreg:$csr, uimm5:$imm)>; +def : InstAlias<"csrsi $csr, $imm", (CSRRSI X0, csr_sysreg:$csr, uimm5:$imm)>; +def : InstAlias<"csrci $csr, $imm", (CSRRCI X0, csr_sysreg:$csr, uimm5:$imm)>; def : InstAlias<"sfence.vma", (SFENCE_VMA X0, X0)>; def : InstAlias<"sfence.vma $rs", (SFENCE_VMA GPR:$rs, X0)>; Index: lib/Target/RISCV/RISCVSystemOperands.td =================================================================== --- /dev/null +++ lib/Target/RISCV/RISCVSystemOperands.td @@ -0,0 +1,335 @@ +//===- RISCVSystemOperands.td ----------------------------*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines the symbolic operands permitted for various kinds of +// RISC-V system instruction. +// +//===----------------------------------------------------------------------===// + +include "llvm/TableGen/SearchableTable.td" + +//===----------------------------------------------------------------------===// +// CSR (control and status register read/write) instruction options. +//===----------------------------------------------------------------------===// + +class SysReg op> : SearchableTable { + let SearchableFields = ["Name", "Encoding"]; + let EnumValueField = "Encoding"; + + string Name = name; + bits<12> Encoding = op; + // Privilege Access: Read and Write = 0, 1, 2; Read-Only = 3. + // Privilege Mode: User = 0, System = 1 or Machine = 3. + bits<2> ReadWrite = op{11-10}; + bits<2> Mode = op{9-8}; + // FIXME: check what bits 7-6 correspond to. + bits<2> Extra = op{7-6}; + // Register number without the privilege bits. + bits<6> Number = op{5-0}; + code Requires = [{ {} }]; +} + +// The following CSR encodings match those given in Tables 2.2, +// 2.3, 2.4 and 2.5 in the RISC-V Instruction Set Manual +// Volume II: Privileged Architecture. + +//===-------------------------- +// User Trap Setup +//===-------------------------- +def : SysReg<"USTATUS", 0x000>; +def : SysReg<"UIE", 0x004>; +def : SysReg<"UTVEC", 0x005>; + +//===-------------------------- +// User Trap Handling +//===-------------------------- +def : SysReg<"USCRATCH", 0x040>; +def : SysReg<"UEPC", 0x041>; +def : SysReg<"UCAUSE", 0x042>; +def : SysReg<"UTVAL", 0x043>; +def : SysReg<"UIP", 0x044>; + + +//===-------------------------- +// User Floating-Point CSRs +//===-------------------------- + +def : SysReg<"FFLAGS", 0x001>; +def : SysReg<"FRM", 0x002>; +def : SysReg<"FCSR", 0x003>; + +//===-------------------------- +// User Counter/Timers +//===-------------------------- +def : SysReg<"CYCLE", 0xC00>; +def : SysReg<"TIME", 0xC01>; +def : SysReg<"INSTRET", 0xC02>; + +def : SysReg<"HPMCOUNTER3", 0xC03>; +def : SysReg<"HPMCOUNTER4", 0xC04>; +def : SysReg<"HPMCOUNTER5", 0xC05>; +def : SysReg<"HPMCOUNTER6", 0xC06>; +def : SysReg<"HPMCOUNTER7", 0xC07>; +def : SysReg<"HPMCOUNTER8", 0xC08>; +def : SysReg<"HPMCOUNTER9", 0xC09>; +def : SysReg<"HPMCOUNTER10", 0xC0A>; +def : SysReg<"HPMCOUNTER11", 0xC0B>; +def : SysReg<"HPMCOUNTER12", 0xC0C>; +def : SysReg<"HPMCOUNTER13", 0xC0D>; +def : SysReg<"HPMCOUNTER14", 0xC0E>; +def : SysReg<"HPMCOUNTER15", 0xC0F>; +def : SysReg<"HPMCOUNTER16", 0xC10>; +def : SysReg<"HPMCOUNTER17", 0xC11>; +def : SysReg<"HPMCOUNTER18", 0xC12>; +def : SysReg<"HPMCOUNTER19", 0xC13>; +def : SysReg<"HPMCOUNTER20", 0xC14>; +def : SysReg<"HPMCOUNTER21", 0xC15>; +def : SysReg<"HPMCOUNTER22", 0xC16>; +def : SysReg<"HPMCOUNTER23", 0xC17>; +def : SysReg<"HPMCOUNTER24", 0xC18>; +def : SysReg<"HPMCOUNTER25", 0xC19>; +def : SysReg<"HPMCOUNTER26", 0xC1A>; +def : SysReg<"HPMCOUNTER27", 0xC1B>; +def : SysReg<"HPMCOUNTER28", 0xC1C>; +def : SysReg<"HPMCOUNTER29", 0xC1D>; +def : SysReg<"HPMCOUNTER30", 0xC1E>; +def : SysReg<"HPMCOUNTER31", 0xC1F>; + +let Requires = [{ {!RISCV::Feature64Bit} }] in { +def : SysReg<"CYCLEH", 0xC80>; +def : SysReg<"TIMEH", 0xC81>; +def : SysReg<"INSTRETH", 0xC82>; + +def : SysReg<"HPMCOUNTER3H", 0xC83>; +def : SysReg<"HPMCOUNTER4H", 0xC84>; +def : SysReg<"HPMCOUNTER5H", 0xC85>; +def : SysReg<"HPMCOUNTER6H", 0xC86>; +def : SysReg<"HPMCOUNTER7H", 0xC87>; +def : SysReg<"HPMCOUNTER8H", 0xC88>; +def : SysReg<"HPMCOUNTER9H", 0xC89>; +def : SysReg<"HPMCOUNTER10H", 0xC8A>; +def : SysReg<"HPMCOUNTER11H", 0xC8B>; +def : SysReg<"HPMCOUNTER12H", 0xC8C>; +def : SysReg<"HPMCOUNTER13H", 0xC8D>; +def : SysReg<"HPMCOUNTER14H", 0xC8E>; +def : SysReg<"HPMCOUNTER15H", 0xC8F>; +def : SysReg<"HPMCOUNTER16H", 0xC90>; +def : SysReg<"HPMCOUNTER17H", 0xC91>; +def : SysReg<"HPMCOUNTER18H", 0xC92>; +def : SysReg<"HPMCOUNTER19H", 0xC93>; +def : SysReg<"HPMCOUNTER20H", 0xC94>; +def : SysReg<"HPMCOUNTER21H", 0xC95>; +def : SysReg<"HPMCOUNTER22H", 0xC96>; +def : SysReg<"HPMCOUNTER23H", 0xC97>; +def : SysReg<"HPMCOUNTER24H", 0xC98>; +def : SysReg<"HPMCOUNTER25H", 0xC99>; +def : SysReg<"HPMCOUNTER26H", 0xC9A>; +def : SysReg<"HPMCOUNTER27H", 0xC9B>; +def : SysReg<"HPMCOUNTER28H", 0xC9C>; +def : SysReg<"HPMCOUNTER29H", 0xC9D>; +def : SysReg<"HPMCOUNTER30H", 0xC9E>; +def : SysReg<"HPMCOUNTER31H", 0xC9F>; +} + +//===-------------------------- +// Supervisor Trap Setup +//===-------------------------- +def : SysReg<"SSTATUS", 0x100>; +def : SysReg<"SEDELEG", 0x102>; +def : SysReg<"SIDELEG", 0x103>; +def : SysReg<"SIE", 0x104>; +def : SysReg<"STVEC", 0x105>; +def : SysReg<"SCOUNTEREN", 0x106>; + +//===-------------------------- +// Supervisor Trap Handling +//===-------------------------- +def : SysReg<"SSCRATCH", 0x140>; +def : SysReg<"SEPC", 0x141>; +def : SysReg<"SCAUSE", 0x142>; +def : SysReg<"STVAL", 0x143>; +def : SysReg<"SIP", 0x144>; + +//===------------------------------------- +// Supervisor Protection and Translation +//===------------------------------------- +def : SysReg<"SATP", 0x180>; + +//===----------------------------- +// Machine Information Registers +//===----------------------------- + +def : SysReg<"MVENDORID", 0xF11>; +def : SysReg<"MARCHID", 0xF12>; +def : SysReg<"MIMPID", 0xF13>; +def : SysReg<"MHARTID", 0xF14>; + +//===----------------------------- +// Machine Trap Setup +//===----------------------------- +def : SysReg<"MSTATUS", 0x300>; +def : SysReg<"MISA", 0x301>; +def : SysReg<"MEDELEG", 0x302>; +def : SysReg<"MIDELEG", 0x303>; +def : SysReg<"MIE", 0x304>; +def : SysReg<"MTVEC", 0x305>; +def : SysReg<"MCOUNTEREN", 0x306>; + +//===----------------------------- +// Machine Trap Handling +//===----------------------------- +def : SysReg<"MSCRATCH", 0x340>; +def : SysReg<"MEPC", 0x341>; +def : SysReg<"MCAUSE", 0x342>; +def : SysReg<"MTVAL", 0x343>; +def : SysReg<"MIP", 0x344>; + +//===---------------------------------- +// Machine Protection and Translation +//===---------------------------------- +def : SysReg<"PMPCFG0", 0x3A0>; +def : SysReg<"PMPCFG1", 0x3A1>; +def : SysReg<"PMPCFG2", 0x3A2>; +def : SysReg<"PMPCFG3", 0x3A3>; + +def : SysReg<"PMPADDR0", 0x3B0>; +def : SysReg<"PMPADDR1", 0x3B1>; +def : SysReg<"PMPADDR2", 0x3B2>; +def : SysReg<"PMPADDR3", 0x3B3>; +def : SysReg<"PMPADDR4", 0x3B4>; +def : SysReg<"PMPADDR5", 0x3B5>; +def : SysReg<"PMPADDR6", 0x3B6>; +def : SysReg<"PMPADDR7", 0x3B7>; +def : SysReg<"PMPADDR8", 0x3B8>; +def : SysReg<"PMPADDR9", 0x3B9>; +def : SysReg<"PMPADDR10", 0x3BA>; +def : SysReg<"PMPADDR11", 0x3BB>; +def : SysReg<"PMPADDR12", 0x3BC>; +def : SysReg<"PMPADDR13", 0x3BD>; +def : SysReg<"PMPADDR14", 0x3BE>; +def : SysReg<"PMPADDR15", 0x3BF>; + +//===-------------------------- +// Machine Counter and Timers +//===-------------------------- +def : SysReg<"MCYCLE", 0xB00>; +def : SysReg<"MINSTRET", 0xB02>; + +def : SysReg<"MHPMCOUNTER3", 0xB03>; +def : SysReg<"MHPMCOUNTER4", 0xB04>; +def : SysReg<"MHPMCOUNTER5", 0xB05>; +def : SysReg<"MHPMCOUNTER6", 0xB06>; +def : SysReg<"MHPMCOUNTER7", 0xB07>; +def : SysReg<"MHPMCOUNTER8", 0xB08>; +def : SysReg<"MHPMCOUNTER9", 0xB09>; +def : SysReg<"MHPMCOUNTER10", 0xB0A>; +def : SysReg<"MHPMCOUNTER11", 0xB0B>; +def : SysReg<"MHPMCOUNTER12", 0xB0C>; +def : SysReg<"MHPMCOUNTER13", 0xB0D>; +def : SysReg<"MHPMCOUNTER14", 0xB0E>; +def : SysReg<"MHPMCOUNTER15", 0xB0F>; +def : SysReg<"MHPMCOUNTER16", 0xB10>; +def : SysReg<"MHPMCOUNTER17", 0xB11>; +def : SysReg<"MHPMCOUNTER18", 0xB12>; +def : SysReg<"MHPMCOUNTER19", 0xB13>; +def : SysReg<"MHPMCOUNTER20", 0xB14>; +def : SysReg<"MHPMCOUNTER21", 0xB15>; +def : SysReg<"MHPMCOUNTER22", 0xB16>; +def : SysReg<"MHPMCOUNTER23", 0xB17>; +def : SysReg<"MHPMCOUNTER24", 0xB18>; +def : SysReg<"MHPMCOUNTER25", 0xB19>; +def : SysReg<"MHPMCOUNTER26", 0xB1A>; +def : SysReg<"MHPMCOUNTER27", 0xB1B>; +def : SysReg<"MHPMCOUNTER28", 0xB1C>; +def : SysReg<"MHPMCOUNTER29", 0xB1D>; +def : SysReg<"MHPMCOUNTER30", 0xB1E>; +def : SysReg<"MHPMCOUNTER31", 0xB1F>; + +let Requires = [{ {!RISCV::Feature64Bit} }] in { +def : SysReg<"MCYCLEH", 0xB80>; +def : SysReg<"MINSTRETH", 0xB82>; + +def : SysReg<"MHPMCOUNTER3H", 0xB83>; +def : SysReg<"MHPMCOUNTER4H", 0xB84>; +def : SysReg<"MHPMCOUNTER5H", 0xB85>; +def : SysReg<"MHPMCOUNTER6H", 0xB86>; +def : SysReg<"MHPMCOUNTER7H", 0xB87>; +def : SysReg<"MHPMCOUNTER8H", 0xB88>; +def : SysReg<"MHPMCOUNTER9H", 0xB89>; +def : SysReg<"MHPMCOUNTER10H", 0xB8A>; +def : SysReg<"MHPMCOUNTER11H", 0xB8B>; +def : SysReg<"MHPMCOUNTER12H", 0xB8C>; +def : SysReg<"MHPMCOUNTER13H", 0xB8D>; +def : SysReg<"MHPMCOUNTER14H", 0xB8E>; +def : SysReg<"MHPMCOUNTER15H", 0xB8F>; +def : SysReg<"MHPMCOUNTER16H", 0xB90>; +def : SysReg<"MHPMCOUNTER17H", 0xB91>; +def : SysReg<"MHPMCOUNTER18H", 0xB92>; +def : SysReg<"MHPMCOUNTER19H", 0xB93>; +def : SysReg<"MHPMCOUNTER20H", 0xB94>; +def : SysReg<"MHPMCOUNTER21H", 0xB95>; +def : SysReg<"MHPMCOUNTER22H", 0xB96>; +def : SysReg<"MHPMCOUNTER23H", 0xB97>; +def : SysReg<"MHPMCOUNTER24H", 0xB98>; +def : SysReg<"MHPMCOUNTER25H", 0xB99>; +def : SysReg<"MHPMCOUNTER26H", 0xB9A>; +def : SysReg<"MHPMCOUNTER27H", 0xB9B>; +def : SysReg<"MHPMCOUNTER28H", 0xB9C>; +def : SysReg<"MHPMCOUNTER29H", 0xB9D>; +def : SysReg<"MHPMCOUNTER30H", 0xB9E>; +def : SysReg<"MHPMCOUNTER31H", 0xB9F>; +} + +//===-------------------------- +// Machine Counter Setup +//===-------------------------- +def : SysReg<"MHPMEVENT3", 0x323>; +def : SysReg<"MHPMEVENT4", 0x324>; +def : SysReg<"MHPMEVENT5", 0x325>; +def : SysReg<"MHPMEVENT6", 0x326>; +def : SysReg<"MHPMEVENT7", 0x327>; +def : SysReg<"MHPMEVENT8", 0x328>; +def : SysReg<"MHPMEVENT9", 0x329>; +def : SysReg<"MHPMEVENT10", 0x32A>; +def : SysReg<"MHPMEVENT11", 0x32B>; +def : SysReg<"MHPMEVENT12", 0x32C>; +def : SysReg<"MHPMEVENT13", 0x32D>; +def : SysReg<"MHPMEVENT14", 0x32E>; +def : SysReg<"MHPMEVENT15", 0x32F>; +def : SysReg<"MHPMEVENT16", 0x330>; +def : SysReg<"MHPMEVENT17", 0x331>; +def : SysReg<"MHPMEVENT18", 0x332>; +def : SysReg<"MHPMEVENT19", 0x333>; +def : SysReg<"MHPMEVENT20", 0x334>; +def : SysReg<"MHPMEVENT21", 0x335>; +def : SysReg<"MHPMEVENT22", 0x336>; +def : SysReg<"MHPMEVENT23", 0x337>; +def : SysReg<"MHPMEVENT24", 0x338>; +def : SysReg<"MHPMEVENT25", 0x339>; +def : SysReg<"MHPMEVENT26", 0x33A>; +def : SysReg<"MHPMEVENT27", 0x33B>; +def : SysReg<"MHPMEVENT28", 0x33C>; +def : SysReg<"MHPMEVENT29", 0x33D>; +def : SysReg<"MHPMEVENT30", 0x33E>; +def : SysReg<"MHPMEVENT31", 0x33F>; + +//===----------------------------------------------- +// Debug/ Trace Registers (shared with Debug Mode) +//===----------------------------------------------- +def : SysReg<"TSELECT", 0x7A0>; +def : SysReg<"TDATA1", 0x7A1>; +def : SysReg<"TDATA2", 0x7A2>; +def : SysReg<"TDATA3", 0x7A3>; + +//===----------------------------------------------- +// Debug Mode Registers +//===----------------------------------------------- +def : SysReg<"DCSR", 0x7B0>; +def : SysReg<"DPC", 0x7B1>; +def : SysReg<"DSCRATCH", 0x7B2>; Index: lib/Target/RISCV/Utils/CMakeLists.txt =================================================================== --- /dev/null +++ lib/Target/RISCV/Utils/CMakeLists.txt @@ -0,0 +1,3 @@ +add_llvm_library(LLVMRISCVUtils + RISCVBaseInfo.cpp + ) Index: lib/Target/RISCV/Utils/LLVMBuild.txt =================================================================== --- /dev/null +++ lib/Target/RISCV/Utils/LLVMBuild.txt @@ -0,0 +1,24 @@ +;===- ./lib/Target/RISCV/Utils/LLVMBuild.txt ----------------*- Conf -*--===; +; +; The LLVM Compiler Infrastructure +; +; This file is distributed under the University of Illinois Open Source +; License. See LICENSE.TXT for details. +; +;===------------------------------------------------------------------------===; +; +; This is an LLVMBuild description file for the components in this subdirectory. +; +; For more information on the LLVMBuild system, please see: +; +; http://llvm.org/docs/LLVMBuild.html +; +;===------------------------------------------------------------------------===; + +[component_0] +type = Library +name = RISCVUtils +parent = RISCV +required_libraries = Support +add_to_library_groups = RISCV + Index: lib/Target/RISCV/Utils/RISCVBaseInfo.h =================================================================== --- /dev/null +++ lib/Target/RISCV/Utils/RISCVBaseInfo.h @@ -0,0 +1,135 @@ +//===-- RISCVBaseInfo.h - Top level definitions for RISCV MC ----*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains small standalone enum definitions for the RISCV target +// useful for the compiler back-end and the MC libraries. +// +//===----------------------------------------------------------------------===// +#ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H +#define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H + +#include "MCTargetDesc/RISCVMCTargetDesc.h" +#include "llvm/ADT/StringRef.h" +#include "llvm/ADT/StringSwitch.h" +#include "llvm/MC/SubtargetFeature.h" + +namespace llvm { + +// RISCVII - This namespace holds all of the target specific flags that +// instruction info tracks. All definitions must match RISCVInstrFormats.td. +namespace RISCVII { +enum { + InstFormatPseudo = 0, + InstFormatR = 1, + InstFormatR4 = 2, + InstFormatI = 3, + InstFormatS = 4, + InstFormatB = 5, + InstFormatU = 6, + InstFormatJ = 7, + InstFormatCR = 8, + InstFormatCI = 9, + InstFormatCSS = 10, + InstFormatCIW = 11, + InstFormatCL = 12, + InstFormatCS = 13, + InstFormatCB = 14, + InstFormatCJ = 15, + InstFormatOther = 16, + + InstFormatMask = 31 +}; + +enum { + MO_None, + MO_LO, + MO_HI, + MO_PCREL_HI, +}; +} // namespace RISCVII + +// Describes the predecessor/successor bits used in the FENCE instruction. +namespace RISCVFenceField { +enum FenceField { + I = 8, + O = 4, + R = 2, + W = 1 +}; +} + +// Describes the supported floating point rounding mode encodings. +namespace RISCVFPRndMode { +enum RoundingMode { + RNE = 0, + RTZ = 1, + RDN = 2, + RUP = 3, + RMM = 4, + DYN = 7, + Invalid +}; + +inline static StringRef roundingModeToString(RoundingMode RndMode) { + switch (RndMode) { + default: + llvm_unreachable("Unknown floating point rounding mode"); + case RISCVFPRndMode::RNE: + return "rne"; + case RISCVFPRndMode::RTZ: + return "rtz"; + case RISCVFPRndMode::RDN: + return "rdn"; + case RISCVFPRndMode::RUP: + return "rup"; + case RISCVFPRndMode::RMM: + return "rmm"; + case RISCVFPRndMode::DYN: + return "dyn"; + } +} + +inline static RoundingMode stringToRoundingMode(StringRef Str) { + return StringSwitch(Str) + .Case("rne", RISCVFPRndMode::RNE) + .Case("rtz", RISCVFPRndMode::RTZ) + .Case("rdn", RISCVFPRndMode::RDN) + .Case("rup", RISCVFPRndMode::RUP) + .Case("rmm", RISCVFPRndMode::RMM) + .Case("dyn", RISCVFPRndMode::DYN) + .Default(RISCVFPRndMode::Invalid); +} +} // namespace RISCVFPRndMode + +namespace RISCVSysReg { + struct SysReg { + const char *Name; + unsigned Encoding; + unsigned ReadWrite; + unsigned Mode; + unsigned Extra; + unsigned Number; + FeatureBitset FeaturesRequired; + + bool haveFeatures(FeatureBitset ActiveFeatures) const { + return (FeaturesRequired & ActiveFeatures) == FeaturesRequired; + } + }; + + #define GET_SYSREG_DECL + #include "RISCVGenSystemOperands.inc" + + const SysReg *lookupSysRegByName(StringRef); + const SysReg *lookupSysRegByEncoding(uint16_t); + +} // end namespace RISCVSysReg + +} // namespace llvm + +#endif Index: lib/Target/RISCV/Utils/RISCVBaseInfo.cpp =================================================================== --- /dev/null +++ lib/Target/RISCV/Utils/RISCVBaseInfo.cpp @@ -0,0 +1,10 @@ +#include "RISCVBaseInfo.h" +#include "llvm/ADT/ArrayRef.h" + +namespace llvm { + namespace RISCVSysReg { +#define GET_SYSREG_IMPL +#include "RISCVGenSystemOperands.inc" + } +} + Index: test/MC/RISCV/csr-aliases.s =================================================================== --- test/MC/RISCV/csr-aliases.s +++ test/MC/RISCV/csr-aliases.s @@ -37,81 +37,81 @@ # RUN: | FileCheck -check-prefix=CHECK-EXT-F-OFF %s -# CHECK-INST: csrrs t0, 3, zero +# CHECK-INST: csrrs t0, FCSR, zero # CHECK-ALIAS: frcsr t0 # CHECK-EXT-F: frcsr t0 -# CHECK-EXT-F-OFF: csrr t0, 3 +# CHECK-EXT-F-OFF: csrr t0, FCSR csrrs t0, 3, zero -# CHECK-INST: csrrw t1, 3, t2 +# CHECK-INST: csrrw t1, FCSR, t2 # CHECK-ALIAS: fscsr t1, t2 # CHECK-EXT-F-ON: fscsr t1, t2 -# CHECK-EXT-F-OFF: csrrw t1, 3, t2 +# CHECK-EXT-F-OFF: csrrw t1, FCSR, t2 csrrw t1, 3, t2 -# CHECK-INST: csrrw zero, 3, t2 +# CHECK-INST: csrrw zero, FCSR, t2 # CHECK-ALIAS: fscsr t2 # CHECK-EXT-F-ON: fscsr t2 -# CHECK-EXT-F-OFF: csrw 3, t2 +# CHECK-EXT-F-OFF: csrw FCSR, t2 csrrw zero, 3, t2 -# CHECK-INST: csrrw zero, 3, t2 +# CHECK-INST: csrrw zero, FCSR, t2 # CHECK-ALIAS: fscsr t2 # CHECK-EXT-F-ON: fscsr t2 -# CHECK-EXT-F-OFF: csrw 3, t2 +# CHECK-EXT-F-OFF: csrw FCSR, t2 csrrw zero, 3, t2 -# CHECK-INST: csrrw t0, 2, zero +# CHECK-INST: csrrw t0, FRM, zero # CHECK-ALIAS: fsrm t0, zero # CHECK-EXT-F-ON: fsrm t0, zero -# CHECK-EXT-F-OFF: csrrw t0, 2, zero +# CHECK-EXT-F-OFF: csrrw t0, FRM, zero csrrw t0, 2, zero -# CHECK-INST: csrrw t0, 2, t1 +# CHECK-INST: csrrw t0, FRM, t1 # CHECK-ALIAS: fsrm t0, t1 # CHECK-EXT-F-ON: fsrm t0, t1 -# CHECK-EXT-F-OFF: csrrw t0, 2, t1 +# CHECK-EXT-F-OFF: csrrw t0, FRM, t1 csrrw t0, 2, t1 -# CHECK-INST: csrrwi t0, 2, 31 +# CHECK-INST: csrrwi t0, FRM, 31 # CHECK-ALIAS: fsrmi t0, 31 # CHECK-EXT-F-ON: fsrmi t0, 31 -# CHECK-EXT-F-OFF: csrrwi t0, 2, 31 +# CHECK-EXT-F-OFF: csrrwi t0, FRM, 31 csrrwi t0, 2, 31 -# CHECK-INST: csrrwi zero, 2, 31 +# CHECK-INST: csrrwi zero, FRM, 31 # CHECK-ALIAS: fsrmi 31 # CHECK-EXT-F-ON: fsrmi 31 -# CHECK-EXT-F-OFF: csrwi 2, 31 +# CHECK-EXT-F-OFF: csrwi FRM, 31 csrrwi zero, 2, 31 -# CHECK-INST: csrrs t0, 1, zero +# CHECK-INST: csrrs t0, FFLAGS, zero # CHECK-ALIAS: frflags t0 # CHECK-EXT-F-ON: frflags t0 -# CHECK-EXT-F-OFF: csrr t0, 1 +# CHECK-EXT-F-OFF: csrr t0, FFLAGS csrrs t0, 1, zero -# CHECK-INST: csrrw t0, 1, t2 +# CHECK-INST: csrrw t0, FFLAGS, t2 # CHECK-ALIAS: fsflags t0, t2 # CHECK-EXT-F-ON: fsflags t0, t2 -# CHECK-EXT-F-OFF: csrrw t0, 1, t2 +# CHECK-EXT-F-OFF: csrrw t0, FFLAGS, t2 csrrw t0, 1, t2 -# CHECK-INST: csrrw zero, 1, t2 +# CHECK-INST: csrrw zero, FFLAGS, t2 # CHECK-ALIAS: fsflags t2 # CHECK-EXT-F-ON: fsflags t2 -# CHECK-EXT-F-OFF: csrw 1, t2 +# CHECK-EXT-F-OFF: csrw FFLAGS, t2 csrrw zero, 1, t2 -# CHECK-INST: csrrwi t0, 1, 31 +# CHECK-INST: csrrwi t0, FFLAGS, 31 # CHECK-ALIAS: fsflagsi t0, 31 # CHECK-EXT-F: fsflagsi t0, 31 -# CHECK-EXT-F-OFF: csrrwi t0, 1, 31 +# CHECK-EXT-F-OFF: csrrwi t0, FFLAGS, 31 csrrwi t0, 1, 31 -# CHECK-INST: csrrwi zero, 1, 31 +# CHECK-INST: csrrwi zero, FFLAGS, 31 # CHECK-ALIAS: fsflagsi 31 # CHECK-EXT-F: fsflagsi 31 -# CHECK-EXT-F-OFF: csrwi 1, 31 +# CHECK-EXT-F-OFF: csrwi FFLAGS, 31 csrrwi zero, 1, 31 Index: test/MC/RISCV/machine-csr-names.s =================================================================== --- /dev/null +++ test/MC/RISCV/machine-csr-names.s @@ -0,0 +1,1312 @@ +# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-INST %s +# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \ +# RUN: | llvm-objdump -d - \ +# RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s +# +# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-INST %s +# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \ +# RUN: | llvm-objdump -d - \ +# RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s + + +################################## +# Machine Information Registers +################################## + +# mvendorid +# name +# CHECK-INST: csrrs t1, MVENDORID, zero +# CHECK-ENC: encoding: [0x73,0x23,0x10,0xf1] +# CHECK-INST: csrrw zero, MVENDORID, t2 +# CHECK-ENC: encoding: [0x73,0x90,0x13,0xf1] +# CHECK-INST: csrrs zero, MVENDORID, t2 +# CHECK-ENC: encoding: [0x73,0xa0,0x13,0xf1] +# CHECK-INST: csrrc zero, MVENDORID, t2 +# CHECK-ENC: encoding: [0x73,0xb0,0x13,0xf1] +# CHECK-INST: csrrwi zero, MVENDORID, 1 +# CHECK-ENC: encoding: [0x73,0xd0,0x10,0xf1] +# CHECK-INST: csrrsi zero, MVENDORID, 1 +# CHECK-ENC: encoding: [0x73,0xe0,0x10,0xf1] +# CHECK-INST: csrrci zero, MVENDORID, 1 +# CHECK-ENC: encoding: [0x73,0xf0,0x10,0xf1] +# uimm12 +# CHECK-INST: csrrs t1, MVENDORID, zero +# CHECK-ENC: encoding: [0x73,0x23,0x10,0xf1] +# CHECK-INST: csrrw zero, MVENDORID, t2 +# CHECK-ENC: encoding: [0x73,0x90,0x13,0xf1] +# CHECK-INST: csrrs zero, MVENDORID, t2 +# CHECK-ENC: encoding: [0x73,0xa0,0x13,0xf1] +# CHECK-INST: csrrc zero, MVENDORID, t2 +# CHECK-ENC: encoding: [0x73,0xb0,0x13,0xf1] +# CHECK-INST: csrrwi zero, MVENDORID, 1 +# CHECK-ENC: encoding: [0x73,0xd0,0x10,0xf1] +# CHECK-INST: csrrsi zero, MVENDORID, 1 +# CHECK-ENC: encoding: [0x73,0xe0,0x10,0xf1] +# CHECK-INST: csrrci zero, MVENDORID, 1 +# CHECK-ENC: encoding: [0x73,0xf0,0x10,0xf1] +# aliases +# CHECK-INST-ALIAS: csrr t1, MVENDORID +# CHECK-INST-ALIAS: csrw MVENDORID, t2 +# CHECK-INST-ALIAS: csrs MVENDORID, t2 +# CHECK-INST-ALIAS: csrc MVENDORID, t2 +# CHECK-INST-ALIAS: csrwi MVENDORID, 1 +# CHECK-INST-ALIAS: csrsi MVENDORID, 1 +# CHECK-INST-ALIAS: csrci MVENDORID, 1 +# aliases with uimm12 +# CHECK-INST-ALIAS: csrr t1, MVENDORID +# CHECK-INST-ALIAS: csrw MVENDORID, t2 +# CHECK-INST-ALIAS: csrs MVENDORID, t2 +# CHECK-INST-ALIAS: csrc MVENDORID, t2 +# CHECK-INST-ALIAS: csrwi MVENDORID, 1 +# CHECK-INST-ALIAS: csrsi MVENDORID, 1 +# CHECK-INST-ALIAS: csrci MVENDORID, 1 +# name +csrrs t1, mvendorid, x0 +csrrw x0, mvendorid, t2 +csrrs x0, mvendorid, t2 +csrrc x0, mvendorid, t2 +csrrwi x0, mvendorid, 1 +csrrsi x0, mvendorid, 1 +csrrci x0, mvendorid, 1 +# uimm12 +csrrs t1, 0xF11, x0 +csrrw x0, 0xF11, t2 +csrrs x0, 0xF11, t2 +csrrc x0, 0xF11, t2 +csrrwi x0, 0xF11, 1 +csrrsi x0, 0xF11, 1 +csrrci x0, 0xF11, 1 + +# marchid +# name +# CHECK-INST: csrrs t1, MARCHID, zero +# CHECK-INST: csrrw zero, MARCHID, t2 +# CHECK-INST: csrrs zero, MARCHID, t2 +# CHECK-INST: csrrc zero, MARCHID, t2 +# CHECK-INST: csrrwi zero, MARCHID, 1 +# CHECK-INST: csrrsi zero, MARCHID, 1 +# CHECK-INST: csrrci zero, MARCHID, 1 +# uimm12 +# CHECK-INST: csrrs t1, MARCHID, zero +# CHECK-INST: csrrw zero, MARCHID, t2 +# CHECK-INST: csrrs zero, MARCHID, t2 +# CHECK-INST: csrrc zero, MARCHID, t2 +# CHECK-INST: csrrwi zero, MARCHID, 1 +# CHECK-INST: csrrsi zero, MARCHID, 1 +# CHECK-INST: csrrci zero, MARCHID, 1 +# aliases +# CHECK-INST-ALIAS: csrr t1, MARCHID +# CHECK-INST-ALIAS: csrw MARCHID, t2 +# CHECK-INST-ALIAS: csrs MARCHID, t2 +# CHECK-INST-ALIAS: csrc MARCHID, t2 +# CHECK-INST-ALIAS: csrwi MARCHID, 1 +# CHECK-INST-ALIAS: csrsi MARCHID, 1 +# CHECK-INST-ALIAS: csrci MARCHID, 1 +# aliases with uimm12 +# CHECK-INST-ALIAS: csrr t1, MARCHID +# CHECK-INST-ALIAS: csrw MARCHID, t2 +# CHECK-INST-ALIAS: csrs MARCHID, t2 +# CHECK-INST-ALIAS: csrc MARCHID, t2 +# CHECK-INST-ALIAS: csrwi MARCHID, 1 +# CHECK-INST-ALIAS: csrsi MARCHID, 1 +# CHECK-INST-ALIAS: csrci MARCHID, 1 +# name +csrrs t1, marchid, x0 +csrrw x0, marchid, t2 +csrrs x0, marchid, t2 +csrrc x0, marchid, t2 +csrrwi x0, marchid, 1 +csrrsi x0, marchid, 1 +csrrci x0, marchid, 1 +# uimm12 +csrrs t1, 0xF12, x0 +csrrw x0, 0xF12, t2 +csrrs x0, 0xF12, t2 +csrrc x0, 0xF12, t2 +csrrwi x0, 0xF12, 1 +csrrsi x0, 0xF12, 1 +csrrci x0, 0xF12, 1 + +# mimpid +# name +# CHECK-INST: csrrs t1, MIMPID, zero +# CHECK-INST: csrrw zero, MIMPID, t2 +# CHECK-INST: csrrs zero, MIMPID, t2 +# CHECK-INST: csrrc zero, MIMPID, t2 +# CHECK-INST: csrrwi zero, MIMPID, 1 +# CHECK-INST: csrrsi zero, MIMPID, 1 +# CHECK-INST: csrrci zero, MIMPID, 1 +# uimm12 +# CHECK-INST: csrrs t1, MIMPID, zero +# CHECK-INST: csrrw zero, MIMPID, t2 +# CHECK-INST: csrrs zero, MIMPID, t2 +# CHECK-INST: csrrc zero, MIMPID, t2 +# CHECK-INST: csrrwi zero, MIMPID, 1 +# CHECK-INST: csrrsi zero, MIMPID, 1 +# CHECK-INST: csrrci zero, MIMPID, 1 +# aliases +# CHECK-INST-ALIAS: csrr t1, MIMPID +# CHECK-INST-ALIAS: csrw MIMPID, t2 +# CHECK-INST-ALIAS: csrs MIMPID, t2 +# CHECK-INST-ALIAS: csrc MIMPID, t2 +# CHECK-INST-ALIAS: csrwi MIMPID, 1 +# CHECK-INST-ALIAS: csrsi MIMPID, 1 +# CHECK-INST-ALIAS: csrci MIMPID, 1 +# aliases with uimm12 +# CHECK-INST-ALIAS: csrr t1, MIMPID +# CHECK-INST-ALIAS: csrw MIMPID, t2 +# CHECK-INST-ALIAS: csrs MIMPID, t2 +# CHECK-INST-ALIAS: csrc MIMPID, t2 +# CHECK-INST-ALIAS: csrwi MIMPID, 1 +# CHECK-INST-ALIAS: csrsi MIMPID, 1 +# CHECK-INST-ALIAS: csrci MIMPID, 1 +# name +csrrs t1, mimpid, x0 +csrrw x0, mimpid, t2 +csrrs x0, mimpid, t2 +csrrc x0, mimpid, t2 +csrrwi x0, mimpid, 1 +csrrsi x0, mimpid, 1 +csrrci x0, mimpid, 1 +# uimm12 +csrrs t1, 0xF13, x0 +csrrw x0, 0xF13, t2 +csrrs x0, 0xF13, t2 +csrrc x0, 0xF13, t2 +csrrwi x0, 0xF13, 1 +csrrsi x0, 0xF13, 1 +csrrci x0, 0xF13, 1 + +# mhartid +# name +# CHECK-INST: csrrs t1, MHARTID, zero +# CHECK-INST: csrrw zero, MHARTID, t2 +# CHECK-INST: csrrs zero, MHARTID, t2 +# CHECK-INST: csrrc zero, MHARTID, t2 +# CHECK-INST: csrrwi zero, MHARTID, 1 +# CHECK-INST: csrrsi zero, MHARTID, 1 +# CHECK-INST: csrrci zero, MHARTID, 1 +# uimm12 +# CHECK-INST: csrrs t1, MHARTID, zero +# CHECK-INST: csrrw zero, MHARTID, t2 +# CHECK-INST: csrrs zero, MHARTID, t2 +# CHECK-INST: csrrc zero, MHARTID, t2 +# CHECK-INST: csrrwi zero, MHARTID, 1 +# CHECK-INST: csrrsi zero, MHARTID, 1 +# CHECK-INST: csrrci zero, MHARTID, 1 +# aliases +# CHECK-INST-ALIAS: csrr t1, MHARTID +# CHECK-INST-ALIAS: csrw MHARTID, t2 +# CHECK-INST-ALIAS: csrs MHARTID, t2 +# CHECK-INST-ALIAS: csrc MHARTID, t2 +# CHECK-INST-ALIAS: csrwi MHARTID, 1 +# CHECK-INST-ALIAS: csrsi MHARTID, 1 +# CHECK-INST-ALIAS: csrci MHARTID, 1 +# aliases with uimm12 +# CHECK-INST-ALIAS: csrr t1, MHARTID +# CHECK-INST-ALIAS: csrw MHARTID, t2 +# CHECK-INST-ALIAS: csrs MHARTID, t2 +# CHECK-INST-ALIAS: csrc MHARTID, t2 +# CHECK-INST-ALIAS: csrwi MHARTID, 1 +# CHECK-INST-ALIAS: csrsi MHARTID, 1 +# CHECK-INST-ALIAS: csrci MHARTID, 1 +# name +csrrs t1, mhartid, x0 +csrrw x0, mhartid, t2 +csrrs x0, mhartid, t2 +csrrc x0, mhartid, t2 +csrrwi x0, mhartid, 1 +csrrsi x0, mhartid, 1 +csrrci x0, mhartid, 1 +# uimm12 +csrrs t1, 0xF14, x0 +csrrw x0, 0xF14, t2 +csrrs x0, 0xF14, t2 +csrrc x0, 0xF14, t2 +csrrwi x0, 0xF14, 1 +csrrsi x0, 0xF14, 1 +csrrci x0, 0xF14, 1 + +################################## +# Machine Trap Setup +################################## + +# mstatus +# name +# CHECK-INST: csrrs t1, MSTATUS, zero +# CHECK-INST: csrrw zero, MSTATUS, t2 +# CHECK-INST: csrrs zero, MSTATUS, t2 +# CHECK-INST: csrrc zero, MSTATUS, t2 +# CHECK-INST: csrrwi zero, MSTATUS, 1 +# CHECK-INST: csrrsi zero, MSTATUS, 1 +# CHECK-INST: csrrci zero, MSTATUS, 1 +# uimm12 +# CHECK-INST: csrrs t1, MSTATUS, zero +# CHECK-INST: csrrw zero, MSTATUS, t2 +# CHECK-INST: csrrs zero, MSTATUS, t2 +# CHECK-INST: csrrc zero, MSTATUS, t2 +# CHECK-INST: csrrwi zero, MSTATUS, 1 +# CHECK-INST: csrrsi zero, MSTATUS, 1 +# CHECK-INST: csrrci zero, MSTATUS, 1 +# aliases +# CHECK-INST-ALIAS: csrr t1, MSTATUS +# CHECK-INST-ALIAS: csrw MSTATUS, t2 +# CHECK-INST-ALIAS: csrs MSTATUS, t2 +# CHECK-INST-ALIAS: csrc MSTATUS, t2 +# CHECK-INST-ALIAS: csrwi MSTATUS, 1 +# CHECK-INST-ALIAS: csrsi MSTATUS, 1 +# CHECK-INST-ALIAS: csrci MSTATUS, 1 +# aliases with uimm12 +# CHECK-INST-ALIAS: csrr t1, MSTATUS +# CHECK-INST-ALIAS: csrw MSTATUS, t2 +# CHECK-INST-ALIAS: csrs MSTATUS, t2 +# CHECK-INST-ALIAS: csrc MSTATUS, t2 +# CHECK-INST-ALIAS: csrwi MSTATUS, 1 +# CHECK-INST-ALIAS: csrsi MSTATUS, 1 +# CHECK-INST-ALIAS: csrci MSTATUS, 1 +# name +csrrs t1, mstatus, x0 +csrrw x0, mstatus, t2 +csrrs x0, mstatus, t2 +csrrc x0, mstatus, t2 +csrrwi x0, mstatus, 1 +csrrsi x0, mstatus, 1 +csrrci x0, mstatus, 1 +# uimm12 +csrrs t1, 0x300, x0 +csrrw x0, 0x300, t2 +csrrs x0, 0x300, t2 +csrrc x0, 0x300, t2 +csrrwi x0, 0x300, 1 +csrrsi x0, 0x300, 1 +csrrci x0, 0x300, 1 + +# misa +# name +# CHECK-INST: csrrs t1, MISA, zero +# CHECK-INST: csrrw zero, MISA, t2 +# CHECK-INST: csrrs zero, MISA, t2 +# CHECK-INST: csrrc zero, MISA, t2 +# CHECK-INST: csrrwi zero, MISA, 1 +# CHECK-INST: csrrsi zero, MISA, 1 +# CHECK-INST: csrrci zero, MISA, 1 +# uimm12 +# CHECK-INST: csrrs t1, MISA, zero +# CHECK-INST: csrrw zero, MISA, t2 +# CHECK-INST: csrrs zero, MISA, t2 +# CHECK-INST: csrrc zero, MISA, t2 +# CHECK-INST: csrrwi zero, MISA, 1 +# CHECK-INST: csrrsi zero, MISA, 1 +# CHECK-INST: csrrci zero, MISA, 1 +# aliases +# CHECK-INST-ALIAS: csrr t1, MISA +# CHECK-INST-ALIAS: csrw MISA, t2 +# CHECK-INST-ALIAS: csrs MISA, t2 +# CHECK-INST-ALIAS: csrc MISA, t2 +# CHECK-INST-ALIAS: csrwi MISA, 1 +# CHECK-INST-ALIAS: csrsi MISA, 1 +# CHECK-INST-ALIAS: csrci MISA, 1 +# aliases with uimm12 +# CHECK-INST-ALIAS: csrr t1, MISA +# CHECK-INST-ALIAS: csrw MISA, t2 +# CHECK-INST-ALIAS: csrs MISA, t2 +# CHECK-INST-ALIAS: csrc MISA, t2 +# CHECK-INST-ALIAS: csrwi MISA, 1 +# CHECK-INST-ALIAS: csrsi MISA, 1 +# CHECK-INST-ALIAS: csrci MISA, 1 +# name +csrrs t1, misa, x0 +csrrw x0, misa, t2 +csrrs x0, misa, t2 +csrrc x0, misa, t2 +csrrwi x0, misa, 1 +csrrsi x0, misa, 1 +csrrci x0, misa, 1 +# uimm12 +csrrs t1, 0x301, x0 +csrrw x0, 0x301, t2 +csrrs x0, 0x301, t2 +csrrc x0, 0x301, t2 +csrrwi x0, 0x301, 1 +csrrsi x0, 0x301, 1 +csrrci x0, 0x301, 1 + +# medeleg +# name +# CHECK-INST: csrrs t1, MEDELEG, zero +# CHECK-INST: csrrw zero, MEDELEG, t2 +# CHECK-INST: csrrs zero, MEDELEG, t2 +# CHECK-INST: csrrc zero, MEDELEG, t2 +# CHECK-INST: csrrwi zero, MEDELEG, 1 +# CHECK-INST: csrrsi zero, MEDELEG, 1 +# CHECK-INST: csrrci zero, MEDELEG, 1 +# uimm12 +# CHECK-INST: csrrs t1, MEDELEG, zero +# CHECK-INST: csrrw zero, MEDELEG, t2 +# CHECK-INST: csrrs zero, MEDELEG, t2 +# CHECK-INST: csrrc zero, MEDELEG, t2 +# CHECK-INST: csrrwi zero, MEDELEG, 1 +# CHECK-INST: csrrsi zero, MEDELEG, 1 +# CHECK-INST: csrrci zero, MEDELEG, 1 +# aliases +# CHECK-INST-ALIAS: csrr t1, MEDELEG +# CHECK-INST-ALIAS: csrw MEDELEG, t2 +# CHECK-INST-ALIAS: csrs MEDELEG, t2 +# CHECK-INST-ALIAS: csrc MEDELEG, t2 +# CHECK-INST-ALIAS: csrwi MEDELEG, 1 +# CHECK-INST-ALIAS: csrsi MEDELEG, 1 +# CHECK-INST-ALIAS: csrci MEDELEG, 1 +# aliases with uimm12 +# CHECK-INST-ALIAS: csrr t1, MEDELEG +# CHECK-INST-ALIAS: csrw MEDELEG, t2 +# CHECK-INST-ALIAS: csrs MEDELEG, t2 +# CHECK-INST-ALIAS: csrc MEDELEG, t2 +# CHECK-INST-ALIAS: csrwi MEDELEG, 1 +# CHECK-INST-ALIAS: csrsi MEDELEG, 1 +# CHECK-INST-ALIAS: csrci MEDELEG, 1 +# name +csrrs t1, medeleg, x0 +csrrw x0, medeleg, t2 +csrrs x0, medeleg, t2 +csrrc x0, medeleg, t2 +csrrwi x0, medeleg, 1 +csrrsi x0, medeleg, 1 +csrrci x0, medeleg, 1 +# uimm12 +csrrs t1, 0x302, x0 +csrrw x0, 0x302, t2 +csrrs x0, 0x302, t2 +csrrc x0, 0x302, t2 +csrrwi x0, 0x302, 1 +csrrsi x0, 0x302, 1 +csrrci x0, 0x302, 1 +# aliases + +# mideleg +# name +# CHECK-INST: csrrs t1, MIDELEG, zero +# CHECK-INST: csrrw zero, MIDELEG, t2 +# CHECK-INST: csrrs zero, MIDELEG, t2 +# CHECK-INST: csrrc zero, MIDELEG, t2 +# CHECK-INST: csrrwi zero, MIDELEG, 1 +# CHECK-INST: csrrsi zero, MIDELEG, 1 +# CHECK-INST: csrrci zero, MIDELEG, 1 +# uimm12 +# CHECK-INST: csrrs t1, MIDELEG, zero +# CHECK-INST: csrrw zero, MIDELEG, t2 +# CHECK-INST: csrrs zero, MIDELEG, t2 +# CHECK-INST: csrrc zero, MIDELEG, t2 +# CHECK-INST: csrrwi zero, MIDELEG, 1 +# CHECK-INST: csrrsi zero, MIDELEG, 1 +# CHECK-INST: csrrci zero, MIDELEG, 1 +# aliases +# CHECK-INST-ALIAS: csrr t1, MIDELEG +# CHECK-INST-ALIAS: csrw MIDELEG, t2 +# CHECK-INST-ALIAS: csrs MIDELEG, t2 +# CHECK-INST-ALIAS: csrc MIDELEG, t2 +# CHECK-INST-ALIAS: csrwi MIDELEG, 1 +# CHECK-INST-ALIAS: csrsi MIDELEG, 1 +# CHECK-INST-ALIAS: csrci MIDELEG, 1 +# aliases with uimm12 +# CHECK-INST-ALIAS: csrr t1, MIDELEG +# CHECK-INST-ALIAS: csrw MIDELEG, t2 +# CHECK-INST-ALIAS: csrs MIDELEG, t2 +# CHECK-INST-ALIAS: csrc MIDELEG, t2 +# CHECK-INST-ALIAS: csrwi MIDELEG, 1 +# CHECK-INST-ALIAS: csrsi MIDELEG, 1 +# CHECK-INST-ALIAS: csrci MIDELEG, 1 +# name +csrrs t1, mideleg, x0 +csrrw x0, mideleg, t2 +csrrs x0, mideleg, t2 +csrrc x0, mideleg, t2 +csrrwi x0, mideleg, 1 +csrrsi x0, mideleg, 1 +csrrci x0, mideleg, 1 +# uimm12 +csrrs t1, 0x303, x0 +csrrw x0, 0x303, t2 +csrrs x0, 0x303, t2 +csrrc x0, 0x303, t2 +csrrwi x0, 0x303, 1 +csrrsi x0, 0x303, 1 +csrrci x0, 0x303, 1 + +# mie +# name +# CHECK-INST: csrrs t1, MIE, zero +# CHECK-INST: csrrw zero, MIE, t2 +# CHECK-INST: csrrs zero, MIE, t2 +# CHECK-INST: csrrc zero, MIE, t2 +# CHECK-INST: csrrwi zero, MIE, 1 +# CHECK-INST: csrrsi zero, MIE, 1 +# CHECK-INST: csrrci zero, MIE, 1 +# uimm12 +# CHECK-INST: csrrs t1, MIE, zero +# CHECK-INST: csrrw zero, MIE, t2 +# CHECK-INST: csrrs zero, MIE, t2 +# CHECK-INST: csrrc zero, MIE, t2 +# CHECK-INST: csrrwi zero, MIE, 1 +# CHECK-INST: csrrsi zero, MIE, 1 +# CHECK-INST: csrrci zero, MIE, 1 +# aliases +# CHECK-INST-ALIAS: csrr t1, MIE +# CHECK-INST-ALIAS: csrw MIE, t2 +# CHECK-INST-ALIAS: csrs MIE, t2 +# CHECK-INST-ALIAS: csrc MIE, t2 +# CHECK-INST-ALIAS: csrwi MIE, 1 +# CHECK-INST-ALIAS: csrsi MIE, 1 +# CHECK-INST-ALIAS: csrci MIE, 1 +# aliases with uimm12 +# CHECK-INST-ALIAS: csrr t1, MIE +# CHECK-INST-ALIAS: csrw MIE, t2 +# CHECK-INST-ALIAS: csrs MIE, t2 +# CHECK-INST-ALIAS: csrc MIE, t2 +# CHECK-INST-ALIAS: csrwi MIE, 1 +# CHECK-INST-ALIAS: csrsi MIE, 1 +# CHECK-INST-ALIAS: csrci MIE, 1 +# name +csrrs t1, mie, x0 +csrrw x0, mie, t2 +csrrs x0, mie, t2 +csrrc x0, mie, t2 +csrrwi x0, mie, 1 +csrrsi x0, mie, 1 +csrrci x0, mie, 1 +# uimm12 +csrrs t1, 0x304, x0 +csrrw x0, 0x304, t2 +csrrs x0, 0x304, t2 +csrrc x0, 0x304, t2 +csrrwi x0, 0x304, 1 +csrrsi x0, 0x304, 1 +csrrci x0, 0x304, 1 + +# mtvec +# name +# CHECK-INST: csrrs t1, MTVEC, zero +# CHECK-INST: csrrw zero, MTVEC, t2 +# CHECK-INST: csrrs zero, MTVEC, t2 +# CHECK-INST: csrrc zero, MTVEC, t2 +# CHECK-INST: csrrwi zero, MTVEC, 1 +# CHECK-INST: csrrsi zero, MTVEC, 1 +# CHECK-INST: csrrci zero, MTVEC, 1 +# uimm12 +# CHECK-INST: csrrs t1, MTVEC, zero +# CHECK-INST: csrrw zero, MTVEC, t2 +# CHECK-INST: csrrs zero, MTVEC, t2 +# CHECK-INST: csrrc zero, MTVEC, t2 +# CHECK-INST: csrrwi zero, MTVEC, 1 +# CHECK-INST: csrrsi zero, MTVEC, 1 +# CHECK-INST: csrrci zero, MTVEC, 1 +# aliases +# CHECK-INST-ALIAS: csrr t1, MTVEC +# CHECK-INST-ALIAS: csrw MTVEC, t2 +# CHECK-INST-ALIAS: csrs MTVEC, t2 +# CHECK-INST-ALIAS: csrc MTVEC, t2 +# CHECK-INST-ALIAS: csrwi MTVEC, 1 +# CHECK-INST-ALIAS: csrsi MTVEC, 1 +# CHECK-INST-ALIAS: csrci MTVEC, 1 +# aliases with uimm12 +# CHECK-INST-ALIAS: csrr t1, MTVEC +# CHECK-INST-ALIAS: csrw MTVEC, t2 +# CHECK-INST-ALIAS: csrs MTVEC, t2 +# CHECK-INST-ALIAS: csrc MTVEC, t2 +# CHECK-INST-ALIAS: csrwi MTVEC, 1 +# CHECK-INST-ALIAS: csrsi MTVEC, 1 +# CHECK-INST-ALIAS: csrci MTVEC, 1 +# name +csrrs t1, mtvec, x0 +csrrw x0, mtvec, t2 +csrrs x0, mtvec, t2 +csrrc x0, mtvec, t2 +csrrwi x0, mtvec, 1 +csrrsi x0, mtvec, 1 +csrrci x0, mtvec, 1 +# uimm12 +csrrs t1, 0x305, x0 +csrrw x0, 0x305, t2 +csrrs x0, 0x305, t2 +csrrc x0, 0x305, t2 +csrrwi x0, 0x305, 1 +csrrsi x0, 0x305, 1 +csrrci x0, 0x305, 1 + +# mcounteren +# name +# CHECK-INST: csrrs t1, MCOUNTEREN, zero +# CHECK-INST: csrrw zero, MCOUNTEREN, t2 +# CHECK-INST: csrrs zero, MCOUNTEREN, t2 +# CHECK-INST: csrrc zero, MCOUNTEREN, t2 +# CHECK-INST: csrrwi zero, MCOUNTEREN, 1 +# CHECK-INST: csrrsi zero, MCOUNTEREN, 1 +# CHECK-INST: csrrci zero, MCOUNTEREN, 1 +# uimm12 +# CHECK-INST: csrrs t1, MCOUNTEREN, zero +# CHECK-INST: csrrw zero, MCOUNTEREN, t2 +# CHECK-INST: csrrs zero, MCOUNTEREN, t2 +# CHECK-INST: csrrc zero, MCOUNTEREN, t2 +# CHECK-INST: csrrwi zero, MCOUNTEREN, 1 +# CHECK-INST: csrrsi zero, MCOUNTEREN, 1 +# CHECK-INST: csrrci zero, MCOUNTEREN, 1 +# aliases +# CHECK-INST-ALIAS: csrr t1, MCOUNTEREN +# CHECK-INST-ALIAS: csrw MCOUNTEREN, t2 +# CHECK-INST-ALIAS: csrs MCOUNTEREN, t2 +# CHECK-INST-ALIAS: csrc MCOUNTEREN, t2 +# CHECK-INST-ALIAS: csrwi MCOUNTEREN, 1 +# CHECK-INST-ALIAS: csrsi MCOUNTEREN, 1 +# CHECK-INST-ALIAS: csrci MCOUNTEREN, 1 +# aliases with uimm12 +# CHECK-INST-ALIAS: csrr t1, MCOUNTEREN +# CHECK-INST-ALIAS: csrw MCOUNTEREN, t2 +# CHECK-INST-ALIAS: csrs MCOUNTEREN, t2 +# CHECK-INST-ALIAS: csrc MCOUNTEREN, t2 +# CHECK-INST-ALIAS: csrwi MCOUNTEREN, 1 +# CHECK-INST-ALIAS: csrsi MCOUNTEREN, 1 +# CHECK-INST-ALIAS: csrci MCOUNTEREN, 1 +# name +csrrs t1, mcounteren, x0 +csrrw x0, mcounteren, t2 +csrrs x0, mcounteren, t2 +csrrc x0, mcounteren, t2 +csrrwi x0, mcounteren, 1 +csrrsi x0, mcounteren, 1 +csrrci x0, mcounteren, 1 +# uimm12 +csrrs t1, 0x306, x0 +csrrw x0, 0x306, t2 +csrrs x0, 0x306, t2 +csrrc x0, 0x306, t2 +csrrwi x0, 0x306, 1 +csrrsi x0, 0x306, 1 +csrrci x0, 0x306, 1 + +# mscratch +# name +# CHECK-INST: csrrs t1, MSCRATCH, zero +# CHECK-INST: csrrw zero, MSCRATCH, t2 +# CHECK-INST: csrrs zero, MSCRATCH, t2 +# CHECK-INST: csrrc zero, MSCRATCH, t2 +# CHECK-INST: csrrwi zero, MSCRATCH, 1 +# CHECK-INST: csrrsi zero, MSCRATCH, 1 +# CHECK-INST: csrrci zero, MSCRATCH, 1 +# uimm12 +# CHECK-INST: csrrs t1, MSCRATCH, zero +# CHECK-INST: csrrw zero, MSCRATCH, t2 +# CHECK-INST: csrrs zero, MSCRATCH, t2 +# CHECK-INST: csrrc zero, MSCRATCH, t2 +# CHECK-INST: csrrwi zero, MSCRATCH, 1 +# CHECK-INST: csrrsi zero, MSCRATCH, 1 +# CHECK-INST: csrrci zero, MSCRATCH, 1 +# aliases +# CHECK-INST-ALIAS: csrr t1, MSCRATCH +# CHECK-INST-ALIAS: csrw MSCRATCH, t2 +# CHECK-INST-ALIAS: csrs MSCRATCH, t2 +# CHECK-INST-ALIAS: csrc MSCRATCH, t2 +# CHECK-INST-ALIAS: csrwi MSCRATCH, 1 +# CHECK-INST-ALIAS: csrsi MSCRATCH, 1 +# CHECK-INST-ALIAS: csrci MSCRATCH, 1 +# aliases with uimm12 +# CHECK-INST-ALIAS: csrr t1, MSCRATCH +# CHECK-INST-ALIAS: csrw MSCRATCH, t2 +# CHECK-INST-ALIAS: csrs MSCRATCH, t2 +# CHECK-INST-ALIAS: csrc MSCRATCH, t2 +# CHECK-INST-ALIAS: csrwi MSCRATCH, 1 +# CHECK-INST-ALIAS: csrsi MSCRATCH, 1 +# CHECK-INST-ALIAS: csrci MSCRATCH, 1 +# name +csrrs t1, mscratch, x0 +csrrw x0, mscratch, t2 +csrrs x0, mscratch, t2 +csrrc x0, mscratch, t2 +csrrwi x0, mscratch, 1 +csrrsi x0, mscratch, 1 +csrrci x0, mscratch, 1 +# uimm12 +csrrs t1, 0x340, x0 +csrrw x0, 0x340, t2 +csrrs x0, 0x340, t2 +csrrc x0, 0x340, t2 +csrrwi x0, 0x340, 1 +csrrsi x0, 0x340, 1 +csrrci x0, 0x340, 1 + +# mepc +# name +# CHECK-INST: csrrs t1, MEPC, zero +# CHECK-INST: csrrw zero, MEPC, t2 +# CHECK-INST: csrrs zero, MEPC, t2 +# CHECK-INST: csrrc zero, MEPC, t2 +# CHECK-INST: csrrwi zero, MEPC, 1 +# CHECK-INST: csrrsi zero, MEPC, 1 +# CHECK-INST: csrrci zero, MEPC, 1 +# uimm12 +# CHECK-INST: csrrs t1, MEPC, zero +# CHECK-INST: csrrw zero, MEPC, t2 +# CHECK-INST: csrrs zero, MEPC, t2 +# CHECK-INST: csrrc zero, MEPC, t2 +# CHECK-INST: csrrwi zero, MEPC, 1 +# CHECK-INST: csrrsi zero, MEPC, 1 +# CHECK-INST: csrrci zero, MEPC, 1 +# aliases +# CHECK-INST-ALIAS: csrr t1, MEPC +# CHECK-INST-ALIAS: csrw MEPC, t2 +# CHECK-INST-ALIAS: csrs MEPC, t2 +# CHECK-INST-ALIAS: csrc MEPC, t2 +# CHECK-INST-ALIAS: csrwi MEPC, 1 +# CHECK-INST-ALIAS: csrsi MEPC, 1 +# CHECK-INST-ALIAS: csrci MEPC, 1 +# aliases with uimm12 +# CHECK-INST-ALIAS: csrr t1, MEPC +# CHECK-INST-ALIAS: csrw MEPC, t2 +# CHECK-INST-ALIAS: csrs MEPC, t2 +# CHECK-INST-ALIAS: csrc MEPC, t2 +# CHECK-INST-ALIAS: csrwi MEPC, 1 +# CHECK-INST-ALIAS: csrsi MEPC, 1 +# CHECK-INST-ALIAS: csrci MEPC, 1 +# name +csrrs t1, mepc, x0 +csrrw x0, mepc, t2 +csrrs x0, mepc, t2 +csrrc x0, mepc, t2 +csrrwi x0, mepc, 1 +csrrsi x0, mepc, 1 +csrrci x0, mepc, 1 +# uimm12 +csrrs t1, 0x341, x0 +csrrw x0, 0x341, t2 +csrrs x0, 0x341, t2 +csrrc x0, 0x341, t2 +csrrwi x0, 0x341, 1 +csrrsi x0, 0x341, 1 +csrrci x0, 0x341, 1 + +# mcause +# name +# CHECK-INST: csrrs t1, MCAUSE, zero +# CHECK-INST: csrrw zero, MCAUSE, t2 +# CHECK-INST: csrrs zero, MCAUSE, t2 +# CHECK-INST: csrrc zero, MCAUSE, t2 +# CHECK-INST: csrrwi zero, MCAUSE, 1 +# CHECK-INST: csrrsi zero, MCAUSE, 1 +# CHECK-INST: csrrci zero, MCAUSE, 1 +# uimm12 +# CHECK-INST: csrrs t1, MCAUSE, zero +# CHECK-INST: csrrw zero, MCAUSE, t2 +# CHECK-INST: csrrs zero, MCAUSE, t2 +# CHECK-INST: csrrc zero, MCAUSE, t2 +# CHECK-INST: csrrwi zero, MCAUSE, 1 +# CHECK-INST: csrrsi zero, MCAUSE, 1 +# CHECK-INST: csrrci zero, MCAUSE, 1 +# aliases +# CHECK-INST-ALIAS: csrr t1, MCAUSE +# CHECK-INST-ALIAS: csrw MCAUSE, t2 +# CHECK-INST-ALIAS: csrs MCAUSE, t2 +# CHECK-INST-ALIAS: csrc MCAUSE, t2 +# CHECK-INST-ALIAS: csrwi MCAUSE, 1 +# CHECK-INST-ALIAS: csrsi MCAUSE, 1 +# CHECK-INST-ALIAS: csrci MCAUSE, 1 +# aliases with uimm12 +# CHECK-INST-ALIAS: csrr t1, MCAUSE +# CHECK-INST-ALIAS: csrw MCAUSE, t2 +# CHECK-INST-ALIAS: csrs MCAUSE, t2 +# CHECK-INST-ALIAS: csrc MCAUSE, t2 +# CHECK-INST-ALIAS: csrwi MCAUSE, 1 +# CHECK-INST-ALIAS: csrsi MCAUSE, 1 +# CHECK-INST-ALIAS: csrci MCAUSE, 1 +# name +csrrs t1, mcause, x0 +csrrw x0, mcause, t2 +csrrs x0, mcause, t2 +csrrc x0, mcause, t2 +csrrwi x0, mcause, 1 +csrrsi x0, mcause, 1 +csrrci x0, mcause, 1 +# uimm12 +csrrs t1, 0x342, x0 +csrrw x0, 0x342, t2 +csrrs x0, 0x342, t2 +csrrc x0, 0x342, t2 +csrrwi x0, 0x342, 1 +csrrsi x0, 0x342, 1 +csrrci x0, 0x342, 1 + +# mtval +# name +# CHECK-INST: csrrs t1, MTVAL, zero +# CHECK-INST: csrrw zero, MTVAL, t2 +# CHECK-INST: csrrs zero, MTVAL, t2 +# CHECK-INST: csrrc zero, MTVAL, t2 +# CHECK-INST: csrrwi zero, MTVAL, 1 +# CHECK-INST: csrrsi zero, MTVAL, 1 +# CHECK-INST: csrrci zero, MTVAL, 1 +# uimm12 +# CHECK-INST: csrrs t1, MTVAL, zero +# CHECK-INST: csrrw zero, MTVAL, t2 +# CHECK-INST: csrrs zero, MTVAL, t2 +# CHECK-INST: csrrc zero, MTVAL, t2 +# CHECK-INST: csrrwi zero, MTVAL, 1 +# CHECK-INST: csrrsi zero, MTVAL, 1 +# CHECK-INST: csrrci zero, MTVAL, 1 +# aliases +# CHECK-INST-ALIAS: csrr t1, MTVAL +# CHECK-INST-ALIAS: csrw MTVAL, t2 +# CHECK-INST-ALIAS: csrs MTVAL, t2 +# CHECK-INST-ALIAS: csrc MTVAL, t2 +# CHECK-INST-ALIAS: csrwi MTVAL, 1 +# CHECK-INST-ALIAS: csrsi MTVAL, 1 +# CHECK-INST-ALIAS: csrci MTVAL, 1 +# aliases with uimm12 +# CHECK-INST-ALIAS: csrr t1, MTVAL +# CHECK-INST-ALIAS: csrw MTVAL, t2 +# CHECK-INST-ALIAS: csrs MTVAL, t2 +# CHECK-INST-ALIAS: csrc MTVAL, t2 +# CHECK-INST-ALIAS: csrwi MTVAL, 1 +# CHECK-INST-ALIAS: csrsi MTVAL, 1 +# CHECK-INST-ALIAS: csrci MTVAL, 1 +# name +csrrs t1, mtval, x0 +csrrw x0, mtval, t2 +csrrs x0, mtval, t2 +csrrc x0, mtval, t2 +csrrwi x0, mtval, 1 +csrrsi x0, mtval, 1 +csrrci x0, mtval, 1 +# uimm12 +csrrs t1, 0x343, x0 +csrrw x0, 0x343, t2 +csrrs x0, 0x343, t2 +csrrc x0, 0x343, t2 +csrrwi x0, 0x343, 1 +csrrsi x0, 0x343, 1 +csrrci x0, 0x343, 1 + +# mip +# name +# CHECK-INST: csrrs t1, MIP, zero +# CHECK-INST: csrrw zero, MIP, t2 +# CHECK-INST: csrrs zero, MIP, t2 +# CHECK-INST: csrrc zero, MIP, t2 +# CHECK-INST: csrrwi zero, MIP, 1 +# CHECK-INST: csrrsi zero, MIP, 1 +# CHECK-INST: csrrci zero, MIP, 1 +# uimm12 +# CHECK-INST: csrrs t1, MIP, zero +# CHECK-INST: csrrw zero, MIP, t2 +# CHECK-INST: csrrs zero, MIP, t2 +# CHECK-INST: csrrc zero, MIP, t2 +# CHECK-INST: csrrwi zero, MIP, 1 +# CHECK-INST: csrrsi zero, MIP, 1 +# CHECK-INST: csrrci zero, MIP, 1 +# aliases +# CHECK-INST-ALIAS: csrr t1, MIP +# CHECK-INST-ALIAS: csrw MIP, t2 +# CHECK-INST-ALIAS: csrs MIP, t2 +# CHECK-INST-ALIAS: csrc MIP, t2 +# CHECK-INST-ALIAS: csrwi MIP, 1 +# CHECK-INST-ALIAS: csrsi MIP, 1 +# CHECK-INST-ALIAS: csrci MIP, 1 +# aliases with uimm12 +# CHECK-INST-ALIAS: csrr t1, MIP +# CHECK-INST-ALIAS: csrw MIP, t2 +# CHECK-INST-ALIAS: csrs MIP, t2 +# CHECK-INST-ALIAS: csrc MIP, t2 +# CHECK-INST-ALIAS: csrwi MIP, 1 +# CHECK-INST-ALIAS: csrsi MIP, 1 +# CHECK-INST-ALIAS: csrci MIP, 1 +# name +csrrs t1, mip, x0 +csrrw x0, mip, t2 +csrrs x0, mip, t2 +csrrc x0, mip, t2 +csrrwi x0, mip, 1 +csrrsi x0, mip, 1 +csrrci x0, mip, 1 +# uimm12 +csrrs t1, 0x344, x0 +csrrw x0, 0x344, t2 +csrrs x0, 0x344, t2 +csrrc x0, 0x344, t2 +csrrwi x0, 0x344, 1 +csrrsi x0, 0x344, 1 +csrrci x0, 0x344, 1 + +###################################### +# Machine Protection and Translation +###################################### +# FIXME: to add PMP config registers + +###################################### +# Machine Counter and Timers +###################################### +# mcycle +# name +# CHECK-INST: csrrs t1, MCYCLE, zero +# CHECK-INST: csrrw zero, MCYCLE, t2 +# CHECK-INST: csrrs zero, MCYCLE, t2 +# CHECK-INST: csrrc zero, MCYCLE, t2 +# CHECK-INST: csrrwi zero, MCYCLE, 1 +# CHECK-INST: csrrsi zero, MCYCLE, 1 +# CHECK-INST: csrrci zero, MCYCLE, 1 +# uimm12 +# CHECK-INST: csrrs t1, MCYCLE, zero +# CHECK-INST: csrrw zero, MCYCLE, t2 +# CHECK-INST: csrrs zero, MCYCLE, t2 +# CHECK-INST: csrrc zero, MCYCLE, t2 +# CHECK-INST: csrrwi zero, MCYCLE, 1 +# CHECK-INST: csrrsi zero, MCYCLE, 1 +# CHECK-INST: csrrci zero, MCYCLE, 1 +# aliases +# CHECK-INST-ALIAS: csrr t1, MCYCLE +# CHECK-INST-ALIAS: csrw MCYCLE, t2 +# CHECK-INST-ALIAS: csrs MCYCLE, t2 +# CHECK-INST-ALIAS: csrc MCYCLE, t2 +# CHECK-INST-ALIAS: csrwi MCYCLE, 1 +# CHECK-INST-ALIAS: csrsi MCYCLE, 1 +# CHECK-INST-ALIAS: csrci MCYCLE, 1 +# aliases with uimm12 +# CHECK-INST-ALIAS: csrr t1, MCYCLE +# CHECK-INST-ALIAS: csrw MCYCLE, t2 +# CHECK-INST-ALIAS: csrs MCYCLE, t2 +# CHECK-INST-ALIAS: csrc MCYCLE, t2 +# CHECK-INST-ALIAS: csrwi MCYCLE, 1 +# CHECK-INST-ALIAS: csrsi MCYCLE, 1 +# CHECK-INST-ALIAS: csrci MCYCLE, 1 +# name +csrrs t1, mcycle, x0 +csrrw x0, mcycle, t2 +csrrs x0, mcycle, t2 +csrrc x0, mcycle, t2 +csrrwi x0, mcycle, 1 +csrrsi x0, mcycle, 1 +csrrci x0, mcycle, 1 +# uimm12 +csrrs t1, 0xB00, x0 +csrrw x0, 0xB00, t2 +csrrs x0, 0xB00, t2 +csrrc x0, 0xB00, t2 +csrrwi x0, 0xB00, 1 +csrrsi x0, 0xB00, 1 +csrrci x0, 0xB00, 1 + +# minstret +# name +# CHECK-INST: csrrs t1, MINSTRET, zero +# CHECK-INST: csrrw zero, MINSTRET, t2 +# CHECK-INST: csrrs zero, MINSTRET, t2 +# CHECK-INST: csrrc zero, MINSTRET, t2 +# CHECK-INST: csrrwi zero, MINSTRET, 1 +# CHECK-INST: csrrsi zero, MINSTRET, 1 +# CHECK-INST: csrrci zero, MINSTRET, 1 +# uimm12 +# CHECK-INST: csrrs t1, MINSTRET, zero +# CHECK-INST: csrrw zero, MINSTRET, t2 +# CHECK-INST: csrrs zero, MINSTRET, t2 +# CHECK-INST: csrrc zero, MINSTRET, t2 +# CHECK-INST: csrrwi zero, MINSTRET, 1 +# CHECK-INST: csrrsi zero, MINSTRET, 1 +# CHECK-INST: csrrci zero, MINSTRET, 1 +# aliases +# CHECK-INST-ALIAS: csrr t1, MINSTRET +# CHECK-INST-ALIAS: csrw MINSTRET, t2 +# CHECK-INST-ALIAS: csrs MINSTRET, t2 +# CHECK-INST-ALIAS: csrc MINSTRET, t2 +# CHECK-INST-ALIAS: csrwi MINSTRET, 1 +# CHECK-INST-ALIAS: csrsi MINSTRET, 1 +# CHECK-INST-ALIAS: csrci MINSTRET, 1 +# aliases with uimm12 +# CHECK-INST-ALIAS: csrr t1, MINSTRET +# CHECK-INST-ALIAS: csrw MINSTRET, t2 +# CHECK-INST-ALIAS: csrs MINSTRET, t2 +# CHECK-INST-ALIAS: csrc MINSTRET, t2 +# CHECK-INST-ALIAS: csrwi MINSTRET, 1 +# CHECK-INST-ALIAS: csrsi MINSTRET, 1 +# CHECK-INST-ALIAS: csrci MINSTRET, 1 +# name +csrrs t1, minstret, x0 +csrrw x0, minstret, t2 +csrrs x0, minstret, t2 +csrrc x0, minstret, t2 +csrrwi x0, minstret, 1 +csrrsi x0, minstret, 1 +csrrci x0, minstret, 1 +# uimm12 +csrrs t1, 0xB02, x0 +csrrw x0, 0xB02, t2 +csrrs x0, 0xB02, t2 +csrrc x0, 0xB02, t2 +csrrwi x0, 0xB02, 1 +csrrsi x0, 0xB02, 1 +csrrci x0, 0xB02, 1 + +# FIXME mhpmconter +# FIXME mycleh +# FIXME minstreth +# FIXME mhpcounterh + +###################################### +# Machine Counter Setup +###################################### +# FIXME: add mhpmevent 3 .. 31 + +###################################################### +# Debug and Trace Registers (shared with Debug Mode) +###################################################### +# tselect +# name +# CHECK-INST: csrrs t1, TSELECT, zero +# CHECK-INST: csrrw zero, TSELECT, t2 +# CHECK-INST: csrrs zero, TSELECT, t2 +# CHECK-INST: csrrc zero, TSELECT, t2 +# CHECK-INST: csrrwi zero, TSELECT, 1 +# CHECK-INST: csrrsi zero, TSELECT, 1 +# CHECK-INST: csrrci zero, TSELECT, 1 +# uimm12 +# CHECK-INST: csrrs t1, TSELECT, zero +# CHECK-INST: csrrw zero, TSELECT, t2 +# CHECK-INST: csrrs zero, TSELECT, t2 +# CHECK-INST: csrrc zero, TSELECT, t2 +# CHECK-INST: csrrwi zero, TSELECT, 1 +# CHECK-INST: csrrsi zero, TSELECT, 1 +# CHECK-INST: csrrci zero, TSELECT, 1 +# aliases +# CHECK-INST-ALIAS: csrr t1, TSELECT +# CHECK-INST-ALIAS: csrw TSELECT, t2 +# CHECK-INST-ALIAS: csrs TSELECT, t2 +# CHECK-INST-ALIAS: csrc TSELECT, t2 +# CHECK-INST-ALIAS: csrwi TSELECT, 1 +# CHECK-INST-ALIAS: csrsi TSELECT, 1 +# CHECK-INST-ALIAS: csrci TSELECT, 1 +# aliases with uimm12 +# CHECK-INST-ALIAS: csrr t1, TSELECT +# CHECK-INST-ALIAS: csrw TSELECT, t2 +# CHECK-INST-ALIAS: csrs TSELECT, t2 +# CHECK-INST-ALIAS: csrc TSELECT, t2 +# CHECK-INST-ALIAS: csrwi TSELECT, 1 +# CHECK-INST-ALIAS: csrsi TSELECT, 1 +# CHECK-INST-ALIAS: csrci TSELECT, 1 +# name +csrrs t1, tselect, x0 +csrrw x0, tselect, t2 +csrrs x0, tselect, t2 +csrrc x0, tselect, t2 +csrrwi x0, tselect, 1 +csrrsi x0, tselect, 1 +csrrci x0, tselect, 1 +# uimm12 +csrrs t1, 0x7A0, x0 +csrrw x0, 0x7A0, t2 +csrrs x0, 0x7A0, t2 +csrrc x0, 0x7A0, t2 +csrrwi x0, 0x7A0, 1 +csrrsi x0, 0x7A0, 1 +csrrci x0, 0x7A0, 1 + +# tdata1 +# name +# CHECK-INST: csrrs t1, TDATA1, zero +# CHECK-INST: csrrw zero, TDATA1, t2 +# CHECK-INST: csrrs zero, TDATA1, t2 +# CHECK-INST: csrrc zero, TDATA1, t2 +# CHECK-INST: csrrwi zero, TDATA1, 1 +# CHECK-INST: csrrsi zero, TDATA1, 1 +# CHECK-INST: csrrci zero, TDATA1, 1 +# uimm12 +# CHECK-INST: csrrs t1, TDATA1, zero +# CHECK-INST: csrrw zero, TDATA1, t2 +# CHECK-INST: csrrs zero, TDATA1, t2 +# CHECK-INST: csrrc zero, TDATA1, t2 +# CHECK-INST: csrrwi zero, TDATA1, 1 +# CHECK-INST: csrrsi zero, TDATA1, 1 +# CHECK-INST: csrrci zero, TDATA1, 1 +# aliases +# CHECK-INST-ALIAS: csrr t1, TDATA1 +# CHECK-INST-ALIAS: csrw TDATA1, t2 +# CHECK-INST-ALIAS: csrs TDATA1, t2 +# CHECK-INST-ALIAS: csrc TDATA1, t2 +# CHECK-INST-ALIAS: csrwi TDATA1, 1 +# CHECK-INST-ALIAS: csrsi TDATA1, 1 +# CHECK-INST-ALIAS: csrci TDATA1, 1 +# aliases with uimm12 +# CHECK-INST-ALIAS: csrr t1, TDATA1 +# CHECK-INST-ALIAS: csrw TDATA1, t2 +# CHECK-INST-ALIAS: csrs TDATA1, t2 +# CHECK-INST-ALIAS: csrc TDATA1, t2 +# CHECK-INST-ALIAS: csrwi TDATA1, 1 +# CHECK-INST-ALIAS: csrsi TDATA1, 1 +# CHECK-INST-ALIAS: csrci TDATA1, 1 +# name +csrrs t1, tdata1, x0 +csrrw x0, tdata1, t2 +csrrs x0, tdata1, t2 +csrrc x0, tdata1, t2 +csrrwi x0, tdata1, 1 +csrrsi x0, tdata1, 1 +csrrci x0, tdata1, 1 +# uimm12 +csrrs t1, 0x7A1, x0 +csrrw x0, 0x7A1, t2 +csrrs x0, 0x7A1, t2 +csrrc x0, 0x7A1, t2 +csrrwi x0, 0x7A1, 1 +csrrsi x0, 0x7A1, 1 +csrrci x0, 0x7A1, 1 + +# tdata2 +# name +# CHECK-INST: csrrs t1, TDATA2, zero +# CHECK-INST: csrrw zero, TDATA2, t2 +# CHECK-INST: csrrs zero, TDATA2, t2 +# CHECK-INST: csrrc zero, TDATA2, t2 +# CHECK-INST: csrrwi zero, TDATA2, 1 +# CHECK-INST: csrrsi zero, TDATA2, 1 +# CHECK-INST: csrrci zero, TDATA2, 1 +# uimm12 +# CHECK-INST: csrrs t1, TDATA2, zero +# CHECK-INST: csrrw zero, TDATA2, t2 +# CHECK-INST: csrrs zero, TDATA2, t2 +# CHECK-INST: csrrc zero, TDATA2, t2 +# CHECK-INST: csrrwi zero, TDATA2, 1 +# CHECK-INST: csrrsi zero, TDATA2, 1 +# CHECK-INST: csrrci zero, TDATA2, 1 +# aliases +# CHECK-INST-ALIAS: csrr t1, TDATA2 +# CHECK-INST-ALIAS: csrw TDATA2, t2 +# CHECK-INST-ALIAS: csrs TDATA2, t2 +# CHECK-INST-ALIAS: csrc TDATA2, t2 +# CHECK-INST-ALIAS: csrwi TDATA2, 1 +# CHECK-INST-ALIAS: csrsi TDATA2, 1 +# CHECK-INST-ALIAS: csrci TDATA2, 1 +# aliases with uimm12 +# CHECK-INST-ALIAS: csrr t1, TDATA2 +# CHECK-INST-ALIAS: csrw TDATA2, t2 +# CHECK-INST-ALIAS: csrs TDATA2, t2 +# CHECK-INST-ALIAS: csrc TDATA2, t2 +# CHECK-INST-ALIAS: csrwi TDATA2, 1 +# CHECK-INST-ALIAS: csrsi TDATA2, 1 +# CHECK-INST-ALIAS: csrci TDATA2, 1 +# name +csrrs t1, tdata2, x0 +csrrw x0, tdata2, t2 +csrrs x0, tdata2, t2 +csrrc x0, tdata2, t2 +csrrwi x0, tdata2, 1 +csrrsi x0, tdata2, 1 +csrrci x0, tdata2, 1 +# uimm12 +csrrs t1, 0x7A2, x0 +csrrw x0, 0x7A2, t2 +csrrs x0, 0x7A2, t2 +csrrc x0, 0x7A2, t2 +csrrwi x0, 0x7A2, 1 +csrrsi x0, 0x7A2, 1 +csrrci x0, 0x7A2, 1 + +#tdata3 +# name +# CHECK-INST: csrrs t1, TDATA3, zero +# CHECK-INST: csrrw zero, TDATA3, t2 +# CHECK-INST: csrrs zero, TDATA3, t2 +# CHECK-INST: csrrc zero, TDATA3, t2 +# CHECK-INST: csrrwi zero, TDATA3, 1 +# CHECK-INST: csrrsi zero, TDATA3, 1 +# CHECK-INST: csrrci zero, TDATA3, 1 +# uimm12 +# CHECK-INST: csrrs t1, TDATA3, zero +# CHECK-INST: csrrw zero, TDATA3, t2 +# CHECK-INST: csrrs zero, TDATA3, t2 +# CHECK-INST: csrrc zero, TDATA3, t2 +# CHECK-INST: csrrwi zero, TDATA3, 1 +# CHECK-INST: csrrsi zero, TDATA3, 1 +# CHECK-INST: csrrci zero, TDATA3, 1 +# aliases +# CHECK-INST-ALIAS: csrr t1, TDATA3 +# CHECK-INST-ALIAS: csrw TDATA3, t2 +# CHECK-INST-ALIAS: csrs TDATA3, t2 +# CHECK-INST-ALIAS: csrc TDATA3, t2 +# CHECK-INST-ALIAS: csrwi TDATA3, 1 +# CHECK-INST-ALIAS: csrsi TDATA3, 1 +# CHECK-INST-ALIAS: csrci TDATA3, 1 +# aliases with uimm12 +# CHECK-INST-ALIAS: csrr t1, TDATA3 +# CHECK-INST-ALIAS: csrw TDATA3, t2 +# CHECK-INST-ALIAS: csrs TDATA3, t2 +# CHECK-INST-ALIAS: csrc TDATA3, t2 +# CHECK-INST-ALIAS: csrwi TDATA3, 1 +# CHECK-INST-ALIAS: csrsi TDATA3, 1 +# CHECK-INST-ALIAS: csrci TDATA3, 1 +# name +csrrs t1, tdata3, x0 +csrrw x0, tdata3, t2 +csrrs x0, tdata3, t2 +csrrc x0, tdata3, t2 +csrrwi x0, tdata3, 1 +csrrsi x0, tdata3, 1 +csrrci x0, tdata3, 1 +# uimm12 +csrrs t1, 0x7A3, x0 +csrrw x0, 0x7A3, t2 +csrrs x0, 0x7A3, t2 +csrrc x0, 0x7A3, t2 +csrrwi x0, 0x7A3, 1 +csrrsi x0, 0x7A3, 1 +csrrci x0, 0x7A3, 1 +# aliases + +####################### +# Debug Mode Registers +######################## +# dcsr +# name +# CHECK-INST: csrrs t1, DCSR, zero +# CHECK-INST: csrrw zero, DCSR, t2 +# CHECK-INST: csrrs zero, DCSR, t2 +# CHECK-INST: csrrc zero, DCSR, t2 +# CHECK-INST: csrrwi zero, DCSR, 1 +# CHECK-INST: csrrsi zero, DCSR, 1 +# CHECK-INST: csrrci zero, DCSR, 1 +# uimm12 +# CHECK-INST: csrrs t1, DCSR, zero +# CHECK-INST: csrrw zero, DCSR, t2 +# CHECK-INST: csrrs zero, DCSR, t2 +# CHECK-INST: csrrc zero, DCSR, t2 +# CHECK-INST: csrrwi zero, DCSR, 1 +# CHECK-INST: csrrsi zero, DCSR, 1 +# CHECK-INST: csrrci zero, DCSR, 1 +# aliases +# CHECK-INST-ALIAS: csrr t1, DCSR +# CHECK-INST-ALIAS: csrw DCSR, t2 +# CHECK-INST-ALIAS: csrs DCSR, t2 +# CHECK-INST-ALIAS: csrc DCSR, t2 +# CHECK-INST-ALIAS: csrwi DCSR, 1 +# CHECK-INST-ALIAS: csrsi DCSR, 1 +# CHECK-INST-ALIAS: csrci DCSR, 1 +# aliases with uimm12 +# CHECK-INST-ALIAS: csrr t1, DCSR +# CHECK-INST-ALIAS: csrw DCSR, t2 +# CHECK-INST-ALIAS: csrs DCSR, t2 +# CHECK-INST-ALIAS: csrc DCSR, t2 +# CHECK-INST-ALIAS: csrwi DCSR, 1 +# CHECK-INST-ALIAS: csrsi DCSR, 1 +# CHECK-INST-ALIAS: csrci DCSR, 1 +# name +csrrs t1, dcsr, x0 +csrrw x0, dcsr, t2 +csrrs x0, dcsr, t2 +csrrc x0, dcsr, t2 +csrrwi x0, dcsr, 1 +csrrsi x0, dcsr, 1 +csrrci x0, dcsr, 1 +# uimm12 +csrrs t1, 0x7B0, x0 +csrrw x0, 0x7B0, t2 +csrrs x0, 0x7B0, t2 +csrrc x0, 0x7B0, t2 +csrrwi x0, 0x7B0, 1 +csrrsi x0, 0x7B0, 1 +csrrci x0, 0x7B0, 1 +# aliases + +# dpc +# name +# CHECK-INST: csrrs t1, DPC, zero +# CHECK-INST: csrrw zero, DPC, t2 +# CHECK-INST: csrrs zero, DPC, t2 +# CHECK-INST: csrrc zero, DPC, t2 +# CHECK-INST: csrrwi zero, DPC, 1 +# CHECK-INST: csrrsi zero, DPC, 1 +# CHECK-INST: csrrci zero, DPC, 1 +# uimm12 +# CHECK-INST: csrrs t1, DPC, zero +# CHECK-INST: csrrw zero, DPC, t2 +# CHECK-INST: csrrs zero, DPC, t2 +# CHECK-INST: csrrc zero, DPC, t2 +# CHECK-INST: csrrwi zero, DPC, 1 +# CHECK-INST: csrrsi zero, DPC, 1 +# CHECK-INST: csrrci zero, DPC, 1 +# aliases +# CHECK-INST-ALIAS: csrr t1, DPC +# CHECK-INST-ALIAS: csrw DPC, t2 +# CHECK-INST-ALIAS: csrs DPC, t2 +# CHECK-INST-ALIAS: csrc DPC, t2 +# CHECK-INST-ALIAS: csrwi DPC, 1 +# CHECK-INST-ALIAS: csrsi DPC, 1 +# CHECK-INST-ALIAS: csrci DPC, 1 +# aliases with uimm12 +# CHECK-INST-ALIAS: csrr t1, DPC +# CHECK-INST-ALIAS: csrw DPC, t2 +# CHECK-INST-ALIAS: csrs DPC, t2 +# CHECK-INST-ALIAS: csrc DPC, t2 +# CHECK-INST-ALIAS: csrwi DPC, 1 +# CHECK-INST-ALIAS: csrsi DPC, 1 +# CHECK-INST-ALIAS: csrci DPC, 1 +# name +csrrs t1, dpc, x0 +csrrw x0, dpc, t2 +csrrs x0, dpc, t2 +csrrc x0, dpc, t2 +csrrwi x0, dpc, 1 +csrrsi x0, dpc, 1 +csrrci x0, dpc, 1 +# uimm12 +csrrs t1, 0x7B1, x0 +csrrw x0, 0x7B1, t2 +csrrs x0, 0x7B1, t2 +csrrc x0, 0x7B1, t2 +csrrwi x0, 0x7B1, 1 +csrrsi x0, 0x7B1, 1 +csrrci x0, 0x7B1, 1 +# aliases + +# dscratch +# name +# CHECK-INST: csrrs t1, DSCRATCH, zero +# CHECK-INST: csrrw zero, DSCRATCH, t2 +# CHECK-INST: csrrs zero, DSCRATCH, t2 +# CHECK-INST: csrrc zero, DSCRATCH, t2 +# CHECK-INST: csrrwi zero, DSCRATCH, 1 +# CHECK-INST: csrrsi zero, DSCRATCH, 1 +# CHECK-INST: csrrci zero, DSCRATCH, 1 +# uimm12 +# CHECK-INST: csrrs t1, DSCRATCH, zero +# CHECK-INST: csrrw zero, DSCRATCH, t2 +# CHECK-INST: csrrs zero, DSCRATCH, t2 +# CHECK-INST: csrrc zero, DSCRATCH, t2 +# CHECK-INST: csrrwi zero, DSCRATCH, 1 +# CHECK-INST: csrrsi zero, DSCRATCH, 1 +# CHECK-INST: csrrci zero, DSCRATCH, 1 +# aliases +# CHECK-INST-ALIAS: csrr t1, DSCRATCH +# CHECK-INST-ALIAS: csrw DSCRATCH, t2 +# CHECK-INST-ALIAS: csrs DSCRATCH, t2 +# CHECK-INST-ALIAS: csrc DSCRATCH, t2 +# CHECK-INST-ALIAS: csrwi DSCRATCH, 1 +# CHECK-INST-ALIAS: csrsi DSCRATCH, 1 +# CHECK-INST-ALIAS: csrci DSCRATCH, 1 +# aliases with uimm12 +# CHECK-INST-ALIAS: csrr t1, DSCRATCH +# CHECK-INST-ALIAS: csrw DSCRATCH, t2 +# CHECK-INST-ALIAS: csrs DSCRATCH, t2 +# CHECK-INST-ALIAS: csrc DSCRATCH, t2 +# CHECK-INST-ALIAS: csrwi DSCRATCH, 1 +# CHECK-INST-ALIAS: csrsi DSCRATCH, 1 +# CHECK-INST-ALIAS: csrci DSCRATCH, 1 +# name +csrrs t1, dscratch, x0 +csrrw x0, dscratch, t2 +csrrs x0, dscratch, t2 +csrrc x0, dscratch, t2 +csrrwi x0, dscratch, 1 +csrrsi x0, dscratch, 1 +csrrci x0, dscratch, 1 +# uimm12 +csrrs t1, 0x7B2, x0 +csrrw x0, 0x7B2, t2 +csrrs x0, 0x7B2, t2 +csrrc x0, 0x7B2, t2 +csrrwi x0, 0x7B2, 1 +csrrsi x0, 0x7B2, 1 +csrrci x0, 0x7B2, 1 Index: test/MC/RISCV/rv32i-invalid.s =================================================================== --- test/MC/RISCV/rv32i-invalid.s +++ test/MC/RISCV/rv32i-invalid.s @@ -80,6 +80,16 @@ csrrwi a0, %pcrel_lo(4), 0 # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [0, 4095] csrrsi a0, %pcrel_lo(d), a0 # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [0, 4095] +## named csr in place of uimm12 +csrrw a0, FOO, a0 # CHECK: :[[@LINE]]:11: error: operand must be a valid system register name or an integer in the range [0, 4095] +csrrs a0, MSTATUSX, a0 # CHECK: :[[@LINE]]:11: error: operand must be a valid system register name or an integer in the range [0, 4095] +csrrs a0, XMSTATUS, a0 # CHECK: :[[@LINE]]:11: error: operand must be a valid system register name or an integer in the range [0, 4095] +csrrc a0, M12STATUS, a0 # CHECK: :[[@LINE]]:11: error: operand must be a valid system register name or an integer in the range [0, 4095] +csrrwi a0, MSTATUS12, 0 # CHECK: :[[@LINE]]:12: error: operand must be a valid system register name or an integer in the range [0, 4095] +csrrsi a0, MHPM12COUNTER, a0 # CHECK: :[[@LINE]]:12: error: operand must be a valid system register name or an integer in the range [0, 4095] +csrrwi a0, MHPMCOUNTER32, 0 # CHECK: :[[@LINE]]:12: error: operand must be a valid system register name or an integer in the range [0, 4095] +csrrsi a0, A, a0 # CHECK: :[[@LINE]]:12: error: operand must be a valid system register name or an integer in the range [0, 4095] + ## simm13_lsb0 beq t0, t1, %lo(1) # CHECK: :[[@LINE]]:13: error: immediate must be a multiple of 2 bytes in the range [-4096, 4094] bne t0, t1, %lo(a) # CHECK: :[[@LINE]]:13: error: immediate must be a multiple of 2 bytes in the range [-4096, 4094] Index: test/MC/RISCV/rv32i-valid.s =================================================================== --- test/MC/RISCV/rv32i-valid.s +++ test/MC/RISCV/rv32i-valid.s @@ -223,21 +223,21 @@ # CHECK-INST: csrrw t0, 4095, t1 # CHECK: encoding: [0xf3,0x12,0xf3,0xff] csrrw t0, 0xfff, t1 -# CHECK-INST: csrrs s0, 3072, zero +# CHECK-INST: csrrs s0, CYCLE, zero # CHECK: encoding: [0x73,0x24,0x00,0xc0] csrrs s0, 0xc00, x0 -# CHECK-INST: csrrs s3, 1, s5 +# CHECK-INST: csrrs s3, FFLAGS, s5 # CHECK: encoding: [0xf3,0xa9,0x1a,0x00] csrrs s3, 0x001, s5 -# CHECK-INST: csrrc sp, 0, ra +# CHECK-INST: csrrc sp, USTATUS, ra # CHECK: encoding: [0x73,0xb1,0x00,0x00] csrrc sp, 0x000, ra -# CHECK-INST: csrrwi a5, 0, 0 +# CHECK-INST: csrrwi a5, USTATUS, 0 # CHECK: encoding: [0xf3,0x57,0x00,0x00] csrrwi a5, 0x000, 0 # CHECK-INST: csrrsi t2, 4095, 31 # CHECK: encoding: [0xf3,0xe3,0xff,0xff] csrrsi t2, 0xfff, 31 -# CHECK-INST: csrrci t1, 320, 5 +# CHECK-INST: csrrci t1, SSCRATCH, 5 # CHECK: encoding: [0x73,0xf3,0x02,0x14] csrrci t1, 0x140, 5 Index: test/MC/RISCV/rvf-aliases-valid.s =================================================================== --- test/MC/RISCV/rvf-aliases-valid.s +++ test/MC/RISCV/rvf-aliases-valid.s @@ -45,45 +45,45 @@ # The following instructions actually alias instructions from the base ISA. # However, it only makes sense to support them when the F extension is enabled. -# CHECK-INST: csrrs t0, 3, zero +# CHECK-INST: csrrs t0, FCSR, zero # CHECK-ALIAS: frcsr t0 frcsr x5 -# CHECK-INST: csrrw t1, 3, t2 +# CHECK-INST: csrrw t1, FCSR, t2 # CHECK-ALIAS: fscsr t1, t2 fscsr x6, x7 -# CHECK-INST: csrrw zero, 3, t3 +# CHECK-INST: csrrw zero, FCSR, t3 # CHECK-ALIAS: fscsr t3 fscsr x28 -# CHECK-INST: csrrs t4, 2, zero +# CHECK-INST: csrrs t4, FRM, zero # CHECK-ALIAS: frrm t4 frrm x29 -# CHECK-INST: csrrw t5, 2, t4 +# CHECK-INST: csrrw t5, FRM, t4 # CHECK-ALIAS: fsrm t5, t4 fsrm x30, x29 -# CHECK-INST: csrrw zero, 2, t6 +# CHECK-INST: csrrw zero, FRM, t6 # CHECK-ALIAS: fsrm t6 fsrm x31 -# CHECK-INST: csrrwi a0, 2, 31 +# CHECK-INST: csrrwi a0, FRM, 31 # CHECK-ALIAS: fsrmi a0, 31 fsrmi x10, 0x1f -# CHECK-INST: csrrwi zero, 2, 30 +# CHECK-INST: csrrwi zero, FRM, 30 # CHECK-ALIAS: fsrmi 30 fsrmi 0x1e -# CHECK-INST: csrrs a1, 1, zero +# CHECK-INST: csrrs a1, FFLAGS, zero # CHECK-ALIAS: frflags a1 frflags x11 -# CHECK-INST: csrrw a2, 1, a1 +# CHECK-INST: csrrw a2, FFLAGS, a1 # CHECK-ALIAS: fsflags a2, a1 fsflags x12, x11 -# CHECK-INST: csrrw zero, 1, a3 +# CHECK-INST: csrrw zero, FFLAGS, a3 # CHECK-ALIAS: fsflags a3 fsflags x13 -# CHECK-INST: csrrwi a4, 1, 29 +# CHECK-INST: csrrwi a4, FFLAGS, 29 # CHECK-ALIAS: fsflagsi a4, 29 fsflagsi x14, 0x1d -# CHECK-INST: csrrwi zero, 1, 28 +# CHECK-INST: csrrwi zero, FFLAGS, 28 # CHECK-ALIAS: fsflagsi 28 fsflagsi 0x1c Index: test/MC/RISCV/supervisor-csr-names.s =================================================================== --- /dev/null +++ test/MC/RISCV/supervisor-csr-names.s @@ -0,0 +1,638 @@ +# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s +# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \ +# RUN: | llvm-objdump -d - \ +# RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s +# +# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s +# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \ +# RUN: | llvm-objdump -d - \ +# RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s + +################################## +# Supervisor Trap Setup +################################## + +# sstatus +# name +# CHECK-INST: csrrs t1, SSTATUS, zero +# CHECK-ENC: encoding: [0x73,0x23,0x00,0x10] +# CHECK-INST: csrrw zero, SSTATUS, t2 +# CHECK-ENC: encoding: [0x73,0x90,0x03,0x10] +# CHECK-INST: csrrs zero, SSTATUS, t2 +# CHECK-ENC: encoding: [0x73,0xa0,0x03,0x10] +# CHECK-INST: csrrc zero, SSTATUS, t2 +# CHECK-ENC: encoding: [0x73,0xb0,0x03,0x10] +# CHECK-INST: csrrwi zero, SSTATUS, 1 +# CHECK-ENC: encoding: [0x73,0xd0,0x00,0x10] +# CHECK-INST: csrrsi zero, SSTATUS, 1 +# CHECK-ENC: encoding: [0x73,0xe0,0x00,0x10] +# CHECK-INST: csrrci zero, SSTATUS, 1 +# CHECK-ENC: encoding: [0x73,0xf0,0x00,0x10] +# uimm12 +# CHECK-INST: csrrs t1, SSTATUS, zero +# CHECK-ENC: encoding: [0x73,0x23,0x00,0x10] +# CHECK-INST: csrrw zero, SSTATUS, t2 +# CHECK-ENC: encoding: [0x73,0x90,0x03,0x10] +# CHECK-INST: csrrs zero, SSTATUS, t2 +# CHECK-ENC: encoding: [0x73,0xa0,0x03,0x10] +# CHECK-INST: csrrc zero, SSTATUS, t2 +# CHECK-ENC: encoding: [0x73,0xb0,0x03,0x10] +# CHECK-INST: csrrwi zero, SSTATUS, 1 +# CHECK-ENC: encoding: [0x73,0xd0,0x00,0x10] +# CHECK-INST: csrrsi zero, SSTATUS, 1 +# CHECK-ENC: encoding: [0x73,0xe0,0x00,0x10] +# CHECK-INST: csrrci zero, SSTATUS, 1 +# CHECK-ENC: encoding: [0x73,0xf0,0x00,0x10] +# aliases +# CHECK-INST-ALIAS: csrr t1, SSTATUS +# CHECK-INST-ALIAS: csrw SSTATUS, t2 +# CHECK-INST-ALIAS: csrs SSTATUS, t2 +# CHECK-INST-ALIAS: csrc SSTATUS, t2 +# CHECK-INST-ALIAS: csrwi SSTATUS, 1 +# CHECK-INST-ALIAS: csrsi SSTATUS, 1 +# CHECK-INST-ALIAS: csrci SSTATUS, 1 +# aliases with uimm12 +# CHECK-INST-ALIAS: csrr t1, SSTATUS +# CHECK-INST-ALIAS: csrw SSTATUS, t2 +# CHECK-INST-ALIAS: csrs SSTATUS, t2 +# CHECK-INST-ALIAS: csrc SSTATUS, t2 +# CHECK-INST-ALIAS: csrwi SSTATUS, 1 +# CHECK-INST-ALIAS: csrsi SSTATUS, 1 +# CHECK-INST-ALIAS: csrci SSTATUS, 1 +# name +csrrs t1, sstatus, x0 +csrrw x0, sstatus, t2 +csrrs x0, sstatus, t2 +csrrc x0, sstatus, t2 +csrrwi x0, sstatus, 1 +csrrsi x0, sstatus, 1 +csrrci x0, sstatus, 1 +# uimm12 +csrrs t1, 0x100, x0 +csrrw x0, 0x100, t2 +csrrs x0, 0x100, t2 +csrrc x0, 0x100, t2 +csrrwi x0, 0x100, 1 +csrrsi x0, 0x100, 1 +csrrci x0, 0x100, 1 + +# sedeleg +# name +# CHECK-INST: csrrs t1, SEDELEG, zero +# CHECK-INST: csrrw zero, SEDELEG, t2 +# CHECK-INST: csrrs zero, SEDELEG, t2 +# CHECK-INST: csrrc zero, SEDELEG, t2 +# CHECK-INST: csrrwi zero, SEDELEG, 1 +# CHECK-INST: csrrsi zero, SEDELEG, 1 +# CHECK-INST: csrrci zero, SEDELEG, 1 +# uimm12 +# CHECK-INST: csrrs t1, SEDELEG, zero +# CHECK-INST: csrrw zero, SEDELEG, t2 +# CHECK-INST: csrrs zero, SEDELEG, t2 +# CHECK-INST: csrrc zero, SEDELEG, t2 +# CHECK-INST: csrrwi zero, SEDELEG, 1 +# CHECK-INST: csrrsi zero, SEDELEG, 1 +# CHECK-INST: csrrci zero, SEDELEG, 1 +# aliases +# CHECK-INST-ALIAS: csrr t1, SEDELEG +# CHECK-INST-ALIAS: csrw SEDELEG, t2 +# CHECK-INST-ALIAS: csrs SEDELEG, t2 +# CHECK-INST-ALIAS: csrc SEDELEG, t2 +# CHECK-INST-ALIAS: csrwi SEDELEG, 1 +# CHECK-INST-ALIAS: csrsi SEDELEG, 1 +# CHECK-INST-ALIAS: csrci SEDELEG, 1 +# aliases with uimm12 +# CHECK-INST-ALIAS: csrr t1, SEDELEG +# CHECK-INST-ALIAS: csrw SEDELEG, t2 +# CHECK-INST-ALIAS: csrs SEDELEG, t2 +# CHECK-INST-ALIAS: csrc SEDELEG, t2 +# CHECK-INST-ALIAS: csrwi SEDELEG, 1 +# CHECK-INST-ALIAS: csrsi SEDELEG, 1 +# CHECK-INST-ALIAS: csrci SEDELEG, 1 +# name +csrrs t1, sedeleg, x0 +csrrw x0, sedeleg, t2 +csrrs x0, sedeleg, t2 +csrrc x0, sedeleg, t2 +csrrwi x0, sedeleg, 1 +csrrsi x0, sedeleg, 1 +csrrci x0, sedeleg, 1 +# uimm12 +csrrs t1, 0x102, x0 +csrrw x0, 0x102, t2 +csrrs x0, 0x102, t2 +csrrc x0, 0x102, t2 +csrrwi x0, 0x102, 1 +csrrsi x0, 0x102, 1 +csrrci x0, 0x102, 1 + +# sideleg +# name +# CHECK-INST: csrrs t1, SIDELEG, zero +# CHECK-INST: csrrw zero, SIDELEG, t2 +# CHECK-INST: csrrs zero, SIDELEG, t2 +# CHECK-INST: csrrc zero, SIDELEG, t2 +# CHECK-INST: csrrwi zero, SIDELEG, 1 +# CHECK-INST: csrrsi zero, SIDELEG, 1 +# CHECK-INST: csrrci zero, SIDELEG, 1 +# uimm12 +# CHECK-INST: csrrs t1, SIDELEG, zero +# CHECK-INST: csrrw zero, SIDELEG, t2 +# CHECK-INST: csrrs zero, SIDELEG, t2 +# CHECK-INST: csrrc zero, SIDELEG, t2 +# CHECK-INST: csrrwi zero, SIDELEG, 1 +# CHECK-INST: csrrsi zero, SIDELEG, 1 +# CHECK-INST: csrrci zero, SIDELEG, 1 +# aliases +# CHECK-INST-ALIAS: csrr t1, SIDELEG +# CHECK-INST-ALIAS: csrw SIDELEG, t2 +# CHECK-INST-ALIAS: csrs SIDELEG, t2 +# CHECK-INST-ALIAS: csrc SIDELEG, t2 +# CHECK-INST-ALIAS: csrwi SIDELEG, 1 +# CHECK-INST-ALIAS: csrsi SIDELEG, 1 +# CHECK-INST-ALIAS: csrci SIDELEG, 1 +# aliases with uimm12 +# CHECK-INST-ALIAS: csrr t1, SIDELEG +# CHECK-INST-ALIAS: csrw SIDELEG, t2 +# CHECK-INST-ALIAS: csrs SIDELEG, t2 +# CHECK-INST-ALIAS: csrc SIDELEG, t2 +# CHECK-INST-ALIAS: csrwi SIDELEG, 1 +# CHECK-INST-ALIAS: csrsi SIDELEG, 1 +# CHECK-INST-ALIAS: csrci SIDELEG, 1 +# name +csrrs t1, sideleg, x0 +csrrw x0, sideleg, t2 +csrrs x0, sideleg, t2 +csrrc x0, sideleg, t2 +csrrwi x0, sideleg, 1 +csrrsi x0, sideleg, 1 +csrrci x0, sideleg, 1 +# uimm12 +csrrs t1, 0x103, x0 +csrrw x0, 0x103, t2 +csrrs x0, 0x103, t2 +csrrc x0, 0x103, t2 +csrrwi x0, 0x103, 1 +csrrsi x0, 0x103, 1 +csrrci x0, 0x103, 1 + +# sie +# name +# CHECK-INST: csrrs t1, SIE, zero +# CHECK-INST: csrrw zero, SIE, t2 +# CHECK-INST: csrrs zero, SIE, t2 +# CHECK-INST: csrrc zero, SIE, t2 +# CHECK-INST: csrrwi zero, SIE, 1 +# CHECK-INST: csrrsi zero, SIE, 1 +# CHECK-INST: csrrci zero, SIE, 1 +# uimm12 +# CHECK-INST: csrrs t1, SIE, zero +# CHECK-INST: csrrw zero, SIE, t2 +# CHECK-INST: csrrs zero, SIE, t2 +# CHECK-INST: csrrc zero, SIE, t2 +# CHECK-INST: csrrwi zero, SIE, 1 +# CHECK-INST: csrrsi zero, SIE, 1 +# CHECK-INST: csrrci zero, SIE, 1 +# aliases +# CHECK-INST-ALIAS: csrr t1, SIE +# CHECK-INST-ALIAS: csrw SIE, t2 +# CHECK-INST-ALIAS: csrs SIE, t2 +# CHECK-INST-ALIAS: csrc SIE, t2 +# CHECK-INST-ALIAS: csrwi SIE, 1 +# CHECK-INST-ALIAS: csrsi SIE, 1 +# CHECK-INST-ALIAS: csrci SIE, 1 +# aliases with uimm12 +# CHECK-INST-ALIAS: csrr t1, SIE +# CHECK-INST-ALIAS: csrw SIE, t2 +# CHECK-INST-ALIAS: csrs SIE, t2 +# CHECK-INST-ALIAS: csrc SIE, t2 +# CHECK-INST-ALIAS: csrwi SIE, 1 +# CHECK-INST-ALIAS: csrsi SIE, 1 +# CHECK-INST-ALIAS: csrci SIE, 1 +# name +csrrs t1, sie, x0 +csrrw x0, sie, t2 +csrrs x0, sie, t2 +csrrc x0, sie, t2 +csrrwi x0, sie, 1 +csrrsi x0, sie, 1 +csrrci x0, sie, 1 +# uimm12 +csrrs t1, 0x104, x0 +csrrw x0, 0x104, t2 +csrrs x0, 0x104, t2 +csrrc x0, 0x104, t2 +csrrwi x0, 0x104, 1 +csrrsi x0, 0x104, 1 +csrrci x0, 0x104, 1 + +# stvec +# name +# CHECK-INST: csrrs t1, STVEC, zero +# CHECK-INST: csrrw zero, STVEC, t2 +# CHECK-INST: csrrs zero, STVEC, t2 +# CHECK-INST: csrrc zero, STVEC, t2 +# CHECK-INST: csrrwi zero, STVEC, 1 +# CHECK-INST: csrrsi zero, STVEC, 1 +# CHECK-INST: csrrci zero, STVEC, 1 +# uimm12 +# CHECK-INST: csrrs t1, STVEC, zero +# CHECK-INST: csrrw zero, STVEC, t2 +# CHECK-INST: csrrs zero, STVEC, t2 +# CHECK-INST: csrrc zero, STVEC, t2 +# CHECK-INST: csrrwi zero, STVEC, 1 +# CHECK-INST: csrrsi zero, STVEC, 1 +# CHECK-INST: csrrci zero, STVEC, 1 +# aliases +# CHECK-INST-ALIAS: csrr t1, STVEC +# CHECK-INST-ALIAS: csrw STVEC, t2 +# CHECK-INST-ALIAS: csrs STVEC, t2 +# CHECK-INST-ALIAS: csrc STVEC, t2 +# CHECK-INST-ALIAS: csrwi STVEC, 1 +# CHECK-INST-ALIAS: csrsi STVEC, 1 +# CHECK-INST-ALIAS: csrci STVEC, 1 +# aliases with uimm12 +# CHECK-INST-ALIAS: csrr t1, STVEC +# CHECK-INST-ALIAS: csrw STVEC, t2 +# CHECK-INST-ALIAS: csrs STVEC, t2 +# CHECK-INST-ALIAS: csrc STVEC, t2 +# CHECK-INST-ALIAS: csrwi STVEC, 1 +# CHECK-INST-ALIAS: csrsi STVEC, 1 +# CHECK-INST-ALIAS: csrci STVEC, 1 +# name +csrrs t1, stvec, x0 +csrrw x0, stvec, t2 +csrrs x0, stvec, t2 +csrrc x0, stvec, t2 +csrrwi x0, stvec, 1 +csrrsi x0, stvec, 1 +csrrci x0, stvec, 1 +# uimm12 +csrrs t1, 0x105, x0 +csrrw x0, 0x105, t2 +csrrs x0, 0x105, t2 +csrrc x0, 0x105, t2 +csrrwi x0, 0x105, 1 +csrrsi x0, 0x105, 1 +csrrci x0, 0x105, 1 + +# scounteren +# name +# CHECK-INST: csrrs t1, SCOUNTEREN, zero +# CHECK-INST: csrrw zero, SCOUNTEREN, t2 +# CHECK-INST: csrrs zero, SCOUNTEREN, t2 +# CHECK-INST: csrrc zero, SCOUNTEREN, t2 +# CHECK-INST: csrrwi zero, SCOUNTEREN, 1 +# CHECK-INST: csrrsi zero, SCOUNTEREN, 1 +# CHECK-INST: csrrci zero, SCOUNTEREN, 1 +# uimm12 +# CHECK-INST: csrrs t1, SCOUNTEREN, zero +# CHECK-INST: csrrw zero, SCOUNTEREN, t2 +# CHECK-INST: csrrs zero, SCOUNTEREN, t2 +# CHECK-INST: csrrc zero, SCOUNTEREN, t2 +# CHECK-INST: csrrwi zero, SCOUNTEREN, 1 +# CHECK-INST: csrrsi zero, SCOUNTEREN, 1 +# CHECK-INST: csrrci zero, SCOUNTEREN, 1 +# aliases +# CHECK-INST-ALIAS: csrr t1, SCOUNTEREN +# CHECK-INST-ALIAS: csrw SCOUNTEREN, t2 +# CHECK-INST-ALIAS: csrs SCOUNTEREN, t2 +# CHECK-INST-ALIAS: csrc SCOUNTEREN, t2 +# CHECK-INST-ALIAS: csrwi SCOUNTEREN, 1 +# CHECK-INST-ALIAS: csrsi SCOUNTEREN, 1 +# CHECK-INST-ALIAS: csrci SCOUNTEREN, 1 +# aliases with uimm12 +# CHECK-INST-ALIAS: csrr t1, SCOUNTEREN +# CHECK-INST-ALIAS: csrw SCOUNTEREN, t2 +# CHECK-INST-ALIAS: csrs SCOUNTEREN, t2 +# CHECK-INST-ALIAS: csrc SCOUNTEREN, t2 +# CHECK-INST-ALIAS: csrwi SCOUNTEREN, 1 +# CHECK-INST-ALIAS: csrsi SCOUNTEREN, 1 +# CHECK-INST-ALIAS: csrci SCOUNTEREN, 1 +# name +csrrs t1, scounteren, x0 +csrrw x0, scounteren, t2 +csrrs x0, scounteren, t2 +csrrc x0, scounteren, t2 +csrrwi x0, scounteren, 1 +csrrsi x0, scounteren, 1 +csrrci x0, scounteren, 1 +# uimm12 +csrrs t1, 0x106, x0 +csrrw x0, 0x106, t2 +csrrs x0, 0x106, t2 +csrrc x0, 0x106, t2 +csrrwi x0, 0x106, 1 +csrrsi x0, 0x106, 1 +csrrci x0, 0x106, 1 + +################################## +# Supervisor Trap Handling +################################## + +# sscratch +# name +# CHECK-INST: csrrs t1, SSCRATCH, zero +# CHECK-INST: csrrw zero, SSCRATCH, t2 +# CHECK-INST: csrrs zero, SSCRATCH, t2 +# CHECK-INST: csrrc zero, SSCRATCH, t2 +# CHECK-INST: csrrwi zero, SSCRATCH, 1 +# CHECK-INST: csrrsi zero, SSCRATCH, 1 +# CHECK-INST: csrrci zero, SSCRATCH, 1 +# uimm12 +# CHECK-INST: csrrs t1, SSCRATCH, zero +# CHECK-INST: csrrw zero, SSCRATCH, t2 +# CHECK-INST: csrrs zero, SSCRATCH, t2 +# CHECK-INST: csrrc zero, SSCRATCH, t2 +# CHECK-INST: csrrwi zero, SSCRATCH, 1 +# CHECK-INST: csrrsi zero, SSCRATCH, 1 +# CHECK-INST: csrrci zero, SSCRATCH, 1 +# aliases +# CHECK-INST-ALIAS: csrr t1, SSCRATCH +# CHECK-INST-ALIAS: csrw SSCRATCH, t2 +# CHECK-INST-ALIAS: csrs SSCRATCH, t2 +# CHECK-INST-ALIAS: csrc SSCRATCH, t2 +# CHECK-INST-ALIAS: csrwi SSCRATCH, 1 +# CHECK-INST-ALIAS: csrsi SSCRATCH, 1 +# CHECK-INST-ALIAS: csrci SSCRATCH, 1 +# aliases with uimm12 +# CHECK-INST-ALIAS: csrr t1, SSCRATCH +# CHECK-INST-ALIAS: csrw SSCRATCH, t2 +# CHECK-INST-ALIAS: csrs SSCRATCH, t2 +# CHECK-INST-ALIAS: csrc SSCRATCH, t2 +# CHECK-INST-ALIAS: csrwi SSCRATCH, 1 +# CHECK-INST-ALIAS: csrsi SSCRATCH, 1 +# CHECK-INST-ALIAS: csrci SSCRATCH, 1 +# name +csrrs t1, sscratch, x0 +csrrw x0, sscratch, t2 +csrrs x0, sscratch, t2 +csrrc x0, sscratch, t2 +csrrwi x0, sscratch, 1 +csrrsi x0, sscratch, 1 +csrrci x0, sscratch, 1 +# uimm12 +csrrs t1, 0x140, x0 +csrrw x0, 0x140, t2 +csrrs x0, 0x140, t2 +csrrc x0, 0x140, t2 +csrrwi x0, 0x140, 1 +csrrsi x0, 0x140, 1 +csrrci x0, 0x140, 1 + +# sepc +# name +# CHECK-INST: csrrs t1, SEPC, zero +# CHECK-INST: csrrw zero, SEPC, t2 +# CHECK-INST: csrrs zero, SEPC, t2 +# CHECK-INST: csrrc zero, SEPC, t2 +# CHECK-INST: csrrwi zero, SEPC, 1 +# CHECK-INST: csrrsi zero, SEPC, 1 +# CHECK-INST: csrrci zero, SEPC, 1 +# uimm12 +# CHECK-INST: csrrs t1, SEPC, zero +# CHECK-INST: csrrw zero, SEPC, t2 +# CHECK-INST: csrrs zero, SEPC, t2 +# CHECK-INST: csrrc zero, SEPC, t2 +# CHECK-INST: csrrwi zero, SEPC, 1 +# CHECK-INST: csrrsi zero, SEPC, 1 +# CHECK-INST: csrrci zero, SEPC, 1 +# aliases +# CHECK-INST-ALIAS: csrr t1, SEPC +# CHECK-INST-ALIAS: csrw SEPC, t2 +# CHECK-INST-ALIAS: csrs SEPC, t2 +# CHECK-INST-ALIAS: csrc SEPC, t2 +# CHECK-INST-ALIAS: csrwi SEPC, 1 +# CHECK-INST-ALIAS: csrsi SEPC, 1 +# CHECK-INST-ALIAS: csrci SEPC, 1 +# aliases with uimm12 +# CHECK-INST-ALIAS: csrr t1, SEPC +# CHECK-INST-ALIAS: csrw SEPC, t2 +# CHECK-INST-ALIAS: csrs SEPC, t2 +# CHECK-INST-ALIAS: csrc SEPC, t2 +# CHECK-INST-ALIAS: csrwi SEPC, 1 +# CHECK-INST-ALIAS: csrsi SEPC, 1 +# CHECK-INST-ALIAS: csrci SEPC, 1 +# name +csrrs t1, sepc, x0 +csrrw x0, sepc, t2 +csrrs x0, sepc, t2 +csrrc x0, sepc, t2 +csrrwi x0, sepc, 1 +csrrsi x0, sepc, 1 +csrrci x0, sepc, 1 +# uimm12 +csrrs t1, 0x141, x0 +csrrw x0, 0x141, t2 +csrrs x0, 0x141, t2 +csrrc x0, 0x141, t2 +csrrwi x0, 0x141, 1 +csrrsi x0, 0x141, 1 +csrrci x0, 0x141, 1 + +# scause +# name +# CHECK-INST: csrrs t1, SCAUSE, zero +# CHECK-INST: csrrw zero, SCAUSE, t2 +# CHECK-INST: csrrs zero, SCAUSE, t2 +# CHECK-INST: csrrc zero, SCAUSE, t2 +# CHECK-INST: csrrwi zero, SCAUSE, 1 +# CHECK-INST: csrrsi zero, SCAUSE, 1 +# CHECK-INST: csrrci zero, SCAUSE, 1 +# uimm12 +# CHECK-INST: csrrs t1, SCAUSE, zero +# CHECK-INST: csrrw zero, SCAUSE, t2 +# CHECK-INST: csrrs zero, SCAUSE, t2 +# CHECK-INST: csrrc zero, SCAUSE, t2 +# CHECK-INST: csrrwi zero, SCAUSE, 1 +# CHECK-INST: csrrsi zero, SCAUSE, 1 +# CHECK-INST: csrrci zero, SCAUSE, 1 +# aliases +# CHECK-INST-ALIAS: csrr t1, SCAUSE +# CHECK-INST-ALIAS: csrw SCAUSE, t2 +# CHECK-INST-ALIAS: csrs SCAUSE, t2 +# CHECK-INST-ALIAS: csrc SCAUSE, t2 +# CHECK-INST-ALIAS: csrwi SCAUSE, 1 +# CHECK-INST-ALIAS: csrsi SCAUSE, 1 +# CHECK-INST-ALIAS: csrci SCAUSE, 1 +# aliases with uimm12 +# CHECK-INST-ALIAS: csrr t1, SCAUSE +# CHECK-INST-ALIAS: csrw SCAUSE, t2 +# CHECK-INST-ALIAS: csrs SCAUSE, t2 +# CHECK-INST-ALIAS: csrc SCAUSE, t2 +# CHECK-INST-ALIAS: csrwi SCAUSE, 1 +# CHECK-INST-ALIAS: csrsi SCAUSE, 1 +# CHECK-INST-ALIAS: csrci SCAUSE, 1 +# name +csrrs t1, scause, x0 +csrrw x0, scause, t2 +csrrs x0, scause, t2 +csrrc x0, scause, t2 +csrrwi x0, scause, 1 +csrrsi x0, scause, 1 +csrrci x0, scause, 1 +# uimm12 +csrrs t1, 0x142, x0 +csrrw x0, 0x142, t2 +csrrs x0, 0x142, t2 +csrrc x0, 0x142, t2 +csrrwi x0, 0x142, 1 +csrrsi x0, 0x142, 1 +csrrci x0, 0x142, 1 + +# stval +# name +# CHECK-INST: csrrs t1, STVAL, zero +# CHECK-INST: csrrw zero, STVAL, t2 +# CHECK-INST: csrrs zero, STVAL, t2 +# CHECK-INST: csrrc zero, STVAL, t2 +# CHECK-INST: csrrwi zero, STVAL, 1 +# CHECK-INST: csrrsi zero, STVAL, 1 +# CHECK-INST: csrrci zero, STVAL, 1 +# uimm12 +# CHECK-INST: csrrs t1, STVAL, zero +# CHECK-INST: csrrw zero, STVAL, t2 +# CHECK-INST: csrrs zero, STVAL, t2 +# CHECK-INST: csrrc zero, STVAL, t2 +# CHECK-INST: csrrwi zero, STVAL, 1 +# CHECK-INST: csrrsi zero, STVAL, 1 +# CHECK-INST: csrrci zero, STVAL, 1 +# aliases +# CHECK-INST-ALIAS: csrr t1, STVAL +# CHECK-INST-ALIAS: csrw STVAL, t2 +# CHECK-INST-ALIAS: csrs STVAL, t2 +# CHECK-INST-ALIAS: csrc STVAL, t2 +# CHECK-INST-ALIAS: csrwi STVAL, 1 +# CHECK-INST-ALIAS: csrsi STVAL, 1 +# CHECK-INST-ALIAS: csrci STVAL, 1 +# aliases with uimm12 +# CHECK-INST-ALIAS: csrr t1, STVAL +# CHECK-INST-ALIAS: csrw STVAL, t2 +# CHECK-INST-ALIAS: csrs STVAL, t2 +# CHECK-INST-ALIAS: csrc STVAL, t2 +# CHECK-INST-ALIAS: csrwi STVAL, 1 +# CHECK-INST-ALIAS: csrsi STVAL, 1 +# CHECK-INST-ALIAS: csrci STVAL, 1 +# name +csrrs t1, stval, x0 +csrrw x0, stval, t2 +csrrs x0, stval, t2 +csrrc x0, stval, t2 +csrrwi x0, stval, 1 +csrrsi x0, stval, 1 +csrrci x0, stval, 1 +# uimm12 +csrrs t1, 0x143, x0 +csrrw x0, 0x143, t2 +csrrs x0, 0x143, t2 +csrrc x0, 0x143, t2 +csrrwi x0, 0x143, 1 +csrrsi x0, 0x143, 1 +csrrci x0, 0x143, 1 + +# sip +# name +# CHECK-INST: csrrs t1, SIP, zero +# CHECK-INST: csrrw zero, SIP, t2 +# CHECK-INST: csrrs zero, SIP, t2 +# CHECK-INST: csrrc zero, SIP, t2 +# CHECK-INST: csrrwi zero, SIP, 1 +# CHECK-INST: csrrsi zero, SIP, 1 +# CHECK-INST: csrrci zero, SIP, 1 +# uimm12 +# CHECK-INST: csrrs t1, SIP, zero +# CHECK-INST: csrrw zero, SIP, t2 +# CHECK-INST: csrrs zero, SIP, t2 +# CHECK-INST: csrrc zero, SIP, t2 +# CHECK-INST: csrrwi zero, SIP, 1 +# CHECK-INST: csrrsi zero, SIP, 1 +# CHECK-INST: csrrci zero, SIP, 1 +# aliases +# CHECK-INST-ALIAS: csrr t1, SIP +# CHECK-INST-ALIAS: csrw SIP, t2 +# CHECK-INST-ALIAS: csrs SIP, t2 +# CHECK-INST-ALIAS: csrc SIP, t2 +# CHECK-INST-ALIAS: csrwi SIP, 1 +# CHECK-INST-ALIAS: csrsi SIP, 1 +# CHECK-INST-ALIAS: csrci SIP, 1 +# aliases with uimm12 +# CHECK-INST-ALIAS: csrr t1, SIP +# CHECK-INST-ALIAS: csrw SIP, t2 +# CHECK-INST-ALIAS: csrs SIP, t2 +# CHECK-INST-ALIAS: csrc SIP, t2 +# CHECK-INST-ALIAS: csrwi SIP, 1 +# CHECK-INST-ALIAS: csrsi SIP, 1 +# CHECK-INST-ALIAS: csrci SIP, 1 +# name +csrrs t1, sip, x0 +csrrw x0, sip, t2 +csrrs x0, sip, t2 +csrrc x0, sip, t2 +csrrwi x0, sip, 1 +csrrsi x0, sip, 1 +csrrci x0, sip, 1 +# uimm12 +csrrs t1, 0x144, x0 +csrrw x0, 0x144, t2 +csrrs x0, 0x144, t2 +csrrc x0, 0x144, t2 +csrrwi x0, 0x144, 1 +csrrsi x0, 0x144, 1 +csrrci x0, 0x144, 1 + + +######################################### +# Supervisor Protection and Translation +######################################### + +# satp +# name +# CHECK-INST: csrrs t1, SATP, zero +# CHECK-INST: csrrw zero, SATP, t2 +# CHECK-INST: csrrs zero, SATP, t2 +# CHECK-INST: csrrc zero, SATP, t2 +# CHECK-INST: csrrwi zero, SATP, 1 +# CHECK-INST: csrrsi zero, SATP, 1 +# CHECK-INST: csrrci zero, SATP, 1 +# uimm12 +# CHECK-INST: csrrs t1, SATP, zero +# CHECK-INST: csrrw zero, SATP, t2 +# CHECK-INST: csrrs zero, SATP, t2 +# CHECK-INST: csrrc zero, SATP, t2 +# CHECK-INST: csrrwi zero, SATP, 1 +# CHECK-INST: csrrsi zero, SATP, 1 +# CHECK-INST: csrrci zero, SATP, 1 +# aliases +# CHECK-INST-ALIAS: csrr t1, SATP +# CHECK-INST-ALIAS: csrw SATP, t2 +# CHECK-INST-ALIAS: csrs SATP, t2 +# CHECK-INST-ALIAS: csrc SATP, t2 +# CHECK-INST-ALIAS: csrwi SATP, 1 +# CHECK-INST-ALIAS: csrsi SATP, 1 +# CHECK-INST-ALIAS: csrci SATP, 1 +# aliases with uimm12 +# CHECK-INST-ALIAS: csrr t1, SATP +# CHECK-INST-ALIAS: csrw SATP, t2 +# CHECK-INST-ALIAS: csrs SATP, t2 +# CHECK-INST-ALIAS: csrc SATP, t2 +# CHECK-INST-ALIAS: csrwi SATP, 1 +# CHECK-INST-ALIAS: csrsi SATP, 1 +# CHECK-INST-ALIAS: csrci SATP, 1 +# name +csrrs t1, satp, x0 +csrrw x0, satp, t2 +csrrs x0, satp, t2 +csrrc x0, satp, t2 +csrrwi x0, satp, 1 +csrrsi x0, satp, 1 +csrrci x0, satp, 1 +# uimm12 +csrrs t1, 0x180, x0 +csrrw x0, 0x180, t2 +csrrs x0, 0x180, t2 +csrrc x0, 0x180, t2 +csrrwi x0, 0x180, 1 +csrrsi x0, 0x180, 1 +csrrci x0, 0x180, 1 Index: test/MC/RISCV/user-csr-names.s =================================================================== --- /dev/null +++ test/MC/RISCV/user-csr-names.s @@ -0,0 +1,750 @@ +# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-INST %s +# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \ +# RUN: | llvm-objdump -d - \ +# RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s +# +# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-INST %s +# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \ +# RUN: | llvm-objdump -d - \ +# RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s + + +################################## +# Supervisor Trap Setup +################################## + +# ustatus +# name +# CHECK-INST: csrrs t1, USTATUS, zero +# CHECK-ENC: # encoding: [0x73,0x23,0x00,0x00] +# CHECK-INST: csrrw zero, USTATUS, t2 +# CHECK-ENC: # encoding: [0x73,0x90,0x03,0x00] +# CHECK-INST: csrrs zero, USTATUS, t2 +# CHECK-ENC: # encoding: [0x73,0xa0,0x03,0x00] +# CHECK-INST: csrrc zero, USTATUS, t2 +# CHECK-ENC: # encoding: [0x73,0xb0,0x03,0x00] +# CHECK-INST: csrrwi zero, USTATUS, 1 +# CHECK-ENC: # encoding: [0x73,0xd0,0x00,0x00] +# CHECK-INST: csrrsi zero, USTATUS, 1 +# CHECK-ENC: # encoding: [0x73,0xe0,0x00,0x00] +# CHECK-INST: csrrci zero, USTATUS, 1 +# CHECK-ENC: # encoding: [0x73,0xf0,0x00,0x00] +# uimm12 +# CHECK-INST: csrrs t1, USTATUS, zero +# CHECK-ENC: # encoding: [0x73,0x23,0x00,0x00] +# CHECK-INST: csrrw zero, USTATUS, t2 +# CHECK-ENC: # encoding: [0x73,0x90,0x03,0x00] +# CHECK-INST: csrrs zero, USTATUS, t2 +# CHECK-ENC: # encoding: [0x73,0xa0,0x03,0x00] +# CHECK-INST: csrrc zero, USTATUS, t2 +# CHECK-ENC: # encoding: [0x73,0xb0,0x03,0x00] +# CHECK-INST: csrrwi zero, USTATUS, 1 +# CHECK-ENC: # encoding: [0x73,0xd0,0x00,0x00] +# CHECK-INST: csrrsi zero, USTATUS, 1 +# CHECK-ENC: # encoding: [0x73,0xe0,0x00,0x00] +# CHECK-INST: csrrci zero, USTATUS, 1 +# CHECK-ENC: # encoding: [0x73,0xf0,0x00,0x00] +# aliases +# CHECK-INST-ALIAS: csrr t1, USTATUS +# CHECK-INST-ALIAS: csrw USTATUS, t2 +# CHECK-INST-ALIAS: csrs USTATUS, t2 +# CHECK-INST-ALIAS: csrc USTATUS, t2 +# CHECK-INST-ALIAS: csrwi USTATUS, 1 +# CHECK-INST-ALIAS: csrsi USTATUS, 1 +# CHECK-INST-ALIAS: csrci USTATUS, 1 +# aliases with uimm12 +# CHECK-INST-ALIAS: csrr t1, USTATUS +# CHECK-INST-ALIAS: csrw USTATUS, t2 +# CHECK-INST-ALIAS: csrs USTATUS, t2 +# CHECK-INST-ALIAS: csrc USTATUS, t2 +# CHECK-INST-ALIAS: csrwi USTATUS, 1 +# CHECK-INST-ALIAS: csrsi USTATUS, 1 +# CHECK-INST-ALIAS: csrci USTATUS, 1 +# name +csrrs t1, ustatus, x0 +csrrw x0, ustatus, t2 +csrrs x0, ustatus, t2 +csrrc x0, ustatus, t2 +csrrwi x0, ustatus, 1 +csrrsi x0, ustatus, 1 +csrrci x0, ustatus, 1 +# uimm12 +csrrs t1, 0x000, x0 +csrrw x0, 0x000, t2 +csrrs x0, 0x000, t2 +csrrc x0, 0x000, t2 +csrrwi x0, 0x000, 1 +csrrsi x0, 0x000, 1 +csrrci x0, 0x000, 1 + +# uie +# name +# CHECK-INST: csrrs t1, UIE, zero +# CHECK-INST: csrrw zero, UIE, t2 +# CHECK-INST: csrrs zero, UIE, t2 +# CHECK-INST: csrrc zero, UIE, t2 +# CHECK-INST: csrrwi zero, UIE, 1 +# CHECK-INST: csrrsi zero, UIE, 1 +# CHECK-INST: csrrci zero, UIE, 1 +# uimm12 +# CHECK-INST: csrrs t1, UIE, zero +# CHECK-INST: csrrw zero, UIE, t2 +# CHECK-INST: csrrs zero, UIE, t2 +# CHECK-INST: csrrc zero, UIE, t2 +# CHECK-INST: csrrwi zero, UIE, 1 +# CHECK-INST: csrrsi zero, UIE, 1 +# CHECK-INST: csrrci zero, UIE, 1 +# aliases +# CHECK-INST-ALIAS: csrr t1, UIE +# CHECK-INST-ALIAS: csrw UIE, t2 +# CHECK-INST-ALIAS: csrs UIE, t2 +# CHECK-INST-ALIAS: csrc UIE, t2 +# CHECK-INST-ALIAS: csrwi UIE, 1 +# CHECK-INST-ALIAS: csrsi UIE, 1 +# CHECK-INST-ALIAS: csrci UIE, 1 +# aliases with uimm12 +# CHECK-INST-ALIAS: csrr t1, UIE +# CHECK-INST-ALIAS: csrw UIE, t2 +# CHECK-INST-ALIAS: csrs UIE, t2 +# CHECK-INST-ALIAS: csrc UIE, t2 +# CHECK-INST-ALIAS: csrwi UIE, 1 +# CHECK-INST-ALIAS: csrsi UIE, 1 +# CHECK-INST-ALIAS: csrci UIE, 1 +# name +csrrs t1, uie, x0 +csrrw x0, uie, t2 +csrrs x0, uie, t2 +csrrc x0, uie, t2 +csrrwi x0, uie, 1 +csrrsi x0, uie, 1 +csrrci x0, uie, 1 +# uimm12 +csrrs t1, 0x004, x0 +csrrw x0, 0x004, t2 +csrrs x0, 0x004, t2 +csrrc x0, 0x004, t2 +csrrwi x0, 0x004, 1 +csrrsi x0, 0x004, 1 +csrrci x0, 0x004, 1 + +# utvec +# name +# CHECK-INST: csrrs t1, UTVEC, zero +# CHECK-INST: csrrw zero, UTVEC, t2 +# CHECK-INST: csrrs zero, UTVEC, t2 +# CHECK-INST: csrrc zero, UTVEC, t2 +# CHECK-INST: csrrwi zero, UTVEC, 1 +# CHECK-INST: csrrsi zero, UTVEC, 1 +# CHECK-INST: csrrci zero, UTVEC, 1 +# uimm12 +# CHECK-INST: csrrs t1, UTVEC, zero +# CHECK-INST: csrrw zero, UTVEC, t2 +# CHECK-INST: csrrs zero, UTVEC, t2 +# CHECK-INST: csrrc zero, UTVEC, t2 +# CHECK-INST: csrrwi zero, UTVEC, 1 +# CHECK-INST: csrrsi zero, UTVEC, 1 +# CHECK-INST: csrrci zero, UTVEC, 1 +# aliases +# CHECK-INST-ALIAS: csrr t1, UTVEC +# CHECK-INST-ALIAS: csrw UTVEC, t2 +# CHECK-INST-ALIAS: csrs UTVEC, t2 +# CHECK-INST-ALIAS: csrc UTVEC, t2 +# CHECK-INST-ALIAS: csrwi UTVEC, 1 +# CHECK-INST-ALIAS: csrsi UTVEC, 1 +# CHECK-INST-ALIAS: csrci UTVEC, 1 +# aliases with uimm12 +# CHECK-INST-ALIAS: csrr t1, UTVEC +# CHECK-INST-ALIAS: csrw UTVEC, t2 +# CHECK-INST-ALIAS: csrs UTVEC, t2 +# CHECK-INST-ALIAS: csrc UTVEC, t2 +# CHECK-INST-ALIAS: csrwi UTVEC, 1 +# CHECK-INST-ALIAS: csrsi UTVEC, 1 +# CHECK-INST-ALIAS: csrci UTVEC, 1 +# name +csrrs t1, utvec, x0 +csrrw x0, utvec, t2 +csrrs x0, utvec, t2 +csrrc x0, utvec, t2 +csrrwi x0, utvec, 1 +csrrsi x0, utvec, 1 +csrrci x0, utvec, 1 +# uimm12 +csrrs t1, 0x005, x0 +csrrw x0, 0x005, t2 +csrrs x0, 0x005, t2 +csrrc x0, 0x005, t2 +csrrwi x0, 0x005, 1 +csrrsi x0, 0x005, 1 +csrrci x0, 0x005, 1 + +################################## +# Supervisor Trap Handling +################################## + +# uscratch +# name +# CHECK-INST: csrrs t1, USCRATCH, zero +# CHECK-INST: csrrw zero, USCRATCH, t2 +# CHECK-INST: csrrs zero, USCRATCH, t2 +# CHECK-INST: csrrc zero, USCRATCH, t2 +# CHECK-INST: csrrwi zero, USCRATCH, 1 +# CHECK-INST: csrrsi zero, USCRATCH, 1 +# CHECK-INST: csrrci zero, USCRATCH, 1 +# uimm12 +# CHECK-INST: csrrs t1, USCRATCH, zero +# CHECK-INST: csrrw zero, USCRATCH, t2 +# CHECK-INST: csrrs zero, USCRATCH, t2 +# CHECK-INST: csrrc zero, USCRATCH, t2 +# CHECK-INST: csrrwi zero, USCRATCH, 1 +# CHECK-INST: csrrsi zero, USCRATCH, 1 +# CHECK-INST: csrrci zero, USCRATCH, 1 +# aliases +# CHECK-INST-ALIAS: csrr t1, USCRATCH +# CHECK-INST-ALIAS: csrw USCRATCH, t2 +# CHECK-INST-ALIAS: csrs USCRATCH, t2 +# CHECK-INST-ALIAS: csrc USCRATCH, t2 +# CHECK-INST-ALIAS: csrwi USCRATCH, 1 +# CHECK-INST-ALIAS: csrsi USCRATCH, 1 +# CHECK-INST-ALIAS: csrci USCRATCH, 1 +# aliases with uimm12 +# CHECK-INST-ALIAS: csrr t1, USCRATCH +# CHECK-INST-ALIAS: csrw USCRATCH, t2 +# CHECK-INST-ALIAS: csrs USCRATCH, t2 +# CHECK-INST-ALIAS: csrc USCRATCH, t2 +# CHECK-INST-ALIAS: csrwi USCRATCH, 1 +# CHECK-INST-ALIAS: csrsi USCRATCH, 1 +# CHECK-INST-ALIAS: csrci USCRATCH, 1 +# name +csrrs t1, uscratch, x0 +csrrw x0, uscratch, t2 +csrrs x0, uscratch, t2 +csrrc x0, uscratch, t2 +csrrwi x0, uscratch, 1 +csrrsi x0, uscratch, 1 +csrrci x0, uscratch, 1 +# uimm12 +csrrs t1, 0x040, x0 +csrrw x0, 0x040, t2 +csrrs x0, 0x040, t2 +csrrc x0, 0x040, t2 +csrrwi x0, 0x040, 1 +csrrsi x0, 0x040, 1 +csrrci x0, 0x040, 1 + +# uepc +# name +# CHECK-INST: csrrs t1, UEPC, zero +# CHECK-INST: csrrw zero, UEPC, t2 +# CHECK-INST: csrrs zero, UEPC, t2 +# CHECK-INST: csrrc zero, UEPC, t2 +# CHECK-INST: csrrwi zero, UEPC, 1 +# CHECK-INST: csrrsi zero, UEPC, 1 +# CHECK-INST: csrrci zero, UEPC, 1 +# uimm12 +# CHECK-INST: csrrs t1, UEPC, zero +# CHECK-INST: csrrw zero, UEPC, t2 +# CHECK-INST: csrrs zero, UEPC, t2 +# CHECK-INST: csrrc zero, UEPC, t2 +# CHECK-INST: csrrwi zero, UEPC, 1 +# CHECK-INST: csrrsi zero, UEPC, 1 +# CHECK-INST: csrrci zero, UEPC, 1 +# aliases +# CHECK-INST-ALIAS: csrr t1, UEPC +# CHECK-INST-ALIAS: csrw UEPC, t2 +# CHECK-INST-ALIAS: csrs UEPC, t2 +# CHECK-INST-ALIAS: csrc UEPC, t2 +# CHECK-INST-ALIAS: csrwi UEPC, 1 +# CHECK-INST-ALIAS: csrsi UEPC, 1 +# CHECK-INST-ALIAS: csrci UEPC, 1 +# aliases with uimm12 +# CHECK-INST-ALIAS: csrr t1, UEPC +# CHECK-INST-ALIAS: csrw UEPC, t2 +# CHECK-INST-ALIAS: csrs UEPC, t2 +# CHECK-INST-ALIAS: csrc UEPC, t2 +# CHECK-INST-ALIAS: csrwi UEPC, 1 +# CHECK-INST-ALIAS: csrsi UEPC, 1 +# CHECK-INST-ALIAS: csrci UEPC, 1 +# name +csrrs t1, uepc, x0 +csrrw x0, uepc, t2 +csrrs x0, uepc, t2 +csrrc x0, uepc, t2 +csrrwi x0, uepc, 1 +csrrsi x0, uepc, 1 +csrrci x0, uepc, 1 +# uimm12 +csrrs t1, 0x041, x0 +csrrw x0, 0x041, t2 +csrrs x0, 0x041, t2 +csrrc x0, 0x041, t2 +csrrwi x0, 0x041, 1 +csrrsi x0, 0x041, 1 +csrrci x0, 0x041, 1 + +# ucause +# name +# CHECK-INST: csrrs t1, UCAUSE, zero +# CHECK-INST: csrrw zero, UCAUSE, t2 +# CHECK-INST: csrrs zero, UCAUSE, t2 +# CHECK-INST: csrrc zero, UCAUSE, t2 +# CHECK-INST: csrrwi zero, UCAUSE, 1 +# CHECK-INST: csrrsi zero, UCAUSE, 1 +# CHECK-INST: csrrci zero, UCAUSE, 1 +# uimm12 +# CHECK-INST: csrrs t1, UCAUSE, zero +# CHECK-INST: csrrw zero, UCAUSE, t2 +# CHECK-INST: csrrs zero, UCAUSE, t2 +# CHECK-INST: csrrc zero, UCAUSE, t2 +# CHECK-INST: csrrwi zero, UCAUSE, 1 +# CHECK-INST: csrrsi zero, UCAUSE, 1 +# CHECK-INST: csrrci zero, UCAUSE, 1 +# aliases +# CHECK-INST-ALIAS: csrr t1, UCAUSE +# CHECK-INST-ALIAS: csrw UCAUSE, t2 +# CHECK-INST-ALIAS: csrs UCAUSE, t2 +# CHECK-INST-ALIAS: csrc UCAUSE, t2 +# CHECK-INST-ALIAS: csrwi UCAUSE, 1 +# CHECK-INST-ALIAS: csrsi UCAUSE, 1 +# CHECK-INST-ALIAS: csrci UCAUSE, 1 +# aliases with uimm12 +# CHECK-INST-ALIAS: csrr t1, UCAUSE +# CHECK-INST-ALIAS: csrw UCAUSE, t2 +# CHECK-INST-ALIAS: csrs UCAUSE, t2 +# CHECK-INST-ALIAS: csrc UCAUSE, t2 +# CHECK-INST-ALIAS: csrwi UCAUSE, 1 +# CHECK-INST-ALIAS: csrsi UCAUSE, 1 +# CHECK-INST-ALIAS: csrci UCAUSE, 1 +# name +csrrs t1, ucause, x0 +csrrw x0, ucause, t2 +csrrs x0, ucause, t2 +csrrc x0, ucause, t2 +csrrwi x0, ucause, 1 +csrrsi x0, ucause, 1 +csrrci x0, ucause, 1 +# uimm12 +csrrs t1, 0x042, x0 +csrrw x0, 0x042, t2 +csrrs x0, 0x042, t2 +csrrc x0, 0x042, t2 +csrrwi x0, 0x042, 1 +csrrsi x0, 0x042, 1 +csrrci x0, 0x042, 1 + +# utval +# name +# CHECK-INST: csrrs t1, UTVAL, zero +# CHECK-INST: csrrw zero, UTVAL, t2 +# CHECK-INST: csrrs zero, UTVAL, t2 +# CHECK-INST: csrrc zero, UTVAL, t2 +# CHECK-INST: csrrwi zero, UTVAL, 1 +# CHECK-INST: csrrsi zero, UTVAL, 1 +# CHECK-INST: csrrci zero, UTVAL, 1 +# uimm12 +# CHECK-INST: csrrs t1, UTVAL, zero +# CHECK-INST: csrrw zero, UTVAL, t2 +# CHECK-INST: csrrs zero, UTVAL, t2 +# CHECK-INST: csrrc zero, UTVAL, t2 +# CHECK-INST: csrrwi zero, UTVAL, 1 +# CHECK-INST: csrrsi zero, UTVAL, 1 +# CHECK-INST: csrrci zero, UTVAL, 1 +# aliases +# CHECK-INST-ALIAS: csrr t1, UTVAL +# CHECK-INST-ALIAS: csrw UTVAL, t2 +# CHECK-INST-ALIAS: csrs UTVAL, t2 +# CHECK-INST-ALIAS: csrc UTVAL, t2 +# CHECK-INST-ALIAS: csrwi UTVAL, 1 +# CHECK-INST-ALIAS: csrsi UTVAL, 1 +# CHECK-INST-ALIAS: csrci UTVAL, 1 +# aliases with uimm12 +# CHECK-INST-ALIAS: csrr t1, UTVAL +# CHECK-INST-ALIAS: csrw UTVAL, t2 +# CHECK-INST-ALIAS: csrs UTVAL, t2 +# CHECK-INST-ALIAS: csrc UTVAL, t2 +# CHECK-INST-ALIAS: csrwi UTVAL, 1 +# CHECK-INST-ALIAS: csrsi UTVAL, 1 +# CHECK-INST-ALIAS: csrci UTVAL, 1 +# name +csrrs t1, utval, x0 +csrrw x0, utval, t2 +csrrs x0, utval, t2 +csrrc x0, utval, t2 +csrrwi x0, utval, 1 +csrrsi x0, utval, 1 +csrrci x0, utval, 1 +# uimm12 +csrrs t1, 0x043, x0 +csrrw x0, 0x043, t2 +csrrs x0, 0x043, t2 +csrrc x0, 0x043, t2 +csrrwi x0, 0x043, 1 +csrrsi x0, 0x043, 1 +csrrci x0, 0x043, 1 + +# uip +# name +# CHECK-INST: csrrs t1, UIP, zero +# CHECK-INST: csrrw zero, UIP, t2 +# CHECK-INST: csrrs zero, UIP, t2 +# CHECK-INST: csrrc zero, UIP, t2 +# CHECK-INST: csrrwi zero, UIP, 1 +# CHECK-INST: csrrsi zero, UIP, 1 +# CHECK-INST: csrrci zero, UIP, 1 +# uimm12 +# CHECK-INST: csrrs t1, UIP, zero +# CHECK-INST: csrrw zero, UIP, t2 +# CHECK-INST: csrrs zero, UIP, t2 +# CHECK-INST: csrrc zero, UIP, t2 +# CHECK-INST: csrrwi zero, UIP, 1 +# CHECK-INST: csrrsi zero, UIP, 1 +# CHECK-INST: csrrci zero, UIP, 1 +# aliases +# CHECK-INST-ALIAS: csrr t1, UIP +# CHECK-INST-ALIAS: csrw UIP, t2 +# CHECK-INST-ALIAS: csrs UIP, t2 +# CHECK-INST-ALIAS: csrc UIP, t2 +# CHECK-INST-ALIAS: csrwi UIP, 1 +# CHECK-INST-ALIAS: csrsi UIP, 1 +# CHECK-INST-ALIAS: csrci UIP, 1 +# aliases with uimm12 +# CHECK-INST-ALIAS: csrr t1, UIP +# CHECK-INST-ALIAS: csrw UIP, t2 +# CHECK-INST-ALIAS: csrs UIP, t2 +# CHECK-INST-ALIAS: csrc UIP, t2 +# CHECK-INST-ALIAS: csrwi UIP, 1 +# CHECK-INST-ALIAS: csrsi UIP, 1 +# CHECK-INST-ALIAS: csrci UIP, 1 +# name +csrrs t1, uip, x0 +csrrw x0, uip, t2 +csrrs x0, uip, t2 +csrrc x0, uip, t2 +csrrwi x0, uip, 1 +csrrsi x0, uip, 1 +csrrci x0, uip, 1 +# uimm12 +csrrs t1, 0x044, x0 +csrrw x0, 0x044, t2 +csrrs x0, 0x044, t2 +csrrc x0, 0x044, t2 +csrrwi x0, 0x044, 1 +csrrsi x0, 0x044, 1 +csrrci x0, 0x044, 1 + +################################## +# User Floating Pont CSRs +################################## + +# fflags +# name +# CHECK-INST: csrrs t1, FFLAGS, zero +# CHECK-INST: csrrw zero, FFLAGS, t2 +# CHECK-INST: csrrs zero, FFLAGS, t2 +# CHECK-INST: csrrc zero, FFLAGS, t2 +# CHECK-INST: csrrwi zero, FFLAGS, 1 +# CHECK-INST: csrrsi zero, FFLAGS, 1 +# CHECK-INST: csrrci zero, FFLAGS, 1 +# uimm12 +# CHECK-INST: csrrs t1, FFLAGS, zero +# CHECK-INST: csrrw zero, FFLAGS, t2 +# CHECK-INST: csrrs zero, FFLAGS, t2 +# CHECK-INST: csrrc zero, FFLAGS, t2 +# CHECK-INST: csrrwi zero, FFLAGS, 1 +# CHECK-INST: csrrsi zero, FFLAGS, 1 +# CHECK-INST: csrrci zero, FFLAGS, 1 +# aliases +# CHECK-INST-ALIAS: csrr t1, FFLAGS +# CHECK-INST-ALIAS: csrw FFLAGS, t2 +# CHECK-INST-ALIAS: csrs FFLAGS, t2 +# CHECK-INST-ALIAS: csrc FFLAGS, t2 +# CHECK-INST-ALIAS: csrwi FFLAGS, 1 +# CHECK-INST-ALIAS: csrsi FFLAGS, 1 +# CHECK-INST-ALIAS: csrci FFLAGS, 1 +# aliases with uimm12 +# CHECK-INST-ALIAS: csrr t1, FFLAGS +# CHECK-INST-ALIAS: csrw FFLAGS, t2 +# CHECK-INST-ALIAS: csrs FFLAGS, t2 +# CHECK-INST-ALIAS: csrc FFLAGS, t2 +# CHECK-INST-ALIAS: csrwi FFLAGS, 1 +# CHECK-INST-ALIAS: csrsi FFLAGS, 1 +# CHECK-INST-ALIAS: csrci FFLAGS, 1 +# name +csrrs t1, fflags, x0 +csrrw x0, fflags, t2 +csrrs x0, fflags, t2 +csrrc x0, fflags, t2 +csrrwi x0, fflags, 1 +csrrsi x0, fflags, 1 +csrrci x0, fflags, 1 +# uimm12 +csrrs t1, 0x001, x0 +csrrw x0, 0x001, t2 +csrrs x0, 0x001, t2 +csrrc x0, 0x001, t2 +csrrwi x0, 0x001, 1 +csrrsi x0, 0x001, 1 +csrrci x0, 0x001, 1 + +# frm +# name +# CHECK-INST: csrrs t1, FRM, zero +# CHECK-INST: csrrw zero, FRM, t2 +# CHECK-INST: csrrs zero, FRM, t2 +# CHECK-INST: csrrc zero, FRM, t2 +# CHECK-INST: csrrwi zero, FRM, 1 +# CHECK-INST: csrrsi zero, FRM, 1 +# CHECK-INST: csrrci zero, FRM, 1 +# uimm12 +# CHECK-INST: csrrs t1, FRM, zero +# CHECK-INST: csrrw zero, FRM, t2 +# CHECK-INST: csrrs zero, FRM, t2 +# CHECK-INST: csrrc zero, FRM, t2 +# CHECK-INST: csrrwi zero, FRM, 1 +# CHECK-INST: csrrsi zero, FRM, 1 +# CHECK-INST: csrrci zero, FRM, 1 +# aliases +# CHECK-INST-ALIAS: csrr t1, FRM +# CHECK-INST-ALIAS: csrw FRM, t2 +# CHECK-INST-ALIAS: csrs FRM, t2 +# CHECK-INST-ALIAS: csrc FRM, t2 +# CHECK-INST-ALIAS: csrwi FRM, 1 +# CHECK-INST-ALIAS: csrsi FRM, 1 +# CHECK-INST-ALIAS: csrci FRM, 1 +# aliases with uimm12 +# CHECK-INST-ALIAS: csrr t1, FRM +# CHECK-INST-ALIAS: csrw FRM, t2 +# CHECK-INST-ALIAS: csrs FRM, t2 +# CHECK-INST-ALIAS: csrc FRM, t2 +# CHECK-INST-ALIAS: csrwi FRM, 1 +# CHECK-INST-ALIAS: csrsi FRM, 1 +# CHECK-INST-ALIAS: csrci FRM, 1 +# name +csrrs t1, frm, x0 +csrrw x0, frm, t2 +csrrs x0, frm, t2 +csrrc x0, frm, t2 +csrrwi x0, frm, 1 +csrrsi x0, frm, 1 +csrrci x0, frm, 1 +# uimm12 +csrrs t1, 0x002, x0 +csrrw x0, 0x002, t2 +csrrs x0, 0x002, t2 +csrrc x0, 0x002, t2 +csrrwi x0, 0x002, 1 +csrrsi x0, 0x002, 1 +csrrci x0, 0x002, 1 + +# fcsr +# name +# CHECK-INST: csrrs t1, FCSR, zero +# CHECK-INST: csrrw zero, FCSR, t2 +# CHECK-INST: csrrs zero, FCSR, t2 +# CHECK-INST: csrrc zero, FCSR, t2 +# CHECK-INST: csrrwi zero, FCSR, 1 +# CHECK-INST: csrrsi zero, FCSR, 1 +# CHECK-INST: csrrci zero, FCSR, 1 +# uimm12 +# CHECK-INST: csrrs t1, FCSR, zero +# CHECK-INST: csrrw zero, FCSR, t2 +# CHECK-INST: csrrs zero, FCSR, t2 +# CHECK-INST: csrrc zero, FCSR, t2 +# CHECK-INST: csrrwi zero, FCSR, 1 +# CHECK-INST: csrrsi zero, FCSR, 1 +# CHECK-INST: csrrci zero, FCSR, 1 +# aliases +# CHECK-INST-ALIAS: csrr t1, FCSR +# CHECK-INST-ALIAS: csrw FCSR, t2 +# CHECK-INST-ALIAS: csrs FCSR, t2 +# CHECK-INST-ALIAS: csrc FCSR, t2 +# CHECK-INST-ALIAS: csrwi FCSR, 1 +# CHECK-INST-ALIAS: csrsi FCSR, 1 +# CHECK-INST-ALIAS: csrci FCSR, 1 +# aliases with uimm12 +# CHECK-INST-ALIAS: csrr t1, FCSR +# CHECK-INST-ALIAS: csrw FCSR, t2 +# CHECK-INST-ALIAS: csrs FCSR, t2 +# CHECK-INST-ALIAS: csrc FCSR, t2 +# CHECK-INST-ALIAS: csrwi FCSR, 1 +# CHECK-INST-ALIAS: csrsi FCSR, 1 +# CHECK-INST-ALIAS: csrci FCSR, 1 +# name +csrrs t1, fcsr, x0 +csrrw x0, fcsr, t2 +csrrs x0, fcsr, t2 +csrrc x0, fcsr, t2 +csrrwi x0, fcsr, 1 +csrrsi x0, fcsr, 1 +csrrci x0, fcsr, 1 +# uimm12 +csrrs t1, 0x003, x0 +csrrw x0, 0x003, t2 +csrrs x0, 0x003, t2 +csrrc x0, 0x003, t2 +csrrwi x0, 0x003, 1 +csrrsi x0, 0x003, 1 +csrrci x0, 0x003, 1 + +################################## +# User Counter and Timers +################################## + +# cycle +# name +# CHECK-INST: csrrs t1, CYCLE, zero +# CHECK-INST: csrrw zero, CYCLE, t2 +# CHECK-INST: csrrs zero, CYCLE, t2 +# CHECK-INST: csrrc zero, CYCLE, t2 +# CHECK-INST: csrrwi zero, CYCLE, 1 +# CHECK-INST: csrrsi zero, CYCLE, 1 +# CHECK-INST: csrrci zero, CYCLE, 1 +# uimm12 +# CHECK-INST: csrrs t1, CYCLE, zero +# CHECK-INST: csrrw zero, CYCLE, t2 +# CHECK-INST: csrrs zero, CYCLE, t2 +# CHECK-INST: csrrc zero, CYCLE, t2 +# CHECK-INST: csrrwi zero, CYCLE, 1 +# CHECK-INST: csrrsi zero, CYCLE, 1 +# CHECK-INST: csrrci zero, CYCLE, 1 +# aliases +# CHECK-INST-ALIAS: rdcycle t1 +# CHECK-INST-ALIAS: csrw CYCLE, t2 +# CHECK-INST-ALIAS: csrs CYCLE, t2 +# CHECK-INST-ALIAS: csrc CYCLE, t2 +# CHECK-INST-ALIAS: csrwi CYCLE, 1 +# CHECK-INST-ALIAS: csrsi CYCLE, 1 +# CHECK-INST-ALIAS: csrci CYCLE, 1 +# aliases with uimm12 +# CHECK-INST-ALIAS: rdcycle t1 +# CHECK-INST-ALIAS: csrw CYCLE, t2 +# CHECK-INST-ALIAS: csrs CYCLE, t2 +# CHECK-INST-ALIAS: csrc CYCLE, t2 +# CHECK-INST-ALIAS: csrwi CYCLE, 1 +# CHECK-INST-ALIAS: csrsi CYCLE, 1 +# CHECK-INST-ALIAS: csrci CYCLE, 1 +# name +csrrs t1, cycle, x0 +csrrw x0, cycle, t2 +csrrs x0, cycle, t2 +csrrc x0, cycle, t2 +csrrwi x0, cycle, 1 +csrrsi x0, cycle, 1 +csrrci x0, cycle, 1 +# uimm12 +csrrs t1, 0xC00, x0 +csrrw x0, 0xC00, t2 +csrrs x0, 0xC00, t2 +csrrc x0, 0xC00, t2 +csrrwi x0, 0xC00, 1 +csrrsi x0, 0xC00, 1 +csrrci x0, 0xC00, 1 + +# time +# name +# CHECK-INST: csrrs t1, TIME, zero +# CHECK-INST: csrrw zero, TIME, t2 +# CHECK-INST: csrrs zero, TIME, t2 +# CHECK-INST: csrrc zero, TIME, t2 +# CHECK-INST: csrrwi zero, TIME, 1 +# CHECK-INST: csrrsi zero, TIME, 1 +# CHECK-INST: csrrci zero, TIME, 1 +# uimm12 +# CHECK-INST: csrrs t1, TIME, zero +# CHECK-INST: csrrw zero, TIME, t2 +# CHECK-INST: csrrs zero, TIME, t2 +# CHECK-INST: csrrc zero, TIME, t2 +# CHECK-INST: csrrwi zero, TIME, 1 +# CHECK-INST: csrrsi zero, TIME, 1 +# CHECK-INST: csrrci zero, TIME, 1 +# aliases +# CHECK-INST-ALIAS: rdtime t1 +# CHECK-INST-ALIAS: csrw TIME, t2 +# CHECK-INST-ALIAS: csrs TIME, t2 +# CHECK-INST-ALIAS: csrc TIME, t2 +# CHECK-INST-ALIAS: csrwi TIME, 1 +# CHECK-INST-ALIAS: csrsi TIME, 1 +# CHECK-INST-ALIAS: csrci TIME, 1 +# aliases with uimm12 +# CHECK-INST-ALIAS: rdtime t1 +# CHECK-INST-ALIAS: csrw TIME, t2 +# CHECK-INST-ALIAS: csrs TIME, t2 +# CHECK-INST-ALIAS: csrc TIME, t2 +# CHECK-INST-ALIAS: csrwi TIME, 1 +# CHECK-INST-ALIAS: csrsi TIME, 1 +# CHECK-INST-ALIAS: csrci TIME, 1 +# name +csrrs t1, time, x0 +csrrw x0, time, t2 +csrrs x0, time, t2 +csrrc x0, time, t2 +csrrwi x0, time, 1 +csrrsi x0, time, 1 +csrrci x0, time, 1 +# uimm12 +csrrs t1, 0xC01, x0 +csrrw x0, 0xC01, t2 +csrrs x0, 0xC01, t2 +csrrc x0, 0xC01, t2 +csrrwi x0, 0xC01, 1 +csrrsi x0, 0xC01, 1 +csrrci x0, 0xC01, 1 + +# instret +# name +# CHECK-INST: csrrs t1, INSTRET, zero +# CHECK-INST: csrrw zero, INSTRET, t2 +# CHECK-INST: csrrs zero, INSTRET, t2 +# CHECK-INST: csrrc zero, INSTRET, t2 +# CHECK-INST: csrrwi zero, INSTRET, 1 +# CHECK-INST: csrrsi zero, INSTRET, 1 +# CHECK-INST: csrrci zero, INSTRET, 1 +# uimm12 +# CHECK-INST: csrrs t1, INSTRET, zero +# CHECK-INST: csrrw zero, INSTRET, t2 +# CHECK-INST: csrrs zero, INSTRET, t2 +# CHECK-INST: csrrc zero, INSTRET, t2 +# CHECK-INST: csrrwi zero, INSTRET, 1 +# CHECK-INST: csrrsi zero, INSTRET, 1 +# CHECK-INST: csrrci zero, INSTRET, 1 +# aliases +# CHECK-INST-ALIAS: rdinstret t1 +# CHECK-INST-ALIAS: csrw INSTRET, t2 +# CHECK-INST-ALIAS: csrs INSTRET, t2 +# CHECK-INST-ALIAS: csrc INSTRET, t2 +# CHECK-INST-ALIAS: csrwi INSTRET, 1 +# CHECK-INST-ALIAS: csrsi INSTRET, 1 +# CHECK-INST-ALIAS: csrci INSTRET, 1 +# aliases with uimm12 +# CHECK-INST-ALIAS: rdinstret t1 +# CHECK-INST-ALIAS: csrw INSTRET, t2 +# CHECK-INST-ALIAS: csrs INSTRET, t2 +# CHECK-INST-ALIAS: csrc INSTRET, t2 +# CHECK-INST-ALIAS: csrwi INSTRET, 1 +# CHECK-INST-ALIAS: csrsi INSTRET, 1 +# CHECK-INST-ALIAS: csrci INSTRET, 1 +# name +csrrs t1, instret, x0 +csrrw x0, instret, t2 +csrrs x0, instret, t2 +csrrc x0, instret, t2 +csrrwi x0, instret, 1 +csrrsi x0, instret, 1 +csrrci x0, instret, 1 +# uimm12 +csrrs t1, 0xC02, x0 +csrrw x0, 0xC02, t2 +csrrs x0, 0xC02, t2 +csrrc x0, 0xC02, t2 +csrrwi x0, 0xC02, 1 +csrrsi x0, 0xC02, 1 +csrrci x0, 0xC02, 1 + +#FIXME hpmcounter3..31 +#FIXME cycleh +#FIXME timeh +#FIXME instreth +#FIXME hpmcounterh3..31 + +