Index: lib/Target/RISCV/RISCVInstrInfo.td
===================================================================
--- lib/Target/RISCV/RISCVInstrInfo.td
+++ lib/Target/RISCV/RISCVInstrInfo.td
@@ -484,6 +484,8 @@
 // TODO tail
 
 def : InstAlias<"fence", (FENCE 0xF, 0xF)>; // 0xF == iorw
+def : InstAlias<"sfence.vma",     (SFENCE_VMA      X0, X0)>;
+def : InstAlias<"sfence.vma $rs", (SFENCE_VMA GPR:$rs, X0)>;
 
 // CSR Addresses: 0xC00 == cycle,  0xC01 == time,  0xC02 == instret
 //                0xC80 == cycleh, 0xC81 == timeh, 0xC82 == instreth
@@ -497,17 +499,63 @@
 def : InstAlias<"rdtimeh $rd",    (CSRRS GPR:$rd, 0xC81, X0)>;
 } // Predicates = [IsRV32]
 
-def : InstAlias<"csrr $rd, $csr", (CSRRS GPR:$rd, uimm12:$csr,      X0)>;
-def : InstAlias<"csrw $csr, $rs", (CSRRW      X0, uimm12:$csr, GPR:$rs)>;
-def : InstAlias<"csrs $csr, $rs", (CSRRS      X0, uimm12:$csr, GPR:$rs)>;
-def : InstAlias<"csrc $csr, $rs", (CSRRC      X0, uimm12:$csr, GPR:$rs)>;
+multiclass CSRAliases {
+  // Aliases for the short canonical forms, using CSR register id.
+  def : InstAlias<"csrr $rd, $csr", (CSRRS GPR:$rd, uimm12:$csr,      X0)>;
+  def : InstAlias<"csrw $csr, $rs", (CSRRW      X0, uimm12:$csr, GPR:$rs)>;
+  def : InstAlias<"csrs $csr, $rs", (CSRRS      X0, uimm12:$csr, GPR:$rs)>;
+  def : InstAlias<"csrc $csr, $rs", (CSRRC      X0, uimm12:$csr, GPR:$rs)>;
+
+  def : InstAlias<"csrwi $csr, $imm", (CSRRWI X0, uimm12:$csr, uimm5:$imm)>;
+  def : InstAlias<"csrsi $csr, $imm", (CSRRSI X0, uimm12:$csr, uimm5:$imm)>;
+  def : InstAlias<"csrci $csr, $imm", (CSRRCI X0, uimm12:$csr, uimm5:$imm)>;
+}
 
-def : InstAlias<"csrwi $csr, $imm", (CSRRWI X0, uimm12:$csr, uimm5:$imm)>;
-def : InstAlias<"csrsi $csr, $imm", (CSRRSI X0, uimm12:$csr, uimm5:$imm)>;
-def : InstAlias<"csrci $csr, $imm", (CSRRCI X0, uimm12:$csr, uimm5:$imm)>;
+defm : CSRAliases;
 
-def : InstAlias<"sfence.vma",     (SFENCE_VMA      X0, X0)>;
-def : InstAlias<"sfence.vma $rs", (SFENCE_VMA GPR:$rs, X0)>;
+multiclass MCSRAliases<string csr, bits<12> enc> {
+  // Aliases using Machine CSR register name.
+  def : InstAlias<!strconcat("csrrs $rd, ", csr, ", x0"), (CSRRS GPR:$rd, enc, X0)>;
+  def : InstAlias<!strconcat("csrrw x0, ", csr, ", $rs"), (CSRRW X0, enc, GPR:$rs)>;
+  def : InstAlias<!strconcat("csrrs x0, ", csr, ", $rs"), (CSRRS X0, enc, GPR:$rs)>;
+  def : InstAlias<!strconcat("csrrc x0, ", csr, ", $rs"), (CSRRC X0, enc, GPR:$rs)>;
+
+  def : InstAlias<!strconcat("csrrwi x0, ", csr, ", $imm"), (CSRRWI X0, enc, uimm5:$imm)>;
+  def : InstAlias<!strconcat("csrrsi x0, ", csr, ", $imm"), (CSRRSI X0, enc, uimm5:$imm)>;
+  def : InstAlias<!strconcat("csrrci x0, ", csr, ", $imm"), (CSRRCI X0, enc, uimm5:$imm)>;
+
+  // Aliases for the short canonical forms using Machine CSR register name.
+  def : InstAlias<!strconcat("csrr $rd, ", csr), (CSRRS GPR:$rd, enc, X0)>;
+  def : InstAlias<!strconcat("csrw ", csr, ", $rs"), (CSRRW X0, enc, GPR:$rs)>;
+  def : InstAlias<!strconcat("csrs ", csr, ", $rs"), (CSRRS X0, enc, GPR:$rs)>;
+  def : InstAlias<!strconcat("csrc ", csr, ", $rs"), (CSRRC X0, enc, GPR:$rs)>;
+
+  def : InstAlias<!strconcat("csrwi ", csr, ", $imm"), (CSRRWI X0, enc, uimm5:$imm)>;
+  def : InstAlias<!strconcat("csrsi ", csr, ", $imm"), (CSRRSI X0, enc, uimm5:$imm)>;
+  def : InstAlias<!strconcat("csrci ", csr, ", $imm"), (CSRRCI X0, enc, uimm5:$imm)>;
+}
+
+// Machine Information Registers.
+defm : MCSRAliases<"mvendorid", ENC_MVENDORID.Value>;
+defm : MCSRAliases<"marchid", ENC_MARCHID.Value>;
+defm : MCSRAliases<"mimpid", ENC_MIMPID.Value>;
+defm : MCSRAliases<"mhartid", ENC_MHARTID.Value>;
+
+// Machine Trap Setup.
+defm : MCSRAliases<"mstatus", ENC_MSTATUS.Value>;
+defm : MCSRAliases<"misa", ENC_MISA.Value>;
+defm : MCSRAliases<"mdeleg", ENC_MDELEG.Value>;
+defm : MCSRAliases<"mideleg", ENC_MIDELEG.Value>;
+defm : MCSRAliases<"mie", ENC_MIE.Value>;
+defm : MCSRAliases<"mtvect", ENC_MTVECT.Value>;
+defm : MCSRAliases<"mcounteren", ENC_MCOUNTEREN.Value>;
+
+// Machine Trap Handling.
+defm : MCSRAliases<"mscratch", ENC_MSCRATCH .Value>;
+defm : MCSRAliases<"mepc", ENC_MEPC.Value>;
+defm : MCSRAliases<"mcause", ENC_MCAUSE.Value>;
+defm : MCSRAliases<"mtval", ENC_MTVAL.Value>;
+defm : MCSRAliases<"mip", ENC_MIP.Value>;
 
 //===----------------------------------------------------------------------===//
 // Pseudo-instructions and codegen patterns
Index: lib/Target/RISCV/RISCVRegisterInfo.td
===================================================================
--- lib/Target/RISCV/RISCVRegisterInfo.td
+++ lib/Target/RISCV/RISCVRegisterInfo.td
@@ -204,3 +204,66 @@
   (sequence "F%u_64", 10, 15),
   (sequence "F%u_64", 8, 9)
 )>;
+
+// The following CSR encodings match those given in Table 2.4 in the
+// RISC-V Instruction Set Manual Vlolume II: Privileged Architecture.
+class RISCVCSREnc<bits<12> val> {
+  bits<12> Value = val;
+}
+
+// Machine Information Registers.
+def ENC_MVENDORID : RISCVCSREnc<0xF11>;
+def ENC_MARCHID   : RISCVCSREnc<0xF12>;
+def ENC_MIMPID    : RISCVCSREnc<0xF13>;
+def ENC_MHARTID   : RISCVCSREnc<0xF14>;
+
+// Machine Trap Setup.
+def ENC_MSTATUS     : RISCVCSREnc<0x300>;
+def ENC_MISA        : RISCVCSREnc<0x301>;
+def ENC_MDELEG      : RISCVCSREnc<0x302>;
+def ENC_MIDELEG     : RISCVCSREnc<0x303>;
+def ENC_MIE         : RISCVCSREnc<0x304>;
+def ENC_MTVECT      : RISCVCSREnc<0x305>;
+def ENC_MCOUNTEREN  : RISCVCSREnc<0x306>;
+
+// Machine Trap Handling.
+def ENC_MSCRATCH    : RISCVCSREnc<0x340>;
+def ENC_MEPC        : RISCVCSREnc<0x341>;
+def ENC_MCAUSE      : RISCVCSREnc<0x342>;
+def ENC_MTVAL       : RISCVCSREnc<0x343>;
+def ENC_MIP         : RISCVCSREnc<0x344>;
+
+// TODO: Machine Counter/Timers.
+// TODO: Machine Counter Setup.
+
+// RISC-V CSRs class.
+let Namespace = "RISCV" in {
+class RISCVCSRReg<
+  RISCVCSREnc enc, string n, list<string> alt = []> : Register<n> {
+    let HWEncoding{11-0} = enc.Value;
+    let AltNames = alt;
+  }
+}
+
+// Machine Information Registers.
+def MVENDORID : RISCVCSRReg<ENC_MVENDORID, "mvendorid">, DwarfRegNum<[1000]>;
+def MARCHID   : RISCVCSRReg<ENC_MARCHID, "marchid">, DwarfRegNum<[1001]>;
+def MIMPID    : RISCVCSRReg<ENC_MIMPID, "mimpid">, DwarfRegNum<[1002]>;
+def MHARTID   : RISCVCSRReg<ENC_MHARTID, "mhartid">, DwarfRegNum<[1003]>;
+
+// Machine Trap Setup.
+def MSTATUS     : RISCVCSRReg<ENC_MSTATUS, "mstatus">, DwarfRegNum<[1004]>;
+def MISA        : RISCVCSRReg<ENC_MISA, "misa">, DwarfRegNum<[1005]>;
+def MDELEG      : RISCVCSRReg<ENC_MDELEG, "mdeleg">, DwarfRegNum<[1006]>;
+def MIDELEG     : RISCVCSRReg<ENC_MIDELEG, "mideleg">, DwarfRegNum<[1007]>;
+def MIE         : RISCVCSRReg<ENC_MIE, "mie">, DwarfRegNum<[1008]>;
+def MTVECT      : RISCVCSRReg<ENC_MTVECT, "mtvect">, DwarfRegNum<[1009]>;
+def MCOUNTEREN  : RISCVCSRReg<ENC_MCOUNTEREN, "mcounteren">, DwarfRegNum<[1010]>;
+
+// Machine Trap Handling.
+def MSCRATCH    : RISCVCSRReg<ENC_MSCRATCH, "mscratch">, DwarfRegNum<[1011]>;
+def MEPC        : RISCVCSRReg<ENC_MEPC, "mepc">, DwarfRegNum<[1012]>;
+def MCAUSE      : RISCVCSRReg<ENC_MCAUSE, "mcause">, DwarfRegNum<[1013]>;
+def MTVAL       : RISCVCSRReg<ENC_MTVAL, "mtval">, DwarfRegNum<[1014]>;
+def MIP         : RISCVCSRReg<ENC_MIP, "mip">, DwarfRegNum<[1015]>;
+
Index: test/MC/RISCV/mcsr-aliases.s
===================================================================
--- /dev/null
+++ test/MC/RISCV/mcsr-aliases.s
@@ -0,0 +1,487 @@
+# RUN: llvm-mc -filetype=obj -triple riscv32  < %s \
+# RUN:     | llvm-objdump -d  -riscv-no-aliases - \
+# RUN:     | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64  < %s \
+# RUN:     | llvm-objdump -d  -riscv-no-aliases - \
+# RUN:     | FileCheck -check-prefix=CHECK-INST %s
+
+# Aliases for mstatus.
+# CHECK-INST: csrrs t1, 768, zero
+# CHECK-INST: csrrw zero, 768, t2
+# CHECK-INST: csrrs zero, 768, t2
+# CHECK-INST: csrrc zero, 768, t2
+# CHECK-INST: csrrwi zero, 768, 1
+# CHECK-INST: csrrsi zero, 768, 1
+# CHECK-INST: csrrci zero, 768, 1
+csrrs t1, mstatus, x0
+csrrw x0, mstatus, t2
+csrrs x0, mstatus, t2
+csrrc x0, mstatus, t2
+csrrwi x0, mstatus, 1
+csrrsi x0, mstatus, 1
+csrrci x0, mstatus, 1
+# CHECK-INST: csrrs t1, 768, zero
+# CHECK-INST: csrrw zero, 768, t2
+# CHECK-INST: csrrs zero, 768, t2
+# CHECK-INST: csrrc zero, 768, t2
+# CHECK-INST: csrrwi zero, 768, 1
+# CHECK-INST: csrrsi zero, 768, 1
+# CHECK-INST: csrrci zero, 768, 1
+csrr t1, mstatus
+csrw mstatus, t2
+csrs mstatus, t2
+csrc mstatus, t2
+csrwi mstatus, 1
+csrsi mstatus, 1
+csrci mstatus, 1
+
+# Aliases for misa.
+# CHECK-INST: csrrs t1, 769, zero
+# CHECK-INST: csrrw zero, 769, t2
+# CHECK-INST: csrrs zero, 769, t2
+# CHECK-INST: csrrc zero, 769, t2
+# CHECK-INST: csrrwi zero, 769, 1
+# CHECK-INST: csrrsi zero, 769, 1
+# CHECK-INST: csrrci zero, 769, 1
+csrrs t1, misa, x0
+csrrw x0, misa, t2
+csrrs x0, misa, t2
+csrrc x0, misa, t2
+csrrwi x0, misa, 1
+csrrsi x0, misa, 1
+csrrci x0, misa, 1
+# CHECK-INST: csrrs t1, 769, zero
+# CHECK-INST: csrrw zero, 769, t2
+# CHECK-INST: csrrs zero, 769, t2
+# CHECK-INST: csrrc zero, 769, t2
+# CHECK-INST: csrrwi zero, 769, 1
+# CHECK-INST: csrrsi zero, 769, 1
+# CHECK-INST: csrrci zero, 769, 1
+csrr t1, misa
+csrw misa, t2
+csrs misa, t2
+csrc misa, t2
+csrwi misa, 1
+csrsi misa, 1
+csrci misa, 1
+
+# Aliases for mdeleg.
+# CHECK-INST: csrrs t1, 770, zero
+# CHECK-INST: csrrw zero, 770, t2
+# CHECK-INST: csrrs zero, 770, t2
+# CHECK-INST: csrrc zero, 770, t2
+# CHECK-INST: csrrwi zero, 770, 1
+# CHECK-INST: csrrsi zero, 770, 1
+# CHECK-INST: csrrci zero, 770, 1
+csrrs t1, mdeleg, x0
+csrrw x0, mdeleg, t2
+csrrs x0, mdeleg, t2
+csrrc x0, mdeleg, t2
+csrrwi x0, mdeleg, 1
+csrrsi x0, mdeleg, 1
+csrrci x0, mdeleg, 1
+# CHECK-INST: csrrs t1, 770, zero
+# CHECK-INST: csrrw zero, 770, t2
+# CHECK-INST: csrrs zero, 770, t2
+# CHECK-INST: csrrc zero, 770, t2
+# CHECK-INST: csrrwi zero, 770, 1
+# CHECK-INST: csrrsi zero, 770, 1
+# CHECK-INST: csrrci zero, 770, 1
+csrr t1, mdeleg
+csrw mdeleg, t2
+csrs mdeleg, t2
+csrc mdeleg, t2
+csrwi mdeleg, 1
+csrsi mdeleg, 1
+csrci mdeleg, 1
+
+# Aliases for mideleg
+# CHECK-INST: csrrs t1, 771, zero
+# CHECK-INST: csrrw zero, 771, t2
+# CHECK-INST: csrrs zero, 771, t2
+# CHECK-INST: csrrc zero, 771, t2
+# CHECK-INST: csrrwi zero, 771, 1
+# CHECK-INST: csrrsi zero, 771, 1
+# CHECK-INST: csrrci zero, 771, 1
+csrrs t1, mideleg, x0
+csrrw x0, mideleg, t2
+csrrs x0, mideleg, t2
+csrrc x0, mideleg, t2
+csrrwi x0, mideleg, 1
+csrrsi x0, mideleg, 1
+csrrci x0, mideleg, 1
+# CHECK-INST: csrrs t1, 771, zero
+# CHECK-INST: csrrw zero, 771, t2
+# CHECK-INST: csrrs zero, 771, t2
+# CHECK-INST: csrrc zero, 771, t2
+# CHECK-INST: csrrwi zero, 771, 1
+# CHECK-INST: csrrsi zero, 771, 1
+# CHECK-INST: csrrci zero, 771, 1
+csrr t1, mideleg
+csrw mideleg, t2
+csrs mideleg, t2
+csrc mideleg, t2
+csrwi mideleg, 1
+csrsi mideleg, 1
+csrci mideleg, 1
+
+# Aliases for mie
+# CHECK-INST: csrrs t1, 772, zero
+# CHECK-INST: csrrw zero, 772, t2
+# CHECK-INST: csrrs zero, 772, t2
+# CHECK-INST: csrrc zero, 772, t2
+# CHECK-INST: csrrwi zero, 772, 1
+# CHECK-INST: csrrsi zero, 772, 1
+# CHECK-INST: csrrci zero, 772, 1
+csrrs t1, mie, x0
+csrrw x0, mie, t2
+csrrs x0, mie, t2
+csrrc x0, mie, t2
+csrrwi x0, mie, 1
+csrrsi x0, mie, 1
+csrrci x0, mie, 1
+# CHECK-INST: csrrs t1, 772, zero
+# CHECK-INST: csrrw zero, 772, t2
+# CHECK-INST: csrrs zero, 772, t2
+# CHECK-INST: csrrc zero, 772, t2
+# CHECK-INST: csrrwi zero, 772, 1
+# CHECK-INST: csrrsi zero, 772, 1
+# CHECK-INST: csrrci zero, 772, 1
+csrr t1, mie
+csrw mie, t2
+csrs mie, t2
+csrc mie, t2
+csrwi mie, 1
+csrsi mie, 1
+csrci mie, 1
+
+# Aliases for mtvect
+# CHECK-INST: csrrs t1, 773, zero
+# CHECK-INST: csrrw zero, 773, t2
+# CHECK-INST: csrrs zero, 773, t2
+# CHECK-INST: csrrc zero, 773, t2
+# CHECK-INST: csrrwi zero, 773, 1
+# CHECK-INST: csrrsi zero, 773, 1
+# CHECK-INST: csrrci zero, 773, 1
+csrrs t1, mtvect, x0
+csrrw x0, mtvect, t2
+csrrs x0, mtvect, t2
+csrrc x0, mtvect, t2
+csrrwi x0, mtvect, 1
+csrrsi x0, mtvect, 1
+csrrci x0, mtvect, 1
+# CHECK-INST: csrrs t1, 773, zero
+# CHECK-INST: csrrw zero, 773, t2
+# CHECK-INST: csrrs zero, 773, t2
+# CHECK-INST: csrrc zero, 773, t2
+# CHECK-INST: csrrwi zero, 773, 1
+# CHECK-INST: csrrsi zero, 773, 1
+# CHECK-INST: csrrci zero, 773, 1
+csrr t1, mtvect
+csrw mtvect, t2
+csrs mtvect, t2
+csrc mtvect, t2
+csrwi mtvect, 1
+csrsi mtvect, 1
+csrci mtvect, 1
+
+# Aliases for mcounteren
+# CHECK-INST: csrrs t1, 774, zero
+# CHECK-INST: csrrw zero, 774, t2
+# CHECK-INST: csrrs zero, 774, t2
+# CHECK-INST: csrrc zero, 774, t2
+# CHECK-INST: csrrwi zero, 774, 1
+# CHECK-INST: csrrsi zero, 774, 1
+# CHECK-INST: csrrci zero, 774, 1
+csrrs t1, mcounteren, x0
+csrrw x0, mcounteren, t2
+csrrs x0, mcounteren, t2
+csrrc x0, mcounteren, t2
+csrrwi x0, mcounteren, 1
+csrrsi x0, mcounteren, 1
+csrrci x0, mcounteren, 1
+# CHECK-INST: csrrs t1, 774, zero
+# CHECK-INST: csrrw zero, 774, t2
+# CHECK-INST: csrrs zero, 774, t2
+# CHECK-INST: csrrc zero, 774, t2
+# CHECK-INST: csrrwi zero, 774, 1
+# CHECK-INST: csrrsi zero, 774, 1
+# CHECK-INST: csrrci zero, 774, 1
+csrr t1, mcounteren
+csrw mcounteren, t2
+csrs mcounteren, t2
+csrc mcounteren, t2
+csrwi mcounteren, 1
+csrsi mcounteren, 1
+csrci mcounteren, 1
+
+# Aliases for mscratch
+# CHECK-INST: csrrs t1, 832, zero
+# CHECK-INST: csrrw zero, 832, t2
+# CHECK-INST: csrrs zero, 832, t2
+# CHECK-INST: csrrc zero, 832, t2
+# CHECK-INST: csrrwi zero, 832, 1
+# CHECK-INST: csrrsi zero, 832, 1
+# CHECK-INST: csrrci zero, 832, 1
+csrrs t1, mscratch, x0
+csrrw x0, mscratch, t2
+csrrs x0, mscratch, t2
+csrrc x0, mscratch, t2
+csrrwi x0, mscratch, 1
+csrrsi x0, mscratch, 1
+csrrci x0, mscratch, 1
+# CHECK-INST: csrrs t1, 832, zero
+# CHECK-INST: csrrw zero, 832, t2
+# CHECK-INST: csrrs zero, 832, t2
+# CHECK-INST: csrrc zero, 832, t2
+# CHECK-INST: csrrwi zero, 832, 1
+# CHECK-INST: csrrsi zero, 832, 1
+# CHECK-INST: csrrci zero, 832, 1
+csrr t1, mscratch
+csrw mscratch, t2
+csrs mscratch, t2
+csrc mscratch, t2
+csrwi mscratch, 1
+csrsi mscratch, 1
+csrci mscratch, 1
+
+# Aliases for mepc
+# CHECK-INST: csrrs t1, 833, zero
+# CHECK-INST: csrrw zero, 833, t2
+# CHECK-INST: csrrs zero, 833, t2
+# CHECK-INST: csrrc zero, 833, t2
+# CHECK-INST: csrrwi zero, 833, 1
+# CHECK-INST: csrrsi zero, 833, 1
+# CHECK-INST: csrrci zero, 833, 1
+csrrs t1, mepc, x0
+csrrw x0, mepc, t2
+csrrs x0, mepc, t2
+csrrc x0, mepc, t2
+csrrwi x0, mepc, 1
+csrrsi x0, mepc, 1
+csrrci x0, mepc, 1
+# CHECK-INST: csrrs t1, 833, zero
+# CHECK-INST: csrrw zero, 833, t2
+# CHECK-INST: csrrs zero, 833, t2
+# CHECK-INST: csrrc zero, 833, t2
+# CHECK-INST: csrrwi zero, 833, 1
+# CHECK-INST: csrrsi zero, 833, 1
+# CHECK-INST: csrrci zero, 833, 1
+csrr t1, mepc
+csrw mepc, t2
+csrs mepc, t2
+csrc mepc, t2
+csrwi mepc, 1
+csrsi mepc, 1
+csrci mepc, 1
+
+# Aliases for mcause
+# CHECK-INST: csrrs t1, 834, zero
+# CHECK-INST: csrrw zero, 834, t2
+# CHECK-INST: csrrs zero, 834, t2
+# CHECK-INST: csrrc zero, 834, t2
+# CHECK-INST: csrrwi zero, 834, 1
+# CHECK-INST: csrrsi zero, 834, 1
+# CHECK-INST: csrrci zero, 834, 1
+csrrs t1, mcause, x0
+csrrw x0, mcause, t2
+csrrs x0, mcause, t2
+csrrc x0, mcause, t2
+csrrwi x0, mcause, 1
+csrrsi x0, mcause, 1
+csrrci x0, mcause, 1
+# CHECK-INST: csrrs t1, 834, zero
+# CHECK-INST: csrrw zero, 834, t2
+# CHECK-INST: csrrs zero, 834, t2
+# CHECK-INST: csrrc zero, 834, t2
+# CHECK-INST: csrrwi zero, 834, 1
+# CHECK-INST: csrrsi zero, 834, 1
+# CHECK-INST: csrrci zero, 834, 1
+csrr t1, mcause
+csrw mcause, t2
+csrs mcause, t2
+csrc mcause, t2
+csrwi mcause, 1
+csrsi mcause, 1
+csrci mcause, 1
+
+# Aliases for mtval
+# CHECK-INST: csrrs t1, 835, zero
+# CHECK-INST: csrrw zero, 835, t2
+# CHECK-INST: csrrs zero, 835, t2
+# CHECK-INST: csrrc zero, 835, t2
+# CHECK-INST: csrrwi zero, 835, 1
+# CHECK-INST: csrrsi zero, 835, 1
+# CHECK-INST: csrrci zero, 835, 1
+csrrs t1, mtval, x0
+csrrw x0, mtval, t2
+csrrs x0, mtval, t2
+csrrc x0, mtval, t2
+csrrwi x0, mtval, 1
+csrrsi x0, mtval, 1
+csrrci x0, mtval, 1
+# CHECK-INST: csrrs t1, 835, zero
+# CHECK-INST: csrrw zero, 835, t2
+# CHECK-INST: csrrs zero, 835, t2
+# CHECK-INST: csrrc zero, 835, t2
+# CHECK-INST: csrrwi zero, 835, 1
+# CHECK-INST: csrrsi zero, 835, 1
+# CHECK-INST: csrrci zero, 835, 1
+csrr t1, mtval
+csrw mtval, t2
+csrs mtval, t2
+csrc mtval, t2
+csrwi mtval, 1
+csrsi mtval, 1
+csrci mtval, 1
+
+# Aliases for mip
+# CHECK-INST: csrrs t1, 836, zero
+# CHECK-INST: csrrw zero, 836, t2
+# CHECK-INST: csrrs zero, 836, t2
+# CHECK-INST: csrrc zero, 836, t2
+# CHECK-INST: csrrwi zero, 836, 1
+# CHECK-INST: csrrsi zero, 836, 1
+# CHECK-INST: csrrci zero, 836, 1
+csrrs t1, mip, x0
+csrrw x0, mip, t2
+csrrs x0, mip, t2
+csrrc x0, mip, t2
+csrrwi x0, mip, 1
+csrrsi x0, mip, 1
+csrrci x0, mip, 1
+# CHECK-INST: csrrs t1, 836, zero
+# CHECK-INST: csrrw zero, 836, t2
+# CHECK-INST: csrrs zero, 836, t2
+# CHECK-INST: csrrc zero, 836, t2
+# CHECK-INST: csrrwi zero, 836, 1
+# CHECK-INST: csrrsi zero, 836, 1
+# CHECK-INST: csrrci zero, 836, 1
+csrr t1, mip
+csrw mip, t2
+csrs mip, t2
+csrc mip, t2
+csrwi mip, 1
+csrsi mip, 1
+csrci mip, 1
+
+# Aliases for mvendorid
+# CHECK-INST: csrrs t1, 3857, zero
+# CHECK-INST: csrrw zero, 3857, t2
+# CHECK-INST: csrrs zero, 3857, t2
+# CHECK-INST: csrrc zero, 3857, t2
+# CHECK-INST: csrrwi zero, 3857, 1
+# CHECK-INST: csrrsi zero, 3857, 1
+# CHECK-INST: csrrci zero, 3857, 1
+csrrs t1, mvendorid, x0
+csrrw x0, mvendorid, t2
+csrrs x0, mvendorid, t2
+csrrc x0, mvendorid, t2
+csrrwi x0, mvendorid, 1
+csrrsi x0, mvendorid, 1
+csrrci x0, mvendorid, 1
+# CHECK-INST: csrrs t1, 3857, zero
+# CHECK-INST: csrrw zero, 3857, t2
+# CHECK-INST: csrrs zero, 3857, t2
+# CHECK-INST: csrrc zero, 3857, t2
+# CHECK-INST: csrrwi zero, 3857, 1
+# CHECK-INST: csrrsi zero, 3857, 1
+# CHECK-INST: csrrci zero, 3857, 1
+csrr t1, mvendorid
+csrw mvendorid, t2
+csrs mvendorid, t2
+csrc mvendorid, t2
+csrwi mvendorid, 1
+csrsi mvendorid, 1
+csrci mvendorid, 1
+
+# Aliases for marchid
+# CHECK-INST: csrrs t1, 3858, zero
+# CHECK-INST: csrrw zero, 3858, t2
+# CHECK-INST: csrrs zero, 3858, t2
+# CHECK-INST: csrrc zero, 3858, t2
+# CHECK-INST: csrrwi zero, 3858, 1
+# CHECK-INST: csrrsi zero, 3858, 1
+# CHECK-INST: csrrci zero, 3858, 1
+csrrs t1, marchid, x0
+csrrw x0, marchid, t2
+csrrs x0, marchid, t2
+csrrc x0, marchid, t2
+csrrwi x0, marchid, 1
+csrrsi x0, marchid, 1
+csrrci x0, marchid, 1
+# CHECK-INST: csrrs t1, 3858, zero
+# CHECK-INST: csrrw zero, 3858, t2
+# CHECK-INST: csrrs zero, 3858, t2
+# CHECK-INST: csrrc zero, 3858, t2
+# CHECK-INST: csrrwi zero, 3858, 1
+# CHECK-INST: csrrsi zero, 3858, 1
+# CHECK-INST: csrrci zero, 3858, 1
+csrr t1, marchid
+csrw marchid, t2
+csrs marchid, t2
+csrc marchid, t2
+csrwi marchid, 1
+csrsi marchid, 1
+csrci marchid, 1
+
+# Aliases for mimpid
+# CHECK-INST: csrrs t1, 3859, zero
+# CHECK-INST: csrrw zero, 3859, t2
+# CHECK-INST: csrrs zero, 3859, t2
+# CHECK-INST: csrrc zero, 3859, t2
+# CHECK-INST: csrrwi zero, 3859, 1
+# CHECK-INST: csrrsi zero, 3859, 1
+# CHECK-INST: csrrci zero, 3859, 1
+csrrs t1, mimpid, x0
+csrrw x0, mimpid, t2
+csrrs x0, mimpid, t2
+csrrc x0, mimpid, t2
+csrrwi x0, mimpid, 1
+csrrsi x0, mimpid, 1
+csrrci x0, mimpid, 1
+# CHECK-INST: csrrs t1, 3859, zero
+# CHECK-INST: csrrw zero, 3859, t2
+# CHECK-INST: csrrs zero, 3859, t2
+# CHECK-INST: csrrc zero, 3859, t2
+# CHECK-INST: csrrwi zero, 3859, 1
+# CHECK-INST: csrrsi zero, 3859, 1
+# CHECK-INST: csrrci zero, 3859, 1
+csrr t1, mimpid
+csrw mimpid, t2
+csrs mimpid, t2
+csrc mimpid, t2
+csrwi mimpid, 1
+csrsi mimpid, 1
+csrci mimpid, 1
+
+# Aliases for mhartid
+# CHECK-INST: csrrs t1, 3860, zero
+# CHECK-INST: csrrw zero, 3860, t2
+# CHECK-INST: csrrs zero, 3860, t2
+# CHECK-INST: csrrc zero, 3860, t2
+# CHECK-INST: csrrwi zero, 3860, 1
+# CHECK-INST: csrrsi zero, 3860, 1
+# CHECK-INST: csrrci zero, 3860, 1
+csrrs t1, mhartid, x0
+csrrw x0, mhartid, t2
+csrrs x0, mhartid, t2
+csrrc x0, mhartid, t2
+csrrwi x0, mhartid, 1
+csrrsi x0, mhartid, 1
+csrrci x0, mhartid, 1
+# CHECK-INST: csrrs t1, 3860, zero
+# CHECK-INST: csrrw zero, 3860, t2
+# CHECK-INST: csrrs zero, 3860, t2
+# CHECK-INST: csrrc zero, 3860, t2
+# CHECK-INST: csrrwi zero, 3860, 1
+# CHECK-INST: csrrsi zero, 3860, 1
+# CHECK-INST: csrrci zero, 3860, 1
+csrr t1, mhartid
+csrw mhartid, t2
+csrs mhartid, t2
+csrc mhartid, t2
+csrwi mhartid, 1
+csrsi mhartid, 1
+csrci mhartid, 1
+