[RFC][AArch64] Use the new MCSchedPredicate to rewrite a couple of predicates.

[andreadb]

Summary

This is related to "[RFC] MC support for variant scheduling classes" in LLVM-dev.

This is an example of how the new predicates can be used in the AArch64 backend.
This is not meant to be committed.

[javed.absar]

lib/Target/AArch64/AArch64InstrInfoPredicates.td

32

Hi Andrea:
Maybe i am not getting this properly. But how is this approach easier than simply defining a function "IsGPRZero(const MachineInstr*)", as it is done presently.

[gbedwell]

lib/Target/AArch64/AArch64InstrInfoPredicates.td

32

The full RFC (including this example) can be seen at http://lists.llvm.org/pipermail/llvm-dev/2018-May/123181.html

Essentially, the new approach gives the ability to use the same semantic information for both MachineInstr and MCInst which is important for llvm-mca which operates entirely in the MCInst domain.

[andreadb]

lib/Target/AArch64/AArch64InstrInfoPredicates.td

32

Hi Javed,

it may not be easier than defining two functions (one for MachineInstr, another for MCInst). In some cases it may be less obvious to read.
I guess it depends on what use cases you (as a developer working on a scheduling model) want to support.
This new syntax mostly makes sense if you plan to expose knowledge about variant scheduling classes to a tool like llvm-mca.

If you don't, then I totally agree: there is no reason why you should use the new syntax.

My idea was: rather than forcing people to define multiple TII hooks (which are semantically the same), let's give to people a tool to automatically generate them.
It is meant to help the transition from SchedPredicate to MCPredicate in ARM/AArch64 models.

Not sure if this comment helps.
I hope it makes sense.

[javed.absar]

lib/Target/AArch64/AArch64InstrInfoPredicates.td

32

Thanks Andrea.
I see the point now. BTW, thanks a lot for this work.

[andreadb]

lib/Target/AArch64/AArch64InstrInfoPredicates.td

32

No problem.

I have also added a comment on the RFC thread suggesting an alternative approach (with an example).

Cheers,
Andrea

[andreadb]

Abandoning this patch as there was no concrete plan to push this change Upstrea. It was mainly to help the review process for the RFC patches.

lib/Target/AArch64/AArch64InstrInfo.h

public:
   /// Returns true if there is a shiftable register and that the shift value
   /// is non-zero.
   static bool hasShiftedReg(const MachineInstr &MI);
 
   /// Returns true if there is an extendable register and that the extending
   /// value is non-zero.
   static bool hasExtendedReg(const MachineInstr &MI);
 
-  /// Does this instruction set its full destination register to zero?
-  static bool isGPRZero(const MachineInstr &MI);
-
   /// Does this instruction rename a GPR without modifying bits?
   static bool isGPRCopy(const MachineInstr &MI);
 
   /// Does this instruction rename an FPR without modifying bits?
   static bool isFPRCopy(const MachineInstr &MI);
 
   /// Return true if this is load/store scales or extends its register offset.
   /// This refers to scaling a dynamic index as opposed to scaled immediates.

lib/Target/AArch64/AArch64InstrInfo.cpp

if (MI.getOperand(3).isImm()) {
       return (val != 0);
     }
     break;
   }
 
   return false;
 }
 
-// Return true if this instruction simply sets its single destination register
-// to zero. This is equivalent to a register rename of the zero-register.
-bool AArch64InstrInfo::isGPRZero(const MachineInstr &MI) {
-  switch (MI.getOpcode()) {
-  default:
-    break;
-  case AArch64::MOVZWi:
-  case AArch64::MOVZXi: // movz Rd, #0 (LSL #0)
-    if (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) {
-      assert(MI.getDesc().getNumOperands() == 3 &&
-             MI.getOperand(2).getImm() == 0 && "invalid MOVZi operands");
-      return true;
-    }
-    break;
-  case AArch64::ANDWri: // and Rd, Rzr, #imm
-    return MI.getOperand(1).getReg() == AArch64::WZR;
-  case AArch64::ANDXri:
-    return MI.getOperand(1).getReg() == AArch64::XZR;
-  case TargetOpcode::COPY:
-    return MI.getOperand(1).getReg() == AArch64::WZR;
-  }
-  return false;
-}
-
 // Return true if this instruction simply renames a general register without
 // modifying bits.
 bool AArch64InstrInfo::isGPRCopy(const MachineInstr &MI) {
   switch (MI.getOpcode()) {
   default:
     break;
   case TargetOpcode::COPY: {
     // GPR32 copies will by lowered to ORRXrs

lib/Target/AArch64/AArch64InstrInfo.td

def : Pat<(AArch64tcret tcGPR64:$dst, (i32 timm:$FPDiff)),
           (TCRETURNri tcGPR64:$dst, imm:$FPDiff)>;
 def : Pat<(AArch64tcret tglobaladdr:$dst, (i32 timm:$FPDiff)),
           (TCRETURNdi texternalsym:$dst, imm:$FPDiff)>;
 def : Pat<(AArch64tcret texternalsym:$dst, (i32 timm:$FPDiff)),
           (TCRETURNdi texternalsym:$dst, imm:$FPDiff)>;
 
 include "AArch64InstrAtomics.td"
 include "AArch64SVEInstrInfo.td"
+
+include "AArch64InstrInfoPredicates.td"

lib/Target/AArch64/AArch64InstrInfoPredicates.td

+// IsGPRZero.
+
+def CheckMOVZ : CheckAllOf<[
+  CheckOpcode<[MOVZWi, MOVZXi]>,
+  CheckNumOperands<3>,
+  CheckImmOperand<1>,
+  CheckZeroOperand<1>,
+  CheckImmOperand<2>,
+  CheckZeroOperand<2>
+]>;
+
+def CheckANDW : CheckAllOf<[
+  CheckOpcode<[ANDWri]>,
+  CheckRegOperand<1>,
+  CheckRegOperandValue<1, WZR>
+]>;
+
+def CheckANDX : CheckAllOf<[
+  CheckOpcode<[ANDXri]>,
+  CheckRegOperand<1>,
+  CheckRegOperandValue<1, XZR>
+]>;
+
+def CheckCOPY : CheckAllOf<[
+  CheckPseudo<[COPY]>,
+  CheckRegOperand<1>,
+  CheckRegOperandValue<1, WZR>
+]>;
+
+// Return true if this instruction simply sets its single destination register
+// to zero. This is equivalent to a register rename of the zero-register.
+def IsGPRZero : TIIPredicate<"AArch64", "isGPRZero",
+  CheckAnyOf<[CheckMOVZ, CheckANDW, CheckANDX, CheckCOPY]>>;

lib/Target/AArch64/AArch64SchedCyclone.td

 
 // A single nop micro-op (uX).
 def WriteX : SchedWriteRes<[]> { let Latency = 0; }
 
 // Move zero is a register rename (to machine register zero).
 // The move is replaced by a single nop micro-op.
 // MOVZ Rd, #0
 // AND Rd, Rzr, #imm
-def WriteZPred : SchedPredicate<[{TII->isGPRZero(*MI)}]>;
-def WriteImmZ  : SchedWriteVariant<[
-                   SchedVar<WriteZPred, [WriteX]>,
-                   SchedVar<NoSchedPred, [WriteImm]>]>;
+
+def WriteZPred : MCSchedPredicate<IsGPRZero>;
+
+def WriteImmZ : SchedWriteVariant<[
+                  SchedVar<SchedDefault, [WriteImm]>]>;
+
 def : InstRW<[WriteImmZ], (instrs MOVZWi,MOVZXi,ANDWri,ANDXri)>;
 
 // Move GPR is a register rename and single nop micro-op.
 // ORR Xd, XZR, Xm
 // ADD Xd, Xn, #0
 def WriteIMovPred : SchedPredicate<[{TII->isGPRCopy(*MI)}]>;
 def WriteVMovPred : SchedPredicate<[{TII->isFPRCopy(*MI)}]>;
 def WriteMov      : SchedWriteVariant<[

lib/Target/AArch64/AArch64SchedExynosM3.td

def M3UnitNSHT : ProcResGroup<[M3UnitNSHT0,
                                M3UnitNSHT2]>;
 def M3UnitNSHF : ProcResGroup<[M3UnitNSHF0,
                                M3UnitNSHF1,
                                M3UnitNSHF2]>;
 
 //===----------------------------------------------------------------------===//
 // Predicates.
 
-def M3BranchLinkFastPred  : SchedPredicate<[{MI->getOpcode() == AArch64::BLR &&
-                                             MI->getOperand(0).isReg() &&
-                                             MI->getOperand(0).getReg() != AArch64::LR}]>;
+def M3BranchLinkFastPred  : MCSchedPredicate<
+  CheckAllOf<[
+    CheckOpcode<[BLR]>,
+    CheckRegOperand<0>,
+    CheckNot<CheckRegOperandValue<0, LR>>]>
+  >;
+
 def M3ResetFastPred       : SchedPredicate<[{TII->isExynosResetFast(*MI)}]>;
 def M3RotateRightFastPred : SchedPredicate<[{(MI->getOpcode() == AArch64::EXTRWrri ||
                                               MI->getOpcode() == AArch64::EXTRXrri) &&
                                              MI->getOperand(1).isReg() && MI->getOperand(2).isReg() &&
                                              MI->getOperand(1).getReg() == MI->getOperand(2).getReg()}]>;
 def M3ShiftLeftFastPred   : SchedPredicate<[{TII->isExynosShiftLeftFast(*MI)}]>;
 
 //===----------------------------------------------------------------------===//

 def M3WriteAX : SchedWriteVariant<[SchedVar<M3ResetFastPred,     [M3WriteZ0]>,
                                    SchedVar<M3ShiftLeftFastPred, [M3WriteA1]>,
                                    SchedVar<NoSchedPred,         [M3WriteAA]>]>;
 def M3WriteAY : SchedWriteVariant<[SchedVar<M3RotateRightFastPred, [M3WriteA1]>,
                                    SchedVar<NoSchedPred,           [M3WriteAA]>]>;
 
 def M3WriteB1 : SchedWriteRes<[M3UnitB]> { let Latency = 1; }
 def M3WriteBX : SchedWriteVariant<[SchedVar<M3BranchLinkFastPred, [M3WriteAB]>,
-                                   SchedVar<NoSchedPred,          [M3WriteAC]>]>;
+                                   SchedVar<SchedDefault,         [M3WriteAC]>]>;
 
 def M3WriteL4 : SchedWriteRes<[M3UnitL]> { let Latency = 4; }
 def M3WriteL5 : SchedWriteRes<[M3UnitL]> { let Latency = 5; }
 def M3WriteLA : SchedWriteRes<[M3UnitL,
                                M3UnitL]> { let Latency = 5;
                                            let NumMicroOps = 1; }
 def M3WriteLB : SchedWriteRes<[M3UnitA,
                                M3UnitL]> { let Latency = 5;

lib/Target/AArch64/AArch64Schedule.td

 
 // Sequential vector load and shuffle.
 def WriteVLDShuffle     : WriteSequence<[WriteVLD, WriteV]>;
 def WriteVLDPairShuffle : WriteSequence<[WriteVLD, WriteV, WriteV]>;
 
 // Store a shuffled vector.
 def WriteVSTShuffle : WriteSequence<[WriteV, WriteVST]>;
 def WriteVSTPairShuffle : WriteSequence<[WriteV, WriteV, WriteVST]>;
+
+// Predicates that are common to all AArch64 processor models.
+def SchedDefault : MCSchedPredicate<TruePred>;

lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h

 #define GET_REGINFO_ENUM
 #include "AArch64GenRegisterInfo.inc"
 
 // Defines symbolic names for the AArch64 instructions.
 //
 #define GET_INSTRINFO_ENUM
 #include "AArch64GenInstrInfo.inc"
 
+#define GET_GENINSTRINFO_MC_DECL
+#include "AArch64GenInstrInfo.inc"
+
 #define GET_SUBTARGETINFO_ENUM
 #include "AArch64GenSubtargetInfo.inc"
 
 #endif

lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp

 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/TargetRegistry.h"
 
 using namespace llvm;
 
 #define GET_INSTRINFO_MC_DESC
 #include "AArch64GenInstrInfo.inc"
 
+#define GET_GENINSTRINFO_MC_HELPERS
+#include "AArch64GenInstrInfo.inc"
+
 #define GET_SUBTARGETINFO_MC_DESC
 #include "AArch64GenSubtargetInfo.inc"
 
 #define GET_REGINFO_MC_DESC
 #include "AArch64GenRegisterInfo.inc"
 
 static MCInstrInfo *createAArch64MCInstrInfo() {
   MCInstrInfo *X = new MCInstrInfo();