Index: llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td =================================================================== --- llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td +++ llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td @@ -80,22 +80,21 @@ ROUND_W_FM_MM<0, 0x24>, ISA_MICROMIPS; } -let isCodeGenOnly = 1 in { -def ROUND_W_S_MM : MMRel, StdMMR6Rel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, - II_ROUND>, ROUND_W_FM_MM<0, 0xec>, - ISA_MICROMIPS; - -def CEIL_W_MM : MMRel, ABSS_FT<"ceil.w.d", FGR32Opnd, AFGR64Opnd, II_CEIL>, - ROUND_W_FM_MM<1, 0x6c>, ISA_MICROMIPS, FGR_32; -def FLOOR_W_MM : MMRel, ABSS_FT<"floor.w.d", FGR32Opnd, AFGR64Opnd, II_FLOOR>, - ROUND_W_FM_MM<1, 0x2c>, ISA_MICROMIPS, FGR_32; -def ROUND_W_MM : MMRel, StdMMR6Rel, ABSS_FT<"round.w.d", FGR32Opnd, AFGR64Opnd, - II_ROUND>, ROUND_W_FM_MM<1, 0xec>, - ISA_MICROMIPS, FGR_32; -def TRUNC_W_MM : MMRel, ABSS_FT<"trunc.w.d", FGR32Opnd, AFGR64Opnd, II_TRUNC>, - ROUND_W_FM_MM<1, 0xac>, ISA_MICROMIPS, FGR_32; -} let DecoderNamespace = "MicroMips" in { + def ROUND_W_S_MM : MMRel, StdMMR6Rel, ABSS_FT<"round.w.s", FGR32Opnd, + FGR32Opnd, II_ROUND>, + ROUND_W_FM_MM<0, 0xec>, ISA_MICROMIPS; + + def CEIL_W_MM : MMRel, ABSS_FT<"ceil.w.d", FGR32Opnd, AFGR64Opnd, II_CEIL>, + ROUND_W_FM_MM<1, 0x6c>, ISA_MICROMIPS, FGR_32; + def FLOOR_W_MM : MMRel, ABSS_FT<"floor.w.d", FGR32Opnd, AFGR64Opnd, II_FLOOR>, + ROUND_W_FM_MM<1, 0x2c>, ISA_MICROMIPS, FGR_32; + def ROUND_W_MM : MMRel, StdMMR6Rel, ABSS_FT<"round.w.d", FGR32Opnd, + AFGR64Opnd, II_ROUND>, + ROUND_W_FM_MM<1, 0xec>, ISA_MICROMIPS, FGR_32; + def TRUNC_W_MM : MMRel, ABSS_FT<"trunc.w.d", FGR32Opnd, AFGR64Opnd, II_TRUNC>, + ROUND_W_FM_MM<1, 0xac>, ISA_MICROMIPS, FGR_32; + def CVT_L_S_MM : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>, ROUND_W_FM_MM<0, 0x4>, ISA_MICROMIPS, FGR_64; def CVT_L_D64_MM : MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>, @@ -221,16 +220,16 @@ def NMSUB_D32_MM : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D>, MADDS_FM_MM<0x2a>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; } -} -def FLOOR_W_S_MM : MMRel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, - II_FLOOR>, ROUND_W_FM_MM<0, 0x2c>, - ISA_MICROMIPS; -def TRUNC_W_S_MM : MMRel, StdMMR6Rel, ABSS_FT<"trunc.w.s", FGR32Opnd, - FGR32Opnd, II_TRUNC>, - ROUND_W_FM_MM<0, 0xac>, ISA_MICROMIPS; -def CEIL_W_S_MM : MMRel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>, - ROUND_W_FM_MM<0, 0x6c>, ISA_MICROMIPS; + def FLOOR_W_S_MM : MMRel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, + II_FLOOR>, ROUND_W_FM_MM<0, 0x2c>, + ISA_MICROMIPS; + def TRUNC_W_S_MM : MMRel, StdMMR6Rel, ABSS_FT<"trunc.w.s", FGR32Opnd, + FGR32Opnd, II_TRUNC>, + ROUND_W_FM_MM<0, 0xac>, ISA_MICROMIPS; + def CEIL_W_S_MM : MMRel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>, + ROUND_W_FM_MM<0, 0x6c>, ISA_MICROMIPS; +} def FSQRT_S_MM : MMRel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, II_SQRT_S, fsqrt>, ROUND_W_FM_MM<0, 0x28>, ISA_MICROMIPS { string DecoderNamespace = "MicroMips"; Index: llvm/trunk/lib/Target/Mips/MipsInstrFPU.td =================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrFPU.td +++ llvm/trunk/lib/Target/Mips/MipsInstrFPU.td @@ -349,23 +349,22 @@ //===----------------------------------------------------------------------===// // Floating Point Instructions //===----------------------------------------------------------------------===// -def ROUND_W_S : MMRel, StdMMR6Rel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, II_ROUND>, - ABSS_FM<0xc, 16>, ISA_MIPS2; -defm ROUND_W : ROUND_M<"round.w.d", II_ROUND>, ABSS_FM<0xc, 17>, ISA_MIPS2; -def TRUNC_W_S : MMRel, StdMMR6Rel, ABSS_FT<"trunc.w.s", FGR32Opnd, FGR32Opnd, II_TRUNC>, - ABSS_FM<0xd, 16>, ISA_MIPS2; -def CEIL_W_S : MMRel, StdMMR6Rel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>, - ABSS_FM<0xe, 16>, ISA_MIPS2; -def FLOOR_W_S : MMRel, StdMMR6Rel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, II_FLOOR>, - ABSS_FM<0xf, 16>, ISA_MIPS2; -let AdditionalPredicates = [NotInMicroMips] in +let AdditionalPredicates = [NotInMicroMips] in { + def ROUND_W_S : MMRel, StdMMR6Rel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, II_ROUND>, + ABSS_FM<0xc, 16>, ISA_MIPS2; + defm ROUND_W : ROUND_M<"round.w.d", II_ROUND>, ABSS_FM<0xc, 17>, ISA_MIPS2; + def TRUNC_W_S : MMRel, StdMMR6Rel, ABSS_FT<"trunc.w.s", FGR32Opnd, FGR32Opnd, II_TRUNC>, + ABSS_FM<0xd, 16>, ISA_MIPS2; + def CEIL_W_S : MMRel, StdMMR6Rel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>, + ABSS_FM<0xe, 16>, ISA_MIPS2; + def FLOOR_W_S : MMRel, StdMMR6Rel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, II_FLOOR>, + ABSS_FM<0xf, 16>, ISA_MIPS2; def CVT_W_S : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>, ABSS_FM<0x24, 16>, ISA_MIPS1; -defm TRUNC_W : ROUND_M<"trunc.w.d", II_TRUNC>, ABSS_FM<0xd, 17>, ISA_MIPS2; -defm CEIL_W : ROUND_M<"ceil.w.d", II_CEIL>, ABSS_FM<0xe, 17>, ISA_MIPS2; -defm FLOOR_W : ROUND_M<"floor.w.d", II_FLOOR>, ABSS_FM<0xf, 17>, ISA_MIPS2; -let AdditionalPredicates = [NotInMicroMips] in { + defm TRUNC_W : ROUND_M<"trunc.w.d", II_TRUNC>, ABSS_FM<0xd, 17>, ISA_MIPS2; + defm CEIL_W : ROUND_M<"ceil.w.d", II_CEIL>, ABSS_FM<0xe, 17>, ISA_MIPS2; + defm FLOOR_W : ROUND_M<"floor.w.d", II_FLOOR>, ABSS_FM<0xf, 17>, ISA_MIPS2; defm CVT_W : ROUND_M<"cvt.w.d", II_CVT>, ABSS_FM<0x24, 17>, ISA_MIPS1; } Index: llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt =================================================================== --- llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt +++ llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt @@ -242,3 +242,13 @@ 0xc4 0x54 0xa9 0x00 # CHECK: msub.d $f0, $f2, $f4, $f6 0xc4 0x54 0xa2 0x00 # CHECK: nmsub.s $f0, $f2, $f4, $f6 0xc4 0x54 0xaa 0x00 # CHECK: nmsub.d $f0, $f2, $f4, $f6 +0xc8 0x54 0x3b 0x1b # CHECK: ceil.w.s $f6, $f8 +0xc8 0x54 0x3b 0x5b # CHECK: ceil.w.d $f6, $f8 +0xc8 0x54 0x3b 0x09 # CHECK: cvt.w.s $f6, $f8 +0xc8 0x54 0x3b 0x49 # CHECK: cvt.w.d $f6, $f8 +0xc8 0x54 0x3b 0x0b # CHECK: floor.w.s $f6, $f8 +0xc8 0x54 0x3b 0x4b # CHECK: floor.w.d $f6, $f8 +0xc8 0x54 0x3b 0x3b # CHECK: round.w.s $f6, $f8 +0xc8 0x54 0x3b 0x7b # CHECK: round.w.d $f6, $f8 +0xc8 0x54 0x3b 0x2b # CHECK: trunc.w.s $f6, $f8 +0xc8 0x54 0x3b 0x6b # CHECK: trunc.w.d $f6, $f8 Index: llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt =================================================================== --- llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt +++ llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt @@ -244,3 +244,13 @@ 0x54 0xc4 0x00 0xa9 # CHECK: msub.d $f0, $f2, $f4, $f6 0x54 0xc4 0x00 0xa2 # CHECK: nmsub.s $f0, $f2, $f4, $f6 0x54 0xc4 0x00 0xaa # CHECK: nmsub.d $f0, $f2, $f4, $f6 +0x54 0xc8 0x1b 0x3b # CHECK: ceil.w.s $f6, $f8 +0x54 0xc8 0x5b 0x3b # CHECK: ceil.w.d $f6, $f8 +0x54 0xc8 0x09 0x3b # CHECK: cvt.w.s $f6, $f8 +0x54 0xc8 0x49 0x3b # CHECK: cvt.w.d $f6, $f8 +0x54 0xc8 0x0b 0x3b # CHECK: floor.w.s $f6, $f8 +0x54 0xc8 0x4b 0x3b # CHECK: floor.w.d $f6, $f8 +0x54 0xc8 0x3b 0x3b # CHECK: round.w.s $f6, $f8 +0x54 0xc8 0x7b 0x3b # CHECK: round.w.d $f6, $f8 +0x54 0xc8 0x2b 0x3b # CHECK: trunc.w.s $f6, $f8 +0x54 0xc8 0x6b 0x3b # CHECK: trunc.w.d $f6, $f8 Index: llvm/trunk/test/MC/Mips/micromips-fpu-instructions.s =================================================================== --- llvm/trunk/test/MC/Mips/micromips-fpu-instructions.s +++ llvm/trunk/test/MC/Mips/micromips-fpu-instructions.s @@ -26,17 +26,25 @@ # CHECK-EL: bc1t 1332 # encoding: [0xa0,0x43,0x9a,0x02] # CHECK-EL: nop # encoding: [0x00,0x00,0x00,0x00] # CHECK-EL: ceil.w.s $f6, $f8 # encoding: [0xc8,0x54,0x3b,0x1b] +# CHECK-EL-NEXT: #