Index: llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.td
===================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.td
+++ llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.td
@@ -792,7 +792,7 @@
 
 class PPRAsmOperand <string name, string RegClass, int Width>: AsmOperandClass {
   let Name = "SVE" # name # "Reg";
-  let PredicateMethod = "isSVEVectorRegOfWidth<"
+  let PredicateMethod = "isSVEPredicateVectorRegOfWidth<"
                             # Width # ", " # "AArch64::" # RegClass # "RegClassID>";
   let DiagnosticType = "InvalidSVE" # name # "Reg";
   let RenderMethod = "addRegOperands";
@@ -837,9 +837,10 @@
 
 class ZPRAsmOperand <string name, int Width>: AsmOperandClass {
   let Name = "SVE" # name # "Reg";
-  let PredicateMethod = "isSVEVectorRegOfWidth<"
+  let PredicateMethod = "isSVEDataVectorRegOfWidth<"
                             # Width # ", AArch64::ZPRRegClassID>";
   let RenderMethod = "addRegOperands";
+  let DiagnosticType = "InvalidZPR" # Width;
   let ParserMethod = "tryParseSVEDataVector<false, "
                                # !if(!eq(Width, 0), "false", "true") # ">";
 }
@@ -958,7 +959,7 @@
   let Name = "ZPRExtend" # ShiftExtend # RegWidth # Scale
                          # !if(ScaleAlwaysSame, "Only", "");
 
-  let PredicateMethod = "isSVEVectorRegWithShiftExtend<"
+  let PredicateMethod = "isSVEDataVectorRegWithShiftExtend<"
                           # RegWidth # ", AArch64::ZPRRegClassID, "
                           # "AArch64_AM::" # ShiftExtend # ", "
                           # Scale # ", "
Index: llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
===================================================================
--- llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -872,21 +872,37 @@
   }
 
   template <int ElementWidth, unsigned Class>
-  bool isSVEVectorRegOfWidth() const {
-    return isSVEVectorReg<Class>() &&
-           (ElementWidth == 0 || Reg.ElementWidth == ElementWidth);
+  DiagnosticPredicate isSVEPredicateVectorRegOfWidth() const {
+    if (Kind != k_Register || Reg.Kind != RegKind::SVEPredicateVector)
+      return DiagnosticPredicateTy::NoMatch;
+
+    if (isSVEVectorReg<Class>() &&
+           (ElementWidth == 0 || Reg.ElementWidth == ElementWidth))
+      return DiagnosticPredicateTy::Match;
+
+    return DiagnosticPredicateTy::NearMatch;
+  }
+
+  template <int ElementWidth, unsigned Class>
+  DiagnosticPredicate isSVEDataVectorRegOfWidth() const {
+    if (Kind != k_Register || Reg.Kind != RegKind::SVEDataVector)
+      return DiagnosticPredicateTy::NoMatch;
+
+    if (isSVEVectorReg<Class>() &&
+           (ElementWidth == 0 || Reg.ElementWidth == ElementWidth))
+      return DiagnosticPredicateTy::Match;
+
+    return DiagnosticPredicateTy::NearMatch;
   }
 
   template <int ElementWidth, unsigned Class,
             AArch64_AM::ShiftExtendType ShiftExtendTy, int ShiftWidth,
             bool ShiftWidthAlwaysSame>
-  DiagnosticPredicate isSVEVectorRegWithShiftExtend() const {
-    if (Kind != k_Register || Reg.Kind != RegKind::SVEDataVector)
+  DiagnosticPredicate isSVEDataVectorRegWithShiftExtend() const {
+    auto VectorMatch = isSVEDataVectorRegOfWidth<ElementWidth, Class>();
+    if (!VectorMatch.isMatch())
       return DiagnosticPredicateTy::NoMatch;
 
-    if (!isSVEVectorRegOfWidth<ElementWidth, Class>())
-      return DiagnosticPredicateTy::NearMatch;
-
     // Give a more specific diagnostic when the user has explicitly typed in
     // a shift-amount that does not match what is expected, but for which
     // there is also an unscaled addressing mode (e.g. sxtw/uxtw).
@@ -3817,6 +3833,14 @@
     return Error(Loc, "invalid shift/extend specified, expected 'z[0..31].d, lsl #2'");
   case Match_InvalidZPR64LSL64:
     return Error(Loc, "invalid shift/extend specified, expected 'z[0..31].d, lsl #3'");
+  case Match_InvalidZPR0:
+    return Error(Loc, "expected register without element width sufix");
+  case Match_InvalidZPR8:
+  case Match_InvalidZPR16:
+  case Match_InvalidZPR32:
+  case Match_InvalidZPR64:
+  case Match_InvalidZPR128:
+    return Error(Loc, "invalid element width");
   case Match_InvalidSVEPattern:
     return Error(Loc, "invalid predicate pattern");
   case Match_InvalidSVEPredicateAnyReg:
@@ -4299,6 +4323,12 @@
   case Match_InvalidZPR64LSL16:
   case Match_InvalidZPR64LSL32:
   case Match_InvalidZPR64LSL64:
+  case Match_InvalidZPR0:
+  case Match_InvalidZPR8:
+  case Match_InvalidZPR16:
+  case Match_InvalidZPR32:
+  case Match_InvalidZPR64:
+  case Match_InvalidZPR128:
   case Match_InvalidSVEPredicateAnyReg:
   case Match_InvalidSVEPattern:
   case Match_InvalidSVEPredicateBReg:
Index: llvm/trunk/test/MC/AArch64/SVE/add-diagnostics.s
===================================================================
--- llvm/trunk/test/MC/AArch64/SVE/add-diagnostics.s
+++ llvm/trunk/test/MC/AArch64/SVE/add-diagnostics.s
@@ -14,7 +14,7 @@
 
 // Element size specifiers should match.
 add z27.h, z11.h, z27.b
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: add z27.h, z11.h, z27.b
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
Index: llvm/trunk/test/MC/AArch64/SVE/ld1b-diagnostics.s
===================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld1b-diagnostics.s
+++ llvm/trunk/test/MC/AArch64/SVE/ld1b-diagnostics.s
@@ -115,17 +115,17 @@
 // Invalid scalar + vector addressing modes
 
 ld1b z0.d, p0/z, [x0, z0.b]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ld1b z0.d, p0/z, [x0, z0.b]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1b z0.d, p0/z, [x0, z0.h]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ld1b z0.d, p0/z, [x0, z0.h]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1b z0.d, p0/z, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ld1b z0.d, p0/z, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
Index: llvm/trunk/test/MC/AArch64/SVE/ld1d-diagnostics.s
===================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld1d-diagnostics.s
+++ llvm/trunk/test/MC/AArch64/SVE/ld1d-diagnostics.s
@@ -75,7 +75,7 @@
 // Invalid scalar + vector addressing modes
 
 ld1d z0.d, p0/z, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ld1d z0.d, p0/z, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
@@ -99,12 +99,12 @@
 // Invalid vector + immediate addressing modes
 
 ld1d z0.s, p0/z, [z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1d z0.s, p0/z, [z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1d z0.s, p0/z, [z0.s, #8]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1d z0.s, p0/z, [z0.s, #8]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
Index: llvm/trunk/test/MC/AArch64/SVE/ld1h-diagnostics.s
===================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld1h-diagnostics.s
+++ llvm/trunk/test/MC/AArch64/SVE/ld1h-diagnostics.s
@@ -105,12 +105,12 @@
 // Invalid scalar + vector addressing modes
 
 ld1h z0.d, p0/z, [x0, z0.h]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ld1h z0.d, p0/z, [x0, z0.h]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1h z0.d, p0/z, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ld1h z0.d, p0/z, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
Index: llvm/trunk/test/MC/AArch64/SVE/ld1rd-diagnostics.s
===================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld1rd-diagnostics.s
+++ llvm/trunk/test/MC/AArch64/SVE/ld1rd-diagnostics.s
@@ -33,17 +33,17 @@
 // Invalid result vector element size
 
 ld1rd z0.b, p1/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1rd z0.b, p1/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1rd z0.h, p1/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1rd z0.h, p1/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1rd z0.s, p1/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1rd z0.s, p1/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
Index: llvm/trunk/test/MC/AArch64/SVE/ld1rh-diagnostics.s
===================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld1rh-diagnostics.s
+++ llvm/trunk/test/MC/AArch64/SVE/ld1rh-diagnostics.s
@@ -33,7 +33,7 @@
 // Invalid result vector element size
 
 ld1rh z0.b, p1/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1rh z0.b, p1/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
Index: llvm/trunk/test/MC/AArch64/SVE/ld1rqb-diagnostics.s
===================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld1rqb-diagnostics.s
+++ llvm/trunk/test/MC/AArch64/SVE/ld1rqb-diagnostics.s
@@ -42,17 +42,17 @@
 // Invalid destination register width.
 
 ld1rqb z0.h, p0/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1rqb z0.h, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1rqb z0.s, p0/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1rqb z0.s, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1rqb z0.d, p0/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1rqb z0.d, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
Index: llvm/trunk/test/MC/AArch64/SVE/ld1rqd-diagnostics.s
===================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld1rqd-diagnostics.s
+++ llvm/trunk/test/MC/AArch64/SVE/ld1rqd-diagnostics.s
@@ -42,17 +42,17 @@
 // Invalid destination register width.
 
 ld1rqd z0.b, p0/z, [x0, x1, lsl #3]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1rqd z0.b, p0/z, [x0, x1, lsl #3]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1rqd z0.h, p0/z, [x0, x1, lsl #3]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1rqd z0.h, p0/z, [x0, x1, lsl #3]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1rqd z0.s, p0/z, [x0, x1, lsl #3]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1rqd z0.s, p0/z, [x0, x1, lsl #3]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
Index: llvm/trunk/test/MC/AArch64/SVE/ld1rqh-diagnostics.s
===================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld1rqh-diagnostics.s
+++ llvm/trunk/test/MC/AArch64/SVE/ld1rqh-diagnostics.s
@@ -42,17 +42,17 @@
 // Invalid destination register width.
 
 ld1rqh z0.b, p0/z, [x0, x1, lsl #1]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1rqh z0.b, p0/z, [x0, x1, lsl #1]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1rqh z0.s, p0/z, [x0, x1, lsl #1]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1rqh z0.s, p0/z, [x0, x1, lsl #1]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1rqh z0.d, p0/z, [x0, x1, lsl #1]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1rqh z0.d, p0/z, [x0, x1, lsl #1]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
Index: llvm/trunk/test/MC/AArch64/SVE/ld1rqw-diagnostics.s
===================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld1rqw-diagnostics.s
+++ llvm/trunk/test/MC/AArch64/SVE/ld1rqw-diagnostics.s
@@ -42,17 +42,17 @@
 // Invalid destination register width.
 
 ld1rqw z0.b, p0/z, [x0, x1, lsl #2]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1rqw z0.b, p0/z, [x0, x1, lsl #2]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1rqw z0.h, p0/z, [x0, x1, lsl #2]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1rqw z0.h, p0/z, [x0, x1, lsl #2]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1rqw z0.d, p0/z, [x0, x1, lsl #2]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1rqw z0.d, p0/z, [x0, x1, lsl #2]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
Index: llvm/trunk/test/MC/AArch64/SVE/ld1rsb-diagnostics.s
===================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld1rsb-diagnostics.s
+++ llvm/trunk/test/MC/AArch64/SVE/ld1rsb-diagnostics.s
@@ -18,7 +18,7 @@
 // Invalid result vector element size
 
 ld1rsb z0.b, p1/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1rsb z0.b, p1/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
Index: llvm/trunk/test/MC/AArch64/SVE/ld1rsh-diagnostics.s
===================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld1rsh-diagnostics.s
+++ llvm/trunk/test/MC/AArch64/SVE/ld1rsh-diagnostics.s
@@ -23,12 +23,12 @@
 // Invalid result vector element size
 
 ld1rsh z0.b, p1/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1rsh z0.b, p1/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1rsh z0.h, p1/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1rsh z0.h, p1/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
Index: llvm/trunk/test/MC/AArch64/SVE/ld1rsw-diagnostics.s
===================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld1rsw-diagnostics.s
+++ llvm/trunk/test/MC/AArch64/SVE/ld1rsw-diagnostics.s
@@ -23,17 +23,17 @@
 // Invalid result vector element size
 
 ld1rsw z0.b, p1/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1rsw z0.b, p1/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1rsw z0.h, p1/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1rsw z0.h, p1/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1rsw z0.s, p1/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1rsw z0.s, p1/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
Index: llvm/trunk/test/MC/AArch64/SVE/ld1rw-diagnostics.s
===================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld1rw-diagnostics.s
+++ llvm/trunk/test/MC/AArch64/SVE/ld1rw-diagnostics.s
@@ -33,12 +33,12 @@
 // Invalid result vector element size
 
 ld1rw z0.b, p1/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1rw z0.b, p1/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1rw z0.h, p1/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1rw z0.h, p1/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
Index: llvm/trunk/test/MC/AArch64/SVE/ld1sb-diagnostics.s
===================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld1sb-diagnostics.s
+++ llvm/trunk/test/MC/AArch64/SVE/ld1sb-diagnostics.s
@@ -4,12 +4,12 @@
 // Invalid operand (.b)
 
 ld1sb z23.b, p0/z, [x13, #1, MUL VL]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1sb z23.b, p0/z, [x13, #1, MUL VL]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sb z29.b, p0/z, [x3, #1, MUL VL]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1sb z29.b, p0/z, [x3, #1, MUL VL]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
@@ -113,17 +113,17 @@
 // Invalid scalar + vector addressing modes
 
 ld1sb z0.d, p0/z, [x0, z0.b]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ld1sb z0.d, p0/z, [x0, z0.b]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sb z0.d, p0/z, [x0, z0.h]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ld1sb z0.d, p0/z, [x0, z0.h]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sb z0.d, p0/z, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ld1sb z0.d, p0/z, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
Index: llvm/trunk/test/MC/AArch64/SVE/ld1sh-diagnostics.s
===================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld1sh-diagnostics.s
+++ llvm/trunk/test/MC/AArch64/SVE/ld1sh-diagnostics.s
@@ -4,12 +4,12 @@
 // Invalid operand (.h)
 
 ld1sh z23.h, p0/z, [x13, #1, MUL VL]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1sh z23.h, p0/z, [x13, #1, MUL VL]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sh z29.h, p0/z, [x3, #1, MUL VL]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1sh z29.h, p0/z, [x3, #1, MUL VL]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
@@ -104,12 +104,12 @@
 // Invalid scalar + vector addressing modes
 
 ld1sh z0.d, p0/z, [x0, z0.h]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ld1sh z0.d, p0/z, [x0, z0.h]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sh z0.d, p0/z, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ld1sh z0.d, p0/z, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
Index: llvm/trunk/test/MC/AArch64/SVE/ld1sw-diagnostics.s
===================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld1sw-diagnostics.s
+++ llvm/trunk/test/MC/AArch64/SVE/ld1sw-diagnostics.s
@@ -4,12 +4,12 @@
 // Invalid operand (.s)
 
 ld1sw z23.s, p0/z, [x13, #1, MUL VL]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1sw z23.s, p0/z, [x13, #1, MUL VL]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sw z29.s, p0/z, [x3, #1, MUL VL]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1sw z29.s, p0/z, [x3, #1, MUL VL]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
@@ -89,17 +89,12 @@
 // Invalid scalar + vector addressing modes
 
 ld1sw z0.d, p0/z, [x0, z0.h]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, z0.h]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sw z0.d, p0/z, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
-// CHECK-NEXT: ld1sw z0.d, p0/z, [x0, z0.s]
-// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-
-ld1sw z0.d, p0/z, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
@@ -133,12 +128,12 @@
 // Invalid vector + immediate addressing modes
 
 ld1sw z0.s, p0/z, [z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1sw z0.s, p0/z, [z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sw z0.s, p0/z, [z0.s, #4]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ld1sw z0.s, p0/z, [z0.s, #4]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
Index: llvm/trunk/test/MC/AArch64/SVE/ld1w-diagnostics.s
===================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ld1w-diagnostics.s
+++ llvm/trunk/test/MC/AArch64/SVE/ld1w-diagnostics.s
@@ -90,12 +90,12 @@
 // Invalid scalar + vector addressing modes
 
 ld1w z0.d, p0/z, [x0, z0.h]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ld1w z0.d, p0/z, [x0, z0.h]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1w z0.d, p0/z, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ld1w z0.d, p0/z, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
Index: llvm/trunk/test/MC/AArch64/SVE/ldff1b-diagnostics.s
===================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ldff1b-diagnostics.s
+++ llvm/trunk/test/MC/AArch64/SVE/ldff1b-diagnostics.s
@@ -50,17 +50,17 @@
 // Invalid scalar + vector addressing modes
 
 ldff1b z0.d, p0/z, [x0, z0.b]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ldff1b z0.d, p0/z, [x0, z0.b]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1b z0.d, p0/z, [x0, z0.h]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ldff1b z0.d, p0/z, [x0, z0.h]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1b z0.d, p0/z, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ldff1b z0.d, p0/z, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
Index: llvm/trunk/test/MC/AArch64/SVE/ldff1d-diagnostics.s
===================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ldff1d-diagnostics.s
+++ llvm/trunk/test/MC/AArch64/SVE/ldff1d-diagnostics.s
@@ -4,17 +4,17 @@
 // Invalid operand (.b, .h, .s)
 
 ldff1d z4.b, p7/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ldff1d z4.b, p7/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1d z4.h, p7/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ldff1d z4.h, p7/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1d z4.s, p7/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ldff1d z4.s, p7/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
@@ -54,7 +54,7 @@
 // Invalid scalar + vector addressing modes
 
 ldff1d z0.d, p0/z, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ldff1d z0.d, p0/z, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
@@ -78,12 +78,12 @@
 // Invalid vector + immediate addressing modes
 
 ldff1d z0.s, p0/z, [z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ldff1d z0.s, p0/z, [z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1d z0.s, p0/z, [z0.s, #8]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ldff1d z0.s, p0/z, [z0.s, #8]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
Index: llvm/trunk/test/MC/AArch64/SVE/ldff1h-diagnostics.s
===================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ldff1h-diagnostics.s
+++ llvm/trunk/test/MC/AArch64/SVE/ldff1h-diagnostics.s
@@ -4,7 +4,7 @@
 // Invalid operand (.b)
 
 ldff1h z9.b, p7/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ldff1h z9.b, p7/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
@@ -54,12 +54,12 @@
 // Invalid scalar + vector addressing modes
 
 ldff1h z0.d, p0/z, [x0, z0.h]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ldff1h z0.d, p0/z, [x0, z0.h]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1h z0.d, p0/z, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ldff1h z0.d, p0/z, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
Index: llvm/trunk/test/MC/AArch64/SVE/ldff1sb-diagnostics.s
===================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ldff1sb-diagnostics.s
+++ llvm/trunk/test/MC/AArch64/SVE/ldff1sb-diagnostics.s
@@ -4,7 +4,7 @@
 // Invalid operand (.b)
 
 ldff1sb z27.b, p7/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ldff1sb z27.b, p7/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
@@ -53,17 +53,17 @@
 // Invalid scalar + vector addressing modes
 
 ldff1sb z0.d, p0/z, [x0, z0.b]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ldff1sb z0.d, p0/z, [x0, z0.b]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1sb z0.d, p0/z, [x0, z0.h]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ldff1sb z0.d, p0/z, [x0, z0.h]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1sb z0.d, p0/z, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ldff1sb z0.d, p0/z, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
Index: llvm/trunk/test/MC/AArch64/SVE/ldff1sh-diagnostics.s
===================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ldff1sh-diagnostics.s
+++ llvm/trunk/test/MC/AArch64/SVE/ldff1sh-diagnostics.s
@@ -4,7 +4,7 @@
 // Invalid operand (.h)
 
 ldff1sh z9.h, p7/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ldff1sh z9.h, p7/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
@@ -48,12 +48,12 @@
 // Invalid scalar + vector addressing modes
 
 ldff1sh z0.d, p0/z, [x0, z0.h]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ldff1sh z0.d, p0/z, [x0, z0.h]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1sh z0.d, p0/z, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ldff1sh z0.d, p0/z, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
Index: llvm/trunk/test/MC/AArch64/SVE/ldff1sw-diagnostics.s
===================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ldff1sw-diagnostics.s
+++ llvm/trunk/test/MC/AArch64/SVE/ldff1sw-diagnostics.s
@@ -4,7 +4,7 @@
 // Invalid operand (.s)
 
 ldff1sw z12.s, p7/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ldff1sw z12.s, p7/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
@@ -44,17 +44,12 @@
 // Invalid scalar + vector addressing modes
 
 ldff1sw z0.d, p0/z, [x0, z0.h]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ldff1sw z0.d, p0/z, [x0, z0.h]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1sw z0.d, p0/z, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
-// CHECK-NEXT: ldff1sw z0.d, p0/z, [x0, z0.s]
-// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-
-ldff1sw z0.d, p0/z, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ldff1sw z0.d, p0/z, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
@@ -88,12 +83,12 @@
 // Invalid vector + immediate addressing modes
 
 ldff1sw z0.s, p0/z, [z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ldff1sw z0.s, p0/z, [z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1sw z0.s, p0/z, [z0.s, #4]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ldff1sw z0.s, p0/z, [z0.s, #4]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
Index: llvm/trunk/test/MC/AArch64/SVE/ldff1w-diagnostics.s
===================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ldff1w-diagnostics.s
+++ llvm/trunk/test/MC/AArch64/SVE/ldff1w-diagnostics.s
@@ -4,12 +4,12 @@
 // Invalid operand (.b, .h)
 
 ldff1w z12.b, p7/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ldff1w z12.b, p7/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1w z4.h, p7/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ldff1w z4.h, p7/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
@@ -54,12 +54,12 @@
 // Invalid scalar + vector addressing modes
 
 ldff1w z0.d, p0/z, [x0, z0.h]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ldff1w z0.d, p0/z, [x0, z0.h]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1w z0.d, p0/z, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ldff1w z0.d, p0/z, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
Index: llvm/trunk/test/MC/AArch64/SVE/ldnf1sb-diagnostics.s
===================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ldnf1sb-diagnostics.s
+++ llvm/trunk/test/MC/AArch64/SVE/ldnf1sb-diagnostics.s
@@ -4,12 +4,12 @@
 // Invalid operand (.b)
 
 ldnf1sb z23.b, p0/z, [x13, #1, MUL VL]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ldnf1sb z23.b, p0/z, [x13, #1, MUL VL]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldnf1sb z29.b, p0/z, [x3, #1, MUL VL]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ldnf1sb z29.b, p0/z, [x3, #1, MUL VL]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
Index: llvm/trunk/test/MC/AArch64/SVE/ldnf1sh-diagnostics.s
===================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ldnf1sh-diagnostics.s
+++ llvm/trunk/test/MC/AArch64/SVE/ldnf1sh-diagnostics.s
@@ -4,12 +4,12 @@
 // Invalid operand (.h)
 
 ldnf1sh z23.h, p0/z, [x13, #1, MUL VL]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ldnf1sh z23.h, p0/z, [x13, #1, MUL VL]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldnf1sh z29.h, p0/z, [x3, #1, MUL VL]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ldnf1sh z29.h, p0/z, [x3, #1, MUL VL]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
Index: llvm/trunk/test/MC/AArch64/SVE/ldnf1sw-diagnostics.s
===================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ldnf1sw-diagnostics.s
+++ llvm/trunk/test/MC/AArch64/SVE/ldnf1sw-diagnostics.s
@@ -4,12 +4,12 @@
 // Invalid operand (.s)
 
 ldnf1sw z23.s, p0/z, [x13, #1, MUL VL]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ldnf1sw z23.s, p0/z, [x13, #1, MUL VL]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldnf1sw z29.s, p0/z, [x3, #1, MUL VL]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ldnf1sw z29.s, p0/z, [x3, #1, MUL VL]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
Index: llvm/trunk/test/MC/AArch64/SVE/ldnt1b-diagnostics.s
===================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ldnt1b-diagnostics.s
+++ llvm/trunk/test/MC/AArch64/SVE/ldnt1b-diagnostics.s
@@ -18,17 +18,17 @@
 // Invalid result type.
 
 ldnt1b z0.h, p0/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ldnt1b z0.h, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldnt1b z0.s, p0/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ldnt1b z0.s, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldnt1b z0.d, p0/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ldnt1b z0.d, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
Index: llvm/trunk/test/MC/AArch64/SVE/ldnt1d-diagnostics.s
===================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ldnt1d-diagnostics.s
+++ llvm/trunk/test/MC/AArch64/SVE/ldnt1d-diagnostics.s
@@ -18,17 +18,17 @@
 // Invalid result type.
 
 ldnt1d z0.b, p0/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ldnt1d z0.b, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldnt1d z0.h, p0/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ldnt1d z0.h, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldnt1d z0.s, p0/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ldnt1d z0.s, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
Index: llvm/trunk/test/MC/AArch64/SVE/ldnt1h-diagnostics.s
===================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ldnt1h-diagnostics.s
+++ llvm/trunk/test/MC/AArch64/SVE/ldnt1h-diagnostics.s
@@ -18,17 +18,17 @@
 // Invalid result type.
 
 ldnt1h z0.b, p0/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ldnt1h z0.b, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldnt1h z0.s, p0/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ldnt1h z0.s, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldnt1h z0.d, p0/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ldnt1h z0.d, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
Index: llvm/trunk/test/MC/AArch64/SVE/ldnt1w-diagnostics.s
===================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ldnt1w-diagnostics.s
+++ llvm/trunk/test/MC/AArch64/SVE/ldnt1w-diagnostics.s
@@ -18,17 +18,17 @@
 // Invalid result type.
 
 ldnt1w z0.b, p0/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ldnt1w z0.b, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldnt1w z0.h, p0/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ldnt1w z0.h, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldnt1w z0.d, p0/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: ldnt1w z0.d, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
Index: llvm/trunk/test/MC/AArch64/SVE/prfb-diagnostics.s
===================================================================
--- llvm/trunk/test/MC/AArch64/SVE/prfb-diagnostics.s
+++ llvm/trunk/test/MC/AArch64/SVE/prfb-diagnostics.s
@@ -58,32 +58,32 @@
 // Invalid scalar + vector addressing modes
 
 prfb #0, p0, [x0, z0.b]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: prfb #0, p0, [x0, z0.b]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 prfb #0, p0, [x0, z0.h]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: prfb #0, p0, [x0, z0.h]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 prfb #0, p0, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
 // CHECK-NEXT: prfb #0, p0, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 prfb #0, p0, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
 // CHECK-NEXT: prfb #0, p0, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 prfb #0, p0, [x0, z0.s, uxtw #1]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
 // CHECK-NEXT: prfb #0, p0, [x0, z0.s, uxtw #1]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 prfb #0, p0, [x0, z0.s, lsl #0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
 // CHECK-NEXT: prfb #0, p0, [x0, z0.s, lsl #0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
Index: llvm/trunk/test/MC/AArch64/SVE/prfd-diagnostics.s
===================================================================
--- llvm/trunk/test/MC/AArch64/SVE/prfd-diagnostics.s
+++ llvm/trunk/test/MC/AArch64/SVE/prfd-diagnostics.s
@@ -58,7 +58,7 @@
 // Invalid scalar + vector addressing modes
 
 prfd #0, p0, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #3'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #3'
 // CHECK-NEXT: prfd #0, p0, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
Index: llvm/trunk/test/MC/AArch64/SVE/prfh-diagnostics.s
===================================================================
--- llvm/trunk/test/MC/AArch64/SVE/prfh-diagnostics.s
+++ llvm/trunk/test/MC/AArch64/SVE/prfh-diagnostics.s
@@ -58,27 +58,27 @@
 // Invalid scalar + vector addressing modes
 
 prfh #0, p0, [x0, z0.h]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: prfh #0, p0, [x0, z0.h]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 prfh #0, p0, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #1'
 // CHECK-NEXT: prfh #0, p0, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 prfh #0, p0, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #1'
 // CHECK-NEXT: prfh #0, p0, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 prfh #0, p0, [x0, z0.s, uxtw #2]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #1'
 // CHECK-NEXT: prfh #0, p0, [x0, z0.s, uxtw #2]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 prfh #0, p0, [x0, z0.s, lsl #1]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #1'
 // CHECK-NEXT: prfh #0, p0, [x0, z0.s, lsl #1]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
Index: llvm/trunk/test/MC/AArch64/SVE/prfw-diagnostics.s
===================================================================
--- llvm/trunk/test/MC/AArch64/SVE/prfw-diagnostics.s
+++ llvm/trunk/test/MC/AArch64/SVE/prfw-diagnostics.s
@@ -58,27 +58,27 @@
 // Invalid scalar + vector addressing modes
 
 prfw #0, p0, [x0, z0.h]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: prfw #0, p0, [x0, z0.h]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 prfw #0, p0, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #2'
 // CHECK-NEXT: prfw #0, p0, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 prfw #0, p0, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #2'
 // CHECK-NEXT: prfw #0, p0, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 prfw #0, p0, [x0, z0.s, uxtw #3]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #2'
 // CHECK-NEXT: prfw #0, p0, [x0, z0.s, uxtw #3]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 prfw #0, p0, [x0, z0.s, lsl #2]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #2'
 // CHECK-NEXT: prfw #0, p0, [x0, z0.s, lsl #2]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
Index: llvm/trunk/test/MC/AArch64/SVE/st1b-diagnostics.s
===================================================================
--- llvm/trunk/test/MC/AArch64/SVE/st1b-diagnostics.s
+++ llvm/trunk/test/MC/AArch64/SVE/st1b-diagnostics.s
@@ -113,17 +113,17 @@
 // Invalid scalar + vector addressing modes
 
 st1b z0.d, p0, [x0, z0.b]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: st1b z0.d, p0, [x0, z0.b]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 st1b z0.d, p0, [x0, z0.h]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: st1b z0.d, p0, [x0, z0.h]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 st1b z0.d, p0, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: st1b z0.d, p0, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
Index: llvm/trunk/test/MC/AArch64/SVE/st1d-diagnostics.s
===================================================================
--- llvm/trunk/test/MC/AArch64/SVE/st1d-diagnostics.s
+++ llvm/trunk/test/MC/AArch64/SVE/st1d-diagnostics.s
@@ -74,7 +74,7 @@
 // Invalid scalar + vector addressing modes
 
 st1d z0.d, p0, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: st1d z0.d, p0, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
@@ -98,12 +98,12 @@
 // Invalid vector + immediate addressing modes
 
 st1d z0.s, p0, [z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: st1d z0.s, p0, [z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 st1d z0.s, p0, [z0.s, #8]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: st1d z0.s, p0, [z0.s, #8]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
Index: llvm/trunk/test/MC/AArch64/SVE/st1h-diagnostics.s
===================================================================
--- llvm/trunk/test/MC/AArch64/SVE/st1h-diagnostics.s
+++ llvm/trunk/test/MC/AArch64/SVE/st1h-diagnostics.s
@@ -103,12 +103,12 @@
 // Invalid scalar + vector addressing modes
 
 st1h z0.d, p0, [x0, z0.h]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: st1h z0.d, p0, [x0, z0.h]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 st1h z0.d, p0, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: st1h z0.d, p0, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
Index: llvm/trunk/test/MC/AArch64/SVE/st1w-diagnostics.s
===================================================================
--- llvm/trunk/test/MC/AArch64/SVE/st1w-diagnostics.s
+++ llvm/trunk/test/MC/AArch64/SVE/st1w-diagnostics.s
@@ -91,12 +91,12 @@
 // Invalid scalar + vector addressing modes
 
 st1w z0.d, p0, [x0, z0.h]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: st1w z0.d, p0, [x0, z0.h]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 st1w z0.d, p0, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: st1w z0.d, p0, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
Index: llvm/trunk/test/MC/AArch64/SVE/stnt1b-diagnostics.s
===================================================================
--- llvm/trunk/test/MC/AArch64/SVE/stnt1b-diagnostics.s
+++ llvm/trunk/test/MC/AArch64/SVE/stnt1b-diagnostics.s
@@ -18,17 +18,17 @@
 // Invalid source type.
 
 stnt1b z0.h, p0, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: stnt1b z0.h, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 stnt1b z0.s, p0, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: stnt1b z0.s, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 stnt1b z0.d, p0, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: stnt1b z0.d, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
@@ -42,7 +42,7 @@
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 stnt1b z0.h, p0/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: stnt1b z0.h, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
Index: llvm/trunk/test/MC/AArch64/SVE/stnt1d-diagnostics.s
===================================================================
--- llvm/trunk/test/MC/AArch64/SVE/stnt1d-diagnostics.s
+++ llvm/trunk/test/MC/AArch64/SVE/stnt1d-diagnostics.s
@@ -18,17 +18,17 @@
 // Invalid source type.
 
 stnt1d z0.b, p0, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: stnt1d z0.b, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 stnt1d z0.h, p0, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: stnt1d z0.h, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 stnt1d z0.s, p0, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: stnt1d z0.s, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
Index: llvm/trunk/test/MC/AArch64/SVE/stnt1h-diagnostics.s
===================================================================
--- llvm/trunk/test/MC/AArch64/SVE/stnt1h-diagnostics.s
+++ llvm/trunk/test/MC/AArch64/SVE/stnt1h-diagnostics.s
@@ -18,17 +18,17 @@
 // Invalid source type.
 
 stnt1h z0.b, p0, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: stnt1h z0.b, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 stnt1h z0.s, p0, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: stnt1h z0.s, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 stnt1h z0.d, p0, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: stnt1h z0.d, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
Index: llvm/trunk/test/MC/AArch64/SVE/stnt1w-diagnostics.s
===================================================================
--- llvm/trunk/test/MC/AArch64/SVE/stnt1w-diagnostics.s
+++ llvm/trunk/test/MC/AArch64/SVE/stnt1w-diagnostics.s
@@ -18,17 +18,17 @@
 // Invalid source type.
 
 stnt1w z0.b, p0, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: stnt1w z0.b, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 stnt1w z0.h, p0, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: stnt1w z0.h, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 stnt1w z0.d, p0, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: stnt1w z0.d, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
Index: llvm/trunk/test/MC/AArch64/SVE/sub-diagnostics.s
===================================================================
--- llvm/trunk/test/MC/AArch64/SVE/sub-diagnostics.s
+++ llvm/trunk/test/MC/AArch64/SVE/sub-diagnostics.s
@@ -14,7 +14,7 @@
 
 // Element size specifiers should match.
 sub z0.h, z8.h, z8.b
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: sub z0.h, z8.h, z8.b
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
Index: llvm/trunk/test/MC/AArch64/SVE/zip1-diagnostics.s
===================================================================
--- llvm/trunk/test/MC/AArch64/SVE/zip1-diagnostics.s
+++ llvm/trunk/test/MC/AArch64/SVE/zip1-diagnostics.s
@@ -8,7 +8,7 @@
 
 // Element size specifiers should match.
 zip1 z10.h, z3.h, z15.b
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: zip1 z10.h, z3.h, z15.b
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
@@ -26,7 +26,7 @@
 
 // p16 is not a valid SVE predicate register
 zip1 p1.s, p2.s, p16.s
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 // CHECK-NEXT: zip1 p1.s, p2.s, p16.s
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
@@ -38,6 +38,6 @@
 
 // Combining predicate and data registers as operands
 zip1 p1.s, p2.s, z3.s
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 // CHECK-NEXT: zip1 p1.s, p2.s, z3.s
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Index: llvm/trunk/test/MC/AArch64/SVE/zip2-diagnostics.s
===================================================================
--- llvm/trunk/test/MC/AArch64/SVE/zip2-diagnostics.s
+++ llvm/trunk/test/MC/AArch64/SVE/zip2-diagnostics.s
@@ -8,7 +8,7 @@
 
 // Element size specifiers should match.
 zip2 z0.h, z30.h, z24.b
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
 // CHECK-NEXT: zip2 z0.h, z30.h, z24.b
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
@@ -26,7 +26,7 @@
 
 // p16 is not a valid SVE predicate register
 zip2 p1.s, p2.s, p16.s
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 // CHECK-NEXT: zip2 p1.s, p2.s, p16.s
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
@@ -38,6 +38,6 @@
 
 // Combining predicate and data registers as operands
 zip2 p1.s, p2.s, z3.s
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 // CHECK-NEXT: zip2 p1.s, p2.s, z3.s
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: