Index: lib/Target/AArch64/AArch64SVEInstrInfo.td =================================================================== --- lib/Target/AArch64/AArch64SVEInstrInfo.td +++ lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -400,6 +400,40 @@ def PRFS_PRR : sve_mem_prfm_ss<0b101, "prfw", GPR64NoXZRshifted32>; def PRFD_PRR : sve_mem_prfm_ss<0b111, "prfd", GPR64NoXZRshifted64>; + // Gather prefetch using scaled 32-bit offsets, e.g. + // prfh pldl1keep, p0, [x0, z0.s, uxtw #1] + defm PRFB_S : sve_mem_32b_prfm_sv_scaled<0b00, "prfb", ZPR32ExtSXTW8Only, ZPR32ExtUXTW8Only>; + defm PRFH_S : sve_mem_32b_prfm_sv_scaled<0b01, "prfh", ZPR32ExtSXTW16, ZPR32ExtUXTW16>; + defm PRFW_S : sve_mem_32b_prfm_sv_scaled<0b10, "prfw", ZPR32ExtSXTW32, ZPR32ExtUXTW32>; + defm PRFD_S : sve_mem_32b_prfm_sv_scaled<0b11, "prfd", ZPR32ExtSXTW64, ZPR32ExtUXTW64>; + + // Gather prefetch using unpacked, scaled 32-bit offsets, e.g. + // prfh pldl1keep, p0, [x0, z0.d, uxtw #1] + defm PRFB_D : sve_mem_64b_prfm_sv_ext_scaled<0b00, "prfb", ZPR64ExtSXTW8Only, ZPR64ExtUXTW8Only>; + defm PRFH_D : sve_mem_64b_prfm_sv_ext_scaled<0b01, "prfh", ZPR64ExtSXTW16, ZPR64ExtUXTW16>; + defm PRFW_D : sve_mem_64b_prfm_sv_ext_scaled<0b10, "prfw", ZPR64ExtSXTW32, ZPR64ExtUXTW32>; + defm PRFD_D : sve_mem_64b_prfm_sv_ext_scaled<0b11, "prfd", ZPR64ExtSXTW64, ZPR64ExtUXTW64>; + + // Gather prefetch using scaled 64-bit offsets, e.g. + // prfh pldl1keep, p0, [x0, z0.d, lsl #1] + defm PRFB_D_SCALED : sve_mem_64b_prfm_sv_lsl_scaled<0b00, "prfb", ZPR64ExtLSL8>; + defm PRFH_D_SCALED : sve_mem_64b_prfm_sv_lsl_scaled<0b01, "prfh", ZPR64ExtLSL16>; + defm PRFW_D_SCALED : sve_mem_64b_prfm_sv_lsl_scaled<0b10, "prfw", ZPR64ExtLSL32>; + defm PRFD_D_SCALED : sve_mem_64b_prfm_sv_lsl_scaled<0b11, "prfd", ZPR64ExtLSL64>; + + // Gather prefetch using 32/64-bit pointers with offset, e.g. + // prfh pldl1keep, p0, [z0.s, #16] + // prfh pldl1keep, p0, [z0.d, #16] + defm PRFB_S_PZI : sve_mem_32b_prfm_vi<0b00, "prfb", imm0_31>; + defm PRFH_S_PZI : sve_mem_32b_prfm_vi<0b01, "prfh", uimm5s2>; + defm PRFW_S_PZI : sve_mem_32b_prfm_vi<0b10, "prfw", uimm5s4>; + defm PRFD_S_PZI : sve_mem_32b_prfm_vi<0b11, "prfd", uimm5s8>; + + defm PRFB_D_PZI : sve_mem_64b_prfm_vi<0b00, "prfb", imm0_31>; + defm PRFH_D_PZI : sve_mem_64b_prfm_vi<0b01, "prfh", uimm5s2>; + defm PRFW_D_PZI : sve_mem_64b_prfm_vi<0b10, "prfw", uimm5s4>; + defm PRFD_D_PZI : sve_mem_64b_prfm_vi<0b11, "prfd", uimm5s8>; + defm ZIP1_ZZZ : sve_int_perm_bin_perm_zz<0b000, "zip1">; defm ZIP2_ZZZ : sve_int_perm_bin_perm_zz<0b001, "zip2">; Index: lib/Target/AArch64/SVEInstrFormats.td =================================================================== --- lib/Target/AArch64/SVEInstrFormats.td +++ lib/Target/AArch64/SVEInstrFormats.td @@ -1347,6 +1347,64 @@ let hasSideEffects = 1; } +class sve_mem_32b_prfm_sv msz, bit xs, string asm, + RegisterOperand zprext> +: I<(outs), (ins sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm), + asm, "\t$prfop, $Pg, [$Rn, $Zm]", + "", + []>, Sched<[]> { + bits<3> Pg; + bits<5> Rn; + bits<5> Zm; + bits<4> prfop; + let Inst{31-23} = 0b100001000; + let Inst{22} = xs; + let Inst{21} = 0b1; + let Inst{20-16} = Zm; + let Inst{15} = 0b0; + let Inst{14-13} = msz; + let Inst{12-10} = Pg; + let Inst{9-5} = Rn; + let Inst{4} = 0b0; + let Inst{3-0} = prfop; + + let hasSideEffects = 1; +} + +multiclass sve_mem_32b_prfm_sv_scaled msz, string asm, + RegisterOperand sxtw_opnd, + RegisterOperand uxtw_opnd> { + def _UXTW_SCALED : sve_mem_32b_prfm_sv; + def _SXTW_SCALED : sve_mem_32b_prfm_sv; +} + +class sve_mem_32b_prfm_vi msz, string asm, Operand imm_ty> +: I<(outs), (ins sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, imm_ty:$imm5), + asm, "\t$prfop, $Pg, [$Zn, $imm5]", + "", + []>, Sched<[]> { + bits<3> Pg; + bits<5> Zn; + bits<5> imm5; + bits<4> prfop; + let Inst{31-25} = 0b1000010; + let Inst{24-23} = msz; + let Inst{22-21} = 0b00; + let Inst{20-16} = imm5; + let Inst{15-13} = 0b111; + let Inst{12-10} = Pg; + let Inst{9-5} = Zn; + let Inst{4} = 0b0; + let Inst{3-0} = prfop; +} + +multiclass sve_mem_32b_prfm_vi msz, string asm, Operand imm_ty> { + def NAME : sve_mem_32b_prfm_vi; + + def : InstAlias(NAME) sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0), 1>; +} + class sve_mem_z_fill : I<(outs ZPRAny:$Zt), (ins GPR64sp:$Rn, simm9:$imm9), asm, "\t$Zt, [$Rn, $imm9, mul vl]", @@ -1504,3 +1562,70 @@ def : InstAlias(NAME # _IMM_REAL) Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0), 1>; } + +// bit lsl is '0' if the offsets are extended (uxtw/sxtw), '1' if shifted (lsl) +class sve_mem_64b_prfm_sv msz, bit xs, bit lsl, string asm, + RegisterOperand zprext> +: I<(outs), (ins sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm), + asm, "\t$prfop, $Pg, [$Rn, $Zm]", + "", + []>, Sched<[]> { + bits<3> Pg; + bits<5> Rn; + bits<5> Zm; + bits<4> prfop; + let Inst{31-23} = 0b110001000; + let Inst{22} = xs; + let Inst{21} = 0b1; + let Inst{20-16} = Zm; + let Inst{15} = lsl; + let Inst{14-13} = msz; + let Inst{12-10} = Pg; + let Inst{9-5} = Rn; + let Inst{4} = 0b0; + let Inst{3-0} = prfop; + + let hasSideEffects = 1; +} + +multiclass sve_mem_64b_prfm_sv_ext_scaled msz, string asm, + RegisterOperand sxtw_opnd, + RegisterOperand uxtw_opnd> { + def _UXTW_SCALED : sve_mem_64b_prfm_sv; + def _SXTW_SCALED : sve_mem_64b_prfm_sv; +} + +multiclass sve_mem_64b_prfm_sv_lsl_scaled msz, string asm, + RegisterOperand zprext> { + def NAME : sve_mem_64b_prfm_sv; +} + + +class sve_mem_64b_prfm_vi msz, string asm, Operand imm_ty> +: I<(outs), (ins sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, imm_ty:$imm5), + asm, "\t$prfop, $Pg, [$Zn, $imm5]", + "", + []>, Sched<[]> { + bits<3> Pg; + bits<5> Zn; + bits<5> imm5; + bits<4> prfop; + let Inst{31-25} = 0b1100010; + let Inst{24-23} = msz; + let Inst{22-21} = 0b00; + let Inst{20-16} = imm5; + let Inst{15-13} = 0b111; + let Inst{12-10} = Pg; + let Inst{9-5} = Zn; + let Inst{4} = 0b0; + let Inst{3-0} = prfop; + + let hasSideEffects = 1; +} + +multiclass sve_mem_64b_prfm_vi msz, string asm, Operand imm_ty> { + def NAME : sve_mem_64b_prfm_vi; + + def : InstAlias(NAME) sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0), 1>; +} Index: test/MC/AArch64/SVE/prfb-diagnostics.s =================================================================== --- test/MC/AArch64/SVE/prfb-diagnostics.s +++ test/MC/AArch64/SVE/prfb-diagnostics.s @@ -26,7 +26,7 @@ // --------------------------------------------------------------------------// -// invalid addressing modes +// invalid scalar + scalar addressing modes prfb #0, p0, [x0, #-33, mul vl] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-32, 31]. @@ -55,6 +55,73 @@ // --------------------------------------------------------------------------// +// Invalid scalar + vector addressing modes + +prfb #0, p0, [x0, z0.b] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK-NEXT: prfb #0, p0, [x0, z0.b] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +prfb #0, p0, [x0, z0.h] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK-NEXT: prfb #0, p0, [x0, z0.h] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +prfb #0, p0, [x0, z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK-NEXT: prfb #0, p0, [x0, z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +prfb #0, p0, [x0, z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK-NEXT: prfb #0, p0, [x0, z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +prfb #0, p0, [x0, z0.s, uxtw #1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK-NEXT: prfb #0, p0, [x0, z0.s, uxtw #1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +prfb #0, p0, [x0, z0.s, lsl #0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK-NEXT: prfb #0, p0, [x0, z0.s, lsl #0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +prfb #0, p0, [x0, z0.d, lsl #1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK-NEXT: prfb #0, p0, [x0, z0.d, lsl #1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +prfb #0, p0, [x0, z0.d, sxtw #1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK-NEXT: prfb #0, p0, [x0, z0.d, sxtw #1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid vector + immediate addressing modes + +prfb #0, p0, [z0.s, #-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]. +// CHECK-NEXT: prfb #0, p0, [z0.s, #-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +prfb #0, p0, [z0.s, #32] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]. +// CHECK-NEXT: prfb #0, p0, [z0.s, #32] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +prfb #0, p0, [z0.d, #-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]. +// CHECK-NEXT: prfb #0, p0, [z0.d, #-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +prfb #0, p0, [z0.d, #32] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]. +// CHECK-NEXT: prfb #0, p0, [z0.d, #32] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// // invalid predicate prfb #0, p8, [x0] Index: test/MC/AArch64/SVE/prfb.s =================================================================== --- test/MC/AArch64/SVE/prfb.s +++ test/MC/AArch64/SVE/prfb.s @@ -192,3 +192,57 @@ // CHECK-ENCODING: [0x01,0x00,0xdf,0x85] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 01 00 df 85 + +prfb pldl1keep, p0, [x0, z0.s, uxtw] +// CHECK-INST: prfb pldl1keep, p0, [x0, z0.s, uxtw] +// CHECK-ENCODING: [0x00,0x00,0x20,0x84] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 00 20 84 + +prfb pldl3strm, p5, [x10, z21.s, uxtw] +// CHECK-INST: prfb pldl3strm, p5, [x10, z21.s, uxtw] +// CHECK-ENCODING: [0x45,0x15,0x35,0x84] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 45 15 35 84 + +prfb pldl1keep, p0, [x0, z0.d, uxtw] +// CHECK-INST: prfb pldl1keep, p0, [x0, z0.d, uxtw] +// CHECK-ENCODING: [0x00,0x00,0x20,0xc4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 00 20 c4 + +prfb pldl3strm, p5, [x10, z21.d, sxtw] +// CHECK-INST: prfb pldl3strm, p5, [x10, z21.d, sxtw] +// CHECK-ENCODING: [0x45,0x15,0x75,0xc4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 45 15 75 c4 + +prfb pldl1keep, p0, [x0, z0.d] +// CHECK-INST: prfb pldl1keep, p0, [x0, z0.d] +// CHECK-ENCODING: [0x00,0x80,0x60,0xc4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 80 60 c4 + +prfb #7, p3, [z13.s, #0] +// CHECK-INST: prfb #7, p3, [z13.s] +// CHECK-ENCODING: [0xa7,0xed,0x00,0x84] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: a7 ed 00 84 + +prfb #7, p3, [z13.s, #31] +// CHECK-INST: prfb #7, p3, [z13.s, #31] +// CHECK-ENCODING: [0xa7,0xed,0x1f,0x84] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: a7 ed 1f 84 + +prfb pldl3strm, p5, [z10.d, #0] +// CHECK-INST: prfb pldl3strm, p5, [z10.d] +// CHECK-ENCODING: [0x45,0xf5,0x00,0xc4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 45 f5 00 c4 + +prfb pldl3strm, p5, [z10.d, #31] +// CHECK-INST: prfb pldl3strm, p5, [z10.d, #31] +// CHECK-ENCODING: [0x45,0xf5,0x1f,0xc4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 45 f5 1f c4 Index: test/MC/AArch64/SVE/prfd-diagnostics.s =================================================================== --- test/MC/AArch64/SVE/prfd-diagnostics.s +++ test/MC/AArch64/SVE/prfd-diagnostics.s @@ -26,7 +26,7 @@ // --------------------------------------------------------------------------// -// invalid addressing modes +// invalid scalar + scalar addressing modes prfd #0, p0, [x0, #-33, mul vl] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-32, 31]. @@ -55,6 +55,59 @@ // --------------------------------------------------------------------------// +// Invalid scalar + vector addressing modes + +prfd #0, p0, [x0, z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #3' +// CHECK-NEXT: prfd #0, p0, [x0, z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +prfd #0, p0, [x0, z0.d, uxtw #2] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #3' +// CHECK-NEXT: prfd #0, p0, [x0, z0.d, uxtw #2] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +prfd #0, p0, [x0, z0.d, lsl #2] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #3' +// CHECK-NEXT: prfd #0, p0, [x0, z0.d, lsl #2] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +prfd #0, p0, [x0, z0.d, lsl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected #imm after shift specifier +// CHECK-NEXT: prfd #0, p0, [x0, z0.d, lsl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid vector + immediate addressing modes + +prfd #0, p0, [z0.d, #-8] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248]. +// CHECK-NEXT: prfd #0, p0, [z0.d, #-8] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +prfd #0, p0, [z0.d, #-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248]. +// CHECK-NEXT: prfd #0, p0, [z0.d, #-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +prfd #0, p0, [z0.d, #249] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248]. +// CHECK-NEXT: prfd #0, p0, [z0.d, #249] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +prfd #0, p0, [z0.d, #256] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248]. +// CHECK-NEXT: prfd #0, p0, [z0.d, #256] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +prfd #0, p0, [z0.d, #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248]. +// CHECK-NEXT: prfd #0, p0, [z0.d, #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// // invalid predicate prfd #0, p8, [x0] Index: test/MC/AArch64/SVE/prfd.s =================================================================== --- test/MC/AArch64/SVE/prfd.s +++ test/MC/AArch64/SVE/prfd.s @@ -192,3 +192,57 @@ // CHECK-ENCODING: [0x01,0x60,0xdf,0x85] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 01 60 df 85 + +prfd pldl1keep, p0, [x0, z0.s, uxtw #3] +// CHECK-INST: prfd pldl1keep, p0, [x0, z0.s, uxtw #3] +// CHECK-ENCODING: [0x00,0x60,0x20,0x84] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 60 20 84 + +prfd pldl1keep, p0, [x0, z0.s, sxtw #3] +// CHECK-INST: prfd pldl1keep, p0, [x0, z0.s, sxtw #3] +// CHECK-ENCODING: [0x00,0x60,0x60,0x84] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 60 60 84 + +prfd pldl1keep, p0, [x0, z0.d, uxtw #3] +// CHECK-INST: prfd pldl1keep, p0, [x0, z0.d, uxtw #3] +// CHECK-ENCODING: [0x00,0x60,0x20,0xc4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 60 20 c4 + +prfd pldl1keep, p0, [x0, z0.d, sxtw #3] +// CHECK-INST: prfd pldl1keep, p0, [x0, z0.d, sxtw #3] +// CHECK-ENCODING: [0x00,0x60,0x60,0xc4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 60 60 c4 + +prfd pldl1keep, p0, [x0, z0.d, lsl #3] +// CHECK-INST: prfd pldl1keep, p0, [x0, z0.d, lsl #3] +// CHECK-ENCODING: [0x00,0xe0,0x60,0xc4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 e0 60 c4 + +prfd #15, p7, [z31.s, #0] +// CHECK-INST: prfd #15, p7, [z31.s] +// CHECK-ENCODING: [0xef,0xff,0x80,0x85] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ef ff 80 85 + +prfd #15, p7, [z31.s, #248] +// CHECK-INST: prfd #15, p7, [z31.s, #248] +// CHECK-ENCODING: [0xef,0xff,0x9f,0x85] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ef ff 9f 85 + +prfd #15, p7, [z31.d, #0] +// CHECK-INST: prfd #15, p7, [z31.d] +// CHECK-ENCODING: [0xef,0xff,0x80,0xc5] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ef ff 80 c5 + +prfd #15, p7, [z31.d, #248] +// CHECK-INST: prfd #15, p7, [z31.d, #248] +// CHECK-ENCODING: [0xef,0xff,0x9f,0xc5] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ef ff 9f c5 Index: test/MC/AArch64/SVE/prfh-diagnostics.s =================================================================== --- test/MC/AArch64/SVE/prfh-diagnostics.s +++ test/MC/AArch64/SVE/prfh-diagnostics.s @@ -26,7 +26,7 @@ // --------------------------------------------------------------------------// -// invalid addressing modes +// invalid scalar + scalar addressing modes prfh #0, p0, [x0, #-33, mul vl] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-32, 31]. @@ -55,6 +55,98 @@ // --------------------------------------------------------------------------// +// Invalid scalar + vector addressing modes + +prfh #0, p0, [x0, z0.h] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1' +// CHECK-NEXT: prfh #0, p0, [x0, z0.h] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +prfh #0, p0, [x0, z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1' +// CHECK-NEXT: prfh #0, p0, [x0, z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +prfh #0, p0, [x0, z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1' +// CHECK-NEXT: prfh #0, p0, [x0, z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +prfh #0, p0, [x0, z0.s, uxtw #2] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1' +// CHECK-NEXT: prfh #0, p0, [x0, z0.s, uxtw #2] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +prfh #0, p0, [x0, z0.s, lsl #1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1' +// CHECK-NEXT: prfh #0, p0, [x0, z0.s, lsl #1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +prfh #0, p0, [x0, z0.d, lsl #2] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1' +// CHECK-NEXT: prfh #0, p0, [x0, z0.d, lsl #2] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +prfh #0, p0, [x0, z0.d, sxtw #2] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1' +// CHECK-NEXT: prfh #0, p0, [x0, z0.d, sxtw #2] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid vector + immediate addressing modes + +prfh #0, p0, [z0.s, #-2] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62]. +// CHECK-NEXT: prfh #0, p0, [z0.s, #-2] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +prfh #0, p0, [z0.s, #-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62]. +// CHECK-NEXT: prfh #0, p0, [z0.s, #-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +prfh #0, p0, [z0.s, #63] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62]. +// CHECK-NEXT: prfh #0, p0, [z0.s, #63] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +prfh #0, p0, [z0.s, #64] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62]. +// CHECK-NEXT: prfh #0, p0, [z0.s, #64] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +prfh #0, p0, [z0.s, #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62]. +// CHECK-NEXT: prfh #0, p0, [z0.s, #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +prfh #0, p0, [z0.d, #-2] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62]. +// CHECK-NEXT: prfh #0, p0, [z0.d, #-2] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +prfh #0, p0, [z0.d, #-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62]. +// CHECK-NEXT: prfh #0, p0, [z0.d, #-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +prfh #0, p0, [z0.d, #63] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62]. +// CHECK-NEXT: prfh #0, p0, [z0.d, #63] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +prfh #0, p0, [z0.d, #64] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62]. +// CHECK-NEXT: prfh #0, p0, [z0.d, #64] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +prfh #0, p0, [z0.d, #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62]. +// CHECK-NEXT: prfh #0, p0, [z0.d, #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// // invalid predicate prfh #0, p8, [x0] Index: test/MC/AArch64/SVE/prfh.s =================================================================== --- test/MC/AArch64/SVE/prfh.s +++ test/MC/AArch64/SVE/prfh.s @@ -192,3 +192,57 @@ // CHECK-ENCODING: [0x01,0x20,0xdf,0x85] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 01 20 df 85 + +prfh pldl3strm, p5, [x10, z21.s, uxtw #1] +// CHECK-INST: prfh pldl3strm, p5, [x10, z21.s, uxtw #1] +// CHECK-ENCODING: [0x45,0x35,0x35,0x84] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 45 35 35 84 + +prfh pldl3strm, p5, [x10, z21.s, sxtw #1] +// CHECK-INST: prfh pldl3strm, p5, [x10, z21.s, sxtw #1] +// CHECK-ENCODING: [0x45,0x35,0x75,0x84] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 45 35 75 84 + +prfh pldl3strm, p5, [x10, z21.d, uxtw #1] +// CHECK-INST: prfh pldl3strm, p5, [x10, z21.d, uxtw #1] +// CHECK-ENCODING: [0x45,0x35,0x35,0xc4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 45 35 35 c4 + +prfh pldl3strm, p5, [x10, z21.d, sxtw #1] +// CHECK-INST: prfh pldl3strm, p5, [x10, z21.d, sxtw #1] +// CHECK-ENCODING: [0x45,0x35,0x75,0xc4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 45 35 75 c4 + +prfh pldl1keep, p0, [x0, z0.d, lsl #1] +// CHECK-INST: prfh pldl1keep, p0, [x0, z0.d, lsl #1] +// CHECK-ENCODING: [0x00,0xa0,0x60,0xc4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 a0 60 c4 + +prfh #15, p7, [z31.s, #0] +// CHECK-INST: prfh #15, p7, [z31.s] +// CHECK-ENCODING: [0xef,0xff,0x80,0x84] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ef ff 80 84 + +prfh #15, p7, [z31.s, #62] +// CHECK-INST: prfh #15, p7, [z31.s, #62] +// CHECK-ENCODING: [0xef,0xff,0x9f,0x84] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ef ff 9f 84 + +prfh #15, p7, [z31.d, #0] +// CHECK-INST: prfh #15, p7, [z31.d] +// CHECK-ENCODING: [0xef,0xff,0x80,0xc4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ef ff 80 c4 + +prfh #15, p7, [z31.d, #62] +// CHECK-INST: prfh #15, p7, [z31.d, #62] +// CHECK-ENCODING: [0xef,0xff,0x9f,0xc4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ef ff 9f c4 Index: test/MC/AArch64/SVE/prfw-diagnostics.s =================================================================== --- test/MC/AArch64/SVE/prfw-diagnostics.s +++ test/MC/AArch64/SVE/prfw-diagnostics.s @@ -26,7 +26,7 @@ // --------------------------------------------------------------------------// -// invalid addressing modes +// invalid scalar + scalar addressing modes prfw #0, p0, [x0, #-33, mul vl] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-32, 31]. @@ -55,6 +55,99 @@ // --------------------------------------------------------------------------// +// Invalid scalar + vector addressing modes + +prfw #0, p0, [x0, z0.h] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2' +// CHECK-NEXT: prfw #0, p0, [x0, z0.h] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +prfw #0, p0, [x0, z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2' +// CHECK-NEXT: prfw #0, p0, [x0, z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +prfw #0, p0, [x0, z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2' +// CHECK-NEXT: prfw #0, p0, [x0, z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +prfw #0, p0, [x0, z0.s, uxtw #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2' +// CHECK-NEXT: prfw #0, p0, [x0, z0.s, uxtw #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +prfw #0, p0, [x0, z0.s, lsl #2] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2' +// CHECK-NEXT: prfw #0, p0, [x0, z0.s, lsl #2] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +prfw #0, p0, [x0, z0.d, lsl #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2' +// CHECK-NEXT: prfw #0, p0, [x0, z0.d, lsl #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +prfw #0, p0, [x0, z0.d, sxtw #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2' +// CHECK-NEXT: prfw #0, p0, [x0, z0.d, sxtw #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid vector + immediate addressing modes + +prfw #0, p0, [z0.s, #-4] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124]. +// CHECK-NEXT: prfw #0, p0, [z0.s, #-4] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +prfw #0, p0, [z0.s, #-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124]. +// CHECK-NEXT: prfw #0, p0, [z0.s, #-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +prfw #0, p0, [z0.s, #125] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124]. +// CHECK-NEXT: prfw #0, p0, [z0.s, #125] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +prfw #0, p0, [z0.s, #128] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124]. +// CHECK-NEXT: prfw #0, p0, [z0.s, #128] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +prfw #0, p0, [z0.s, #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124]. +// CHECK-NEXT: prfw #0, p0, [z0.s, #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +prfw #0, p0, [z0.d, #-4] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124]. +// CHECK-NEXT: prfw #0, p0, [z0.d, #-4] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +prfw #0, p0, [z0.d, #-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124]. +// CHECK-NEXT: prfw #0, p0, [z0.d, #-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +prfw #0, p0, [z0.d, #125] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124]. +// CHECK-NEXT: prfw #0, p0, [z0.d, #125] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +prfw #0, p0, [z0.d, #128] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124]. +// CHECK-NEXT: prfw #0, p0, [z0.d, #128] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +prfw #0, p0, [z0.d, #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124]. +// CHECK-NEXT: prfw #0, p0, [z0.d, #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// // invalid predicate prfw #0, p8, [x0] Index: test/MC/AArch64/SVE/prfw.s =================================================================== --- test/MC/AArch64/SVE/prfw.s +++ test/MC/AArch64/SVE/prfw.s @@ -192,3 +192,57 @@ // CHECK-ENCODING: [0x01,0x40,0xdf,0x85] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 01 40 df 85 + +prfw pldl1keep, p0, [x0, z0.s, uxtw #2] +// CHECK-INST: prfw pldl1keep, p0, [x0, z0.s, uxtw #2] +// CHECK-ENCODING: [0x00,0x40,0x20,0x84] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 40 20 84 + +prfw pldl3strm, p5, [x10, z21.s, sxtw #2] +// CHECK-INST: prfw pldl3strm, p5, [x10, z21.s, sxtw #2] +// CHECK-ENCODING: [0x45,0x55,0x75,0x84] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 45 55 75 84 + +prfw #7, p3, [x13, z8.d, uxtw #2] +// CHECK-INST: prfw #7, p3, [x13, z8.d, uxtw #2] +// CHECK-ENCODING: [0xa7,0x4d,0x28,0xc4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: a7 4d 28 c4 + +prfw pldl1keep, p0, [x0, z0.d, sxtw #2] +// CHECK-INST: prfw pldl1keep, p0, [x0, z0.d, sxtw #2] +// CHECK-ENCODING: [0x00,0x40,0x60,0xc4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 40 60 c4 + +prfw pldl3strm, p5, [x10, z21.d, lsl #2] +// CHECK-INST: prfw pldl3strm, p5, [x10, z21.d, lsl #2] +// CHECK-ENCODING: [0x45,0xd5,0x75,0xc4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 45 d5 75 c4 + +prfw #15, p7, [z31.s, #0] +// CHECK-INST: prfw #15, p7, [z31.s] +// CHECK-ENCODING: [0xef,0xff,0x00,0x85] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ef ff 00 85 + +prfw #15, p7, [z31.s, #124] +// CHECK-INST: prfw #15, p7, [z31.s, #124] +// CHECK-ENCODING: [0xef,0xff,0x1f,0x85] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ef ff 1f 85 + +prfw #15, p7, [z31.d, #0] +// CHECK-INST: prfw #15, p7, [z31.d] +// CHECK-ENCODING: [0xef,0xff,0x00,0xc5] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ef ff 00 c5 + +prfw #15, p7, [z31.d, #124] +// CHECK-INST: prfw #15, p7, [z31.d, #124] +// CHECK-ENCODING: [0xef,0xff,0x1f,0xc5] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ef ff 1f c5