Index: llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td =================================================================== --- llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td +++ llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td @@ -797,9 +797,9 @@ MMRel, LW_FM_MM<0x7>, ISA_MICROMIPS; def LBu_MM : LoadMemory<"lbu", GPR32Opnd, mem_mm_16, zextloadi8, II_LBU>, MMRel, LW_FM_MM<0x5>, ISA_MICROMIPS; - def LH_MM : LoadMemory<"lh", GPR32Opnd, mem_simm16, sextloadi16, II_LH, + def LH_MM : LoadMemory<"lh", GPR32Opnd, mem_simmptr, sextloadi16, II_LH, addrDefault>, MMRel, LW_FM_MM<0xf>, ISA_MICROMIPS; - def LHu_MM : LoadMemory<"lhu", GPR32Opnd, mem_simm16, zextloadi16, II_LHU>, + def LHu_MM : LoadMemory<"lhu", GPR32Opnd, mem_simmptr, zextloadi16, II_LHU>, MMRel, LW_FM_MM<0xd>, ISA_MICROMIPS; def LW_MM : Load<"lw", GPR32Opnd, null_frag, II_LW>, MMRel, LW_FM_MM<0x3f>, ISA_MICROMIPS; Index: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td =================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td @@ -2040,9 +2040,9 @@ LW_FM<0x20>; def LBu : LoadMemory<"lbu", GPR32Opnd, mem_simmptr, zextloadi8, II_LBU, addrDefault>, MMRel, LW_FM<0x24>; - def LH : LoadMemory<"lh", GPR32Opnd, mem_simm16, sextloadi16, II_LH, + def LH : LoadMemory<"lh", GPR32Opnd, mem_simmptr, sextloadi16, II_LH, addrDefault>, MMRel, LW_FM<0x21>; - def LHu : LoadMemory<"lhu", GPR32Opnd, mem_simm16, zextloadi16, II_LHU>, + def LHu : LoadMemory<"lhu", GPR32Opnd, mem_simmptr, zextloadi16, II_LHU>, MMRel, LW_FM<0x25>; def LW : StdMMR6Rel, Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel, LW_FM<0x23>; Index: llvm/trunk/test/MC/Mips/micromips-expansions.s =================================================================== --- llvm/trunk/test/MC/Mips/micromips-expansions.s +++ llvm/trunk/test/MC/Mips/micromips-expansions.s @@ -55,3 +55,21 @@ lw $t2, 655483($a0) sw $t2, 123456($t1) + + lh $4, 0x8000 +# CHECK-LE: lui $4, 1 +# CHECK-LE: lh $4, -32768($4) + + lh $4, 0x20004($3) +# CHECK-LE: lui $4, 2 +# CHECK-LE: addu $4, $4, $3 +# CHECK-LE: lh $4, 4($4) + + lhu $4, 0x8000 +# CHECK-LE: lui $4, 1 +# CHECK-LE: lhu $4, -32768($4) + + lhu $4, 0x20004($3) +# CHECK-LE: lui $4, 2 +# CHECK-LE: addu $4, $4, $3 +# CHECK-LE: lhu $4, 4($4) Index: llvm/trunk/test/MC/Mips/micromips/invalid.s =================================================================== --- llvm/trunk/test/MC/Mips/micromips/invalid.s +++ llvm/trunk/test/MC/Mips/micromips/invalid.s @@ -91,12 +91,12 @@ lhe $4, 8($33) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number lhu $4, 8($35) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number lhue $4, 8($37) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number - lh $2, -65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset - lh $2, 65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset + lh $2, -2147483649($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed offset + lh $2, 2147483648($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed offset lhe $4, -512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset lhe $4, 512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - lhu $4, -65536($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset - lhu $4, 65536($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset + lhu $4, -2147483649($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed offset + lhu $4, 2147483648($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed offset lhue $4, -512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset lhue $4, 512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset lwp $31, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction Index: llvm/trunk/test/MC/Mips/micromips32r6/invalid.s =================================================================== --- llvm/trunk/test/MC/Mips/micromips32r6/invalid.s +++ llvm/trunk/test/MC/Mips/micromips32r6/invalid.s @@ -183,12 +183,12 @@ lhe $4, 8($33) # CHECK: :[[@LINE]]:13: error: invalid register number lhu $4, 8($35) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number lhue $4, 8($37) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number - lh $2, -65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset - lh $2, 65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset + lh $2, -2147483649($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed offset + lh $2, 2147483648($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed offset lhe $4, -512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset lhe $4, 512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - lhu $4, -65536($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset - lhu $4, 65536($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset + lhu $4, -2147483649($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed offset + lhu $4, 2147483648($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed offset lhue $4, -512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset lhue $4, 512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset lwm32 $5, $6, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected Index: llvm/trunk/test/MC/Mips/mips-expansions.s =================================================================== --- llvm/trunk/test/MC/Mips/mips-expansions.s +++ llvm/trunk/test/MC/Mips/mips-expansions.s @@ -31,6 +31,24 @@ # CHECK-LE: addu $4, $4, $3 # encoding: [0x21,0x20,0x83,0x00] # CHECK-LE: lbu $4, 4($4) # encoding: [0x04,0x00,0x84,0x90] + lh $4, 0x8000 +# CHECK-LE: lui $4, 1 +# CHECK-LE: lh $4, -32768($4) + + lh $4, 0x20004($3) +# CHECK-LE: lui $4, 2 +# CHECK-LE: addu $4, $4, $3 +# CHECK-LE: lh $4, 4($4) + + lhu $4, 0x8000 +# CHECK-LE: lui $4, 1 +# CHECK-LE: lhu $4, -32768($4) + + lhu $4, 0x20004($3) +# CHECK-LE: lui $4, 2 +# CHECK-LE: addu $4, $4, $3 +# CHECK-LE: lhu $4, 4($4) + # LW/SW and LDC1/SDC1 of symbol address, done by MipsAsmParser::expandMemInst(): .set noat lw $10, symbol($4) Index: llvm/trunk/test/MC/Mips/mips32r6/invalid.s =================================================================== --- llvm/trunk/test/MC/Mips/mips32r6/invalid.s +++ llvm/trunk/test/MC/Mips/mips32r6/invalid.s @@ -30,12 +30,12 @@ lhe $4, 8($33) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number lhu $4, 8($35) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number lhue $4, 8($37) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number - lh $2, -65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset - lh $2, 65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset + lh $2, -2147483649($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed offset + lh $2, 2147483648($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed offset lhe $4, -512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction lhe $4, 512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - lhu $4, -65536($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset - lhu $4, 65536($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset + lhu $4, -2147483649($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed offset + lhu $4, 2147483648($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed offset lhue $4, -512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction lhue $4, 512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction // FIXME: Following tests are temporarily disabled, until "PredicateControl not in hierarchy" problem is resolved Index: llvm/trunk/test/MC/Mips/mips64r6/invalid.s =================================================================== --- llvm/trunk/test/MC/Mips/mips64r6/invalid.s +++ llvm/trunk/test/MC/Mips/mips64r6/invalid.s @@ -60,12 +60,12 @@ lhe $4, 8($33) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number lhu $4, 8($35) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number lhue $4, 8($37) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number - lh $2, -65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset - lh $2, 65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset + lh $2, -2147483649($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed offset + lh $2, 2147483648($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed offset lhe $4, -512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction lhe $4, 512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - lhu $4, -65536($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset - lhu $4, 65536($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset + lhu $4, -2147483649($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed offset + lhu $4, 2147483648($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed offset lhue $4, -512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction lhue $4, 512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction // FIXME: Following tests are temporarily disabled, until "PredicateControl not in hierarchy" problem is resolved