Index: lib/Target/Mips/MicroMipsInstrFPU.td =================================================================== --- lib/Target/Mips/MicroMipsInstrFPU.td +++ lib/Target/Mips/MicroMipsInstrFPU.td @@ -197,24 +197,31 @@ def MTC1_MM : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1, bitconvert>, MFC1_FM_MM<0xa0>, ISA_MICROMIPS; +} -def MADD_S_MM : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>, - MADDS_FM_MM<0x1>, ISA_MICROMIPS32_NOT_MIPS32R6; -def MSUB_S_MM : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>, - MADDS_FM_MM<0x21>, ISA_MICROMIPS32_NOT_MIPS32R6; -def NMADD_S_MM : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S, fadd>, - MADDS_FM_MM<0x2>, ISA_MICROMIPS32_NOT_MIPS32R6; -def NMSUB_S_MM : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S, fsub>, - MADDS_FM_MM<0x22>, ISA_MICROMIPS32_NOT_MIPS32R6; - -def MADD_D32_MM : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D, fadd>, - MADDS_FM_MM<0x9>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; -def MSUB_D32_MM : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>, - MADDS_FM_MM<0x29>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; -def NMADD_D32_MM : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D, fadd>, - MADDS_FM_MM<0xa>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; -def NMSUB_D32_MM : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D, fsub>, - MADDS_FM_MM<0x2a>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; +let DecoderNamespace = "MicroMips" in { + def MADD_S_MM : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S>, + MADDS_FM_MM<0x1>, ISA_MICROMIPS32_NOT_MIPS32R6, MADD4; + def MSUB_S_MM : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S>, + MADDS_FM_MM<0x21>, ISA_MICROMIPS32_NOT_MIPS32R6, MADD4; + let AdditionalPredicates = [NoNaNsFPMath, HasMadd4] in { + def NMADD_S_MM : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S>, + MADDS_FM_MM<0x2>, ISA_MICROMIPS32_NOT_MIPS32R6; + def NMSUB_S_MM : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S>, + MADDS_FM_MM<0x22>, ISA_MICROMIPS32_NOT_MIPS32R6; + } + def MADD_D32_MM : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D>, + MADDS_FM_MM<0x9>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32, + MADD4; + def MSUB_D32_MM : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D>, + MADDS_FM_MM<0x29>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32, + MADD4; + let AdditionalPredicates = [NoNaNsFPMath, HasMadd4] in { + def NMADD_D32_MM : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D>, + MADDS_FM_MM<0xa>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; + def NMSUB_D32_MM : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D>, + MADDS_FM_MM<0x2a>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; + } } def FLOOR_W_S_MM : MMRel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, Index: lib/Target/Mips/MipsInstrFPU.td =================================================================== --- lib/Target/Mips/MipsInstrFPU.td +++ lib/Target/Mips/MipsInstrFPU.td @@ -606,38 +606,39 @@ defm FSUB : ADDS_M<"sub.d", II_SUB_D, 0, fsub>, ADDS_FM<0x01, 17>; } -def MADD_S : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>, - MADDS_FM<4, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6, MADD4; -def MSUB_S : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>, - MADDS_FM<5, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6, MADD4; +let AdditionalPredicates = [NotInMicroMips, HasMadd4] in { + def MADD_S : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>, + MADDS_FM<4, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6; + def MSUB_S : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>, + MADDS_FM<5, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6; +} -let AdditionalPredicates = [NoNaNsFPMath, HasMadd4] in { +let AdditionalPredicates = [NoNaNsFPMath, HasMadd4, NotInMicroMips] in { def NMADD_S : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S, fadd>, MADDS_FM<6, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6; def NMSUB_S : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S, fsub>, MADDS_FM<7, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6; } - -def MADD_D32 : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D, fadd>, - MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32, MADD4; -def MSUB_D32 : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>, - MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32, MADD4; - -let AdditionalPredicates = [NoNaNsFPMath, HasMadd4] in { +let AdditionalPredicates = [NotInMicroMips, HasMadd4] in { + def MADD_D32 : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D, fadd>, + MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32; + def MSUB_D32 : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>, + MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32; +} +let AdditionalPredicates = [NoNaNsFPMath, HasMadd4, NotInMicroMips] in { def NMADD_D32 : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D, fadd>, MADDS_FM<6, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32; def NMSUB_D32 : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D, fsub>, MADDS_FM<7, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32; } - -let DecoderNamespace = "MipsFP64" in { - def MADD_D64 : MADDS_FT<"madd.d", FGR64Opnd, II_MADD_D, fadd>, - MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64, MADD4; - def MSUB_D64 : MADDS_FT<"msub.d", FGR64Opnd, II_MSUB_D, fsub>, - MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64, MADD4; +let AdditionalPredicates = [NotInMicroMips, HasMadd4, NotInMicroMips], + DecoderNamespace = "MipsFP64" in { + def MADD_D64 : MADDS_FT<"madd.d", FGR64Opnd, II_MADD_D, fadd>, + MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64; + def MSUB_D64 : MADDS_FT<"msub.d", FGR64Opnd, II_MSUB_D, fsub>, + MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64; } - -let AdditionalPredicates = [NoNaNsFPMath, HasMadd4], +let AdditionalPredicates = [NoNaNsFPMath, HasMadd4, NotInMicroMips], DecoderNamespace = "MipsFP64" in { def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64Opnd, II_NMADD_D, fadd>, MADDS_FM<6, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64; Index: test/MC/Disassembler/Mips/micromips32r3/valid-el.txt =================================================================== --- test/MC/Disassembler/Mips/micromips32r3/valid-el.txt +++ test/MC/Disassembler/Mips/micromips32r3/valid-el.txt @@ -234,3 +234,11 @@ 0x02 0x54 0x7b 0x1b # CHECK: cvt.s.d $f0, $f2 0x07 0x00 0x7c 0x6b # CHECK: sync 7 0x03 0x42 0x00 0x04 # CHECK: synci 1024($3) +0xc4 0x54 0x81 0x00 # CHECK: madd.s $f0, $f2, $f4, $f6 +0xc4 0x54 0x89 0x00 # CHECK: madd.d $f0, $f2, $f4, $f6 +0xc4 0x54 0x82 0x00 # CHECK: nmadd.s $f0, $f2, $f4, $f6 +0xc4 0x54 0x8a 0x00 # CHECK: nmadd.d $f0, $f2, $f4, $f6 +0xc4 0x54 0xa1 0x00 # CHECK: msub.s $f0, $f2, $f4, $f6 +0xc4 0x54 0xa9 0x00 # CHECK: msub.d $f0, $f2, $f4, $f6 +0xc4 0x54 0xa2 0x00 # CHECK: nmsub.s $f0, $f2, $f4, $f6 +0xc4 0x54 0xaa 0x00 # CHECK: nmsub.d $f0, $f2, $f4, $f6 Index: test/MC/Disassembler/Mips/micromips32r3/valid.txt =================================================================== --- test/MC/Disassembler/Mips/micromips32r3/valid.txt +++ test/MC/Disassembler/Mips/micromips32r3/valid.txt @@ -236,3 +236,11 @@ 0x54 0x02 0x13 0x7b # CHECK: cvt.d.s $f0, $f2 0x54 0x02 0x33 0x7b # CHECK: cvt.d.w $f0, $f2 0x54 0x02 0x1b 0x7b # CHECK: cvt.s.d $f0, $f2 +0x54 0xc4 0x00 0x81 # CHECK: madd.s $f0, $f2, $f4, $f6 +0x54 0xc4 0x00 0x89 # CHECK: madd.d $f0, $f2, $f4, $f6 +0x54 0xc4 0x00 0x82 # CHECK: nmadd.s $f0, $f2, $f4, $f6 +0x54 0xc4 0x00 0x8a # CHECK: nmadd.d $f0, $f2, $f4, $f6 +0x54 0xc4 0x00 0xa1 # CHECK: msub.s $f0, $f2, $f4, $f6 +0x54 0xc4 0x00 0xa9 # CHECK: msub.d $f0, $f2, $f4, $f6 +0x54 0xc4 0x00 0xa2 # CHECK: nmsub.s $f0, $f2, $f4, $f6 +0x54 0xc4 0x00 0xaa # CHECK: nmsub.d $f0, $f2, $f4, $f6 Index: test/MC/Mips/micromips-fpu-instructions.s =================================================================== --- test/MC/Mips/micromips-fpu-instructions.s +++ test/MC/Mips/micromips-fpu-instructions.s @@ -153,12 +153,19 @@ # CHECK-EB: movf.d $f4, $f6, $fcc0 # encoding: [0x54,0x86,0x02,0x20] # CHECK-EB-NEXT: #