Index: lib/CodeGen/SelectionDAG/DAGCombiner.cpp =================================================================== --- lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -7252,20 +7252,25 @@ &DAG.getTarget().Options)) return GetNegatedExpression(N0, DAG, LegalOperations); - // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading + // Transform fneg(bitconvert(x)) -> bitconvert(x ^ sign) to avoid loading // constant pool values. - if (!TLI.isFNegFree(VT) && N0.getOpcode() == ISD::BITCAST && - !VT.isVector() && - N0.getNode()->hasOneUse() && - N0.getOperand(0).getValueType().isInteger()) { + if (!TLI.isFNegFree(VT) && + N0.getOpcode() == ISD::BITCAST && + N0.getNode()->hasOneUse()) { SDValue Int = N0.getOperand(0); EVT IntVT = Int.getValueType(); if (IntVT.isInteger() && !IntVT.isVector()) { + APInt SignMask; + if (N0.getValueType().isVector()) { + SignMask = APInt::getSignBit(N0.getValueType().getScalarSizeInBits()); + SignMask = APInt::getSplat(IntVT.getSizeInBits(), SignMask); + } else { + SignMask = APInt::getSignBit(IntVT.getSizeInBits()); + } Int = DAG.getNode(ISD::XOR, SDLoc(N0), IntVT, Int, - DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); + DAG.getConstant(SignMask, IntVT)); AddToWorklist(Int.getNode()); - return DAG.getNode(ISD::BITCAST, SDLoc(N), - VT, Int); + return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Int); } } @@ -7344,20 +7349,25 @@ if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0.getOperand(0)); - // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading + // Transform fabs(bitconvert(x)) -> bitconvert(x & ~sign) to avoid loading // constant pool values. if (!TLI.isFAbsFree(VT) && - N0.getOpcode() == ISD::BITCAST && N0.getNode()->hasOneUse() && - N0.getOperand(0).getValueType().isInteger() && - !N0.getOperand(0).getValueType().isVector()) { + N0.getOpcode() == ISD::BITCAST && + N0.getNode()->hasOneUse()) { SDValue Int = N0.getOperand(0); EVT IntVT = Int.getValueType(); if (IntVT.isInteger() && !IntVT.isVector()) { + APInt SignMask; + if (N0.getValueType().isVector()) { + SignMask = ~APInt::getSignBit(N0.getValueType().getScalarSizeInBits()); + SignMask = APInt::getSplat(IntVT.getSizeInBits(), SignMask); + } else { + SignMask = ~APInt::getSignBit(IntVT.getSizeInBits()); + } Int = DAG.getNode(ISD::AND, SDLoc(N0), IntVT, Int, - DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); + DAG.getConstant(SignMask, IntVT)); AddToWorklist(Int.getNode()); - return DAG.getNode(ISD::BITCAST, SDLoc(N), - N->getValueType(0), Int); + return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getValueType(0), Int); } } Index: test/CodeGen/ARM/2009-10-21-InvalidFNeg.ll =================================================================== --- test/CodeGen/ARM/2009-10-21-InvalidFNeg.ll +++ test/CodeGen/ARM/2009-10-21-InvalidFNeg.ll @@ -1,4 +1,5 @@ -; RUN: llc -mcpu=cortex-a8 -mattr=+neon < %s | grep vneg +; RUN: llc %s -mcpu=cortex-a8 -mattr=+neon -o - | FileCheck %s + target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" target triple = "armv7-eabi" @@ -10,6 +11,13 @@ %fff = type { %struct.vec_float4 } %struct.vec_float4 = type { <4 x float> } +; As part of the optimization from PR20354, this test should no longer use any VFP/NEON. +; CHECK-LABEL: foo +; CHECK: eor {{.*}}, {{.*}}, #-2147483648 +; CHECK: eor {{.*}}, {{.*}}, #-2147483648 +; CHECK: eor {{.*}}, {{.*}}, #-2147483648 +; CHECK: eor {{.*}}, {{.*}}, #-2147483648 + define linkonce_odr arm_aapcs_vfpcc void @foo(%eee* noalias sret %agg.result, i64 %tfrm.0.0, i64 %tfrm.0.1, i64 %tfrm.0.2, i64 %tfrm.0.3, i64 %tfrm.0.4, i64 %tfrm.0.5, i64 %tfrm.0.6, i64 %tfrm.0.7) nounwind noinline { entry: %tmp104 = zext i64 %tfrm.0.2 to i512 ; [#uses=1] Index: test/CodeGen/X86/vec_fabs.ll =================================================================== --- test/CodeGen/X86/vec_fabs.ll +++ test/CodeGen/X86/vec_fabs.ll @@ -36,3 +36,29 @@ ret <8 x float> %t } declare <8 x float> @llvm.fabs.v8f32(<8 x float> %p) + +; The following 2 tests are related to PR20354 ( http://llvm.org/bugs/show_bug.cgi?id=20354 ). +; If we're bitcasting to and from FP values, we can avoid the FPU entirely. + +; Make sure that we're only turning off the sign bit of each float value. + +; CHECK-LABEL: fabs_v2f32_1 +; CHECK: xorl %eax, %eax +; CHECK: movl $2147483647, %edx +define i64 @fabs_v2f32_1() { + %ones = bitcast i64 18446744069414584320 to <2 x float> ; 0xffffffff00000000 + %fabs = call <2 x float> @llvm.fabs.v2f32(<2 x float> %ones) + %ret = bitcast <2 x float> %fabs to i64 + ret i64 %ret +} + +; CHECK-LABEL: fabs_v2f32_2 +; CHECK: movl $2147483647, %eax +; CHECK: xorl %edx, %edx +define i64 @fabs_v2f32_2() { + %ones = bitcast i64 4294967295 to <2 x float> ; 0x00000000ffffffff + %fabs = call <2 x float> @llvm.fabs.v2f32(<2 x float> %ones) + %ret = bitcast <2 x float> %fabs to i64 + ret i64 %ret +} +declare <2 x float> @llvm.fabs.v2f32(<2 x float> %p) Index: test/CodeGen/X86/vec_fneg.ll =================================================================== --- test/CodeGen/X86/vec_fneg.ll +++ test/CodeGen/X86/vec_fneg.ll @@ -1,5 +1,6 @@ -; RUN: llc < %s -march=x86 -mattr=+sse2 +; RUN: llc < %s -march=x86 | FileCheck %s +; FIXME: The following 2 tests don't have any checks! define <4 x float> @t1(<4 x float> %Q) { %tmp15 = fsub <4 x float> < float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00 >, %Q ret <4 x float> %tmp15 @@ -9,3 +10,28 @@ %tmp15 = fsub <4 x float> zeroinitializer, %Q ret <4 x float> %tmp15 } + +; The following 2 tests are related to PR20354 ( http://llvm.org/bugs/show_bug.cgi?id=20354 ). +; If we're bitcasting to and from FP values, we can avoid the FPU entirely. + +; Make sure that we're only flipping the sign bit of each float. + +; CHECK-LABEL: fneg_v2f32_1 +; CHECK: movl $-2147483648, %eax +; CHECK: movl $2147483647, %edx +define i64 @fneg_v2f32_1() { + %ones = bitcast i64 18446744069414584320 to <2 x float> ; 0xffffffff00000000 + %fneg = fsub <2 x float> , %ones + %ret = bitcast <2 x float> %fneg to i64 + ret i64 %ret +} + +; CHECK-LABEL: fneg_v2f32_2 +; CHECK: movl $2147483647, %eax +; CHECK: movl $-2147483648, %edx +define i64 @fneg_v2f32_2() { + %ones = bitcast i64 4294967295 to <2 x float> ; 0x00000000ffffffff + %fneg = fsub <2 x float> , %ones + %ret = bitcast <2 x float> %fneg to i64 + ret i64 %ret +}