Index: lib/Target/AArch64/AArch64InstrFormats.td
===================================================================
--- lib/Target/AArch64/AArch64InstrFormats.td
+++ lib/Target/AArch64/AArch64InstrFormats.td
@@ -7792,16 +7792,23 @@
 multiclass SIMDFPScalarRShift<bit U, bits<5> opc, string asm> {
 
   let Predicates = [HasNEON, HasFullFP16] in {
-  def SHr : BaseSIMDScalarShift<U, opc, {0,0,1,?,?,?,?},
-                                FPR32, FPR16, vecshiftR32, asm, []> {
+  def HSr : BaseSIMDScalarShift<U, opc, {0,0,1,?,?,?,?},
+                                FPR16, FPR32, vecshiftR16, asm, []> {
     let Inst{19-16} = imm{3-0};
     let Inst{23-22} = 0b11;
   }
+  } // Predicates = [HasNEON, HasFullFP16]
+
+  let Predicates = [HasNEON, HasFullFP16] in {
+  def SHr : BaseSIMDScalarShift<U, opc, {?,?,?,?,?,?,?},
+                                FPR32, FPR16, vecshiftR32, asm, []> {
+    let Inst{19-16} = imm{3-0};
+  }
 
   } // Predicates = [HasNEON, HasFullFP16]
 
   def HDr : BaseSIMDScalarShift<U, opc, {?,?,?,?,?,?,?},
-                                FPR16, FPR64, vecshiftR16, asm, []> {
+                                FPR16, FPR64, vecshiftR32, asm, []> {
     let Inst{21-16} = imm{5-0};
     let Inst{23-22} = 0b11;
   }
@@ -7819,13 +7826,13 @@
   }
 
   def d : BaseSIMDScalarShift<U, opc, {1,?,?,?,?,?,?},
-                              FPR64, FPR64, vecshiftR16, asm, []> {
+                              FPR64, FPR64, vecshiftR64, asm, []> {
     let Inst{21-16} = imm{5-0};
   }
 
   let Predicates = [HasNEON, HasFullFP16] in {
   def h : BaseSIMDScalarShift<U, opc, {0,0,1,?,?,?,?},
-                              FPR16, FPR32, vecshiftR16, asm, []> {
+                              FPR16, FPR16, vecshiftR16, asm, []> {
     let Inst{19-16} = imm{3-0};
   }
   } // Predicates = [HasNEON, HasFullFP16]
Index: lib/Target/AArch64/AArch64InstrInfo.td
===================================================================
--- lib/Target/AArch64/AArch64InstrInfo.td
+++ lib/Target/AArch64/AArch64InstrInfo.td
@@ -4888,15 +4888,15 @@
                                             vecshiftR64:$imm)),
           (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>;
 def : Pat<(f16 (int_aarch64_neon_vcvtfxs2fp (i64 FPR64:$Rn), vecshiftR16:$imm)),
-          (FCVTZSHDr (i64 FPR64:$Rn), vecshiftR16:$imm)>;
+          (FCVTZSHDr (i64 FPR64:$Rn), vecshiftR32:$imm)>;
 def : Pat<(i32 (int_aarch64_neon_vcvtfp2fxu FPR16:$Rn, vecshiftR32:$imm)),
           (FCVTZUSHr FPR16:$Rn, vecshiftR32:$imm)>;
 def : Pat<(i32 (int_aarch64_neon_vcvtfp2fxs FPR16:$Rn, vecshiftR32:$imm)),
           (FCVTZSSHr FPR16:$Rn, vecshiftR32:$imm)>;
 def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxs (f16 FPR16:$Rn), vecshiftR64:$imm)),
           (FCVTZSDHr (f16 FPR16:$Rn), vecshiftR64:$imm)>;
-def : Pat<(f16 (int_aarch64_neon_vcvtfxu2fp FPR32:$Rn, vecshiftR16:$imm)),       
-          (UCVTFh FPR32:$Rn, vecshiftR16:$imm)>;
+def : Pat<(f16 (int_aarch64_neon_vcvtfxu2fp FPR32:$Rn, vecshiftR16:$imm)),
+          (UCVTFHSr FPR32:$Rn, vecshiftR16:$imm)>;
 def : Pat<(int_aarch64_neon_vcvtfxu2fp FPR32:$Rn, vecshiftR32:$imm),
           (UCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
 def : Pat<(f64 (int_aarch64_neon_vcvtfxu2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
@@ -4905,9 +4905,9 @@
                                             vecshiftR64:$imm)),
           (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
 def : Pat<(f16 (int_aarch64_neon_vcvtfxs2fp (i32 FPR32:$Rn), vecshiftR16:$imm)),
-          (SCVTFh FPR32:$Rn, vecshiftR16:$imm)>;
+          (SCVTFHSr FPR32:$Rn, vecshiftR16:$imm)>;
 def : Pat<(f16 (int_aarch64_neon_vcvtfxs2fp FPR32:$Rn, vecshiftR16:$imm)),
-          (SCVTFh FPR32:$Rn, vecshiftR16:$imm)>;
+          (SCVTFHSr FPR32:$Rn, vecshiftR16:$imm)>;
 def : Pat<(f64 (int_aarch64_neon_vcvtfxs2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
           (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
 def : Pat<(v1f64 (int_aarch64_neon_vcvtfxu2fp (v1i64 FPR64:$Rn),