Index: lib/Target/AMDGPU/AMDGPURegisterInfo.h =================================================================== --- lib/Target/AMDGPU/AMDGPURegisterInfo.h +++ lib/Target/AMDGPU/AMDGPURegisterInfo.h @@ -31,7 +31,7 @@ /// \returns the sub reg enum value for the given \p Channel /// (e.g. getSubRegFromChannel(0) -> AMDGPU::sub0) - unsigned getSubRegFromChannel(unsigned Channel) const; + static unsigned getSubRegFromChannel(unsigned Channel); void reserveRegisterTuples(BitVector &, unsigned Reg) const; }; Index: lib/Target/AMDGPU/AMDGPURegisterInfo.cpp =================================================================== --- lib/Target/AMDGPU/AMDGPURegisterInfo.cpp +++ lib/Target/AMDGPU/AMDGPURegisterInfo.cpp @@ -27,7 +27,7 @@ // they are not supported at this time. //===----------------------------------------------------------------------===// -unsigned AMDGPURegisterInfo::getSubRegFromChannel(unsigned Channel) const { +unsigned AMDGPURegisterInfo::getSubRegFromChannel(unsigned Channel) { static const unsigned SubRegs[] = { AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, AMDGPU::sub8, AMDGPU::sub9, Index: lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp =================================================================== --- lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp +++ lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp @@ -309,7 +309,7 @@ DstMI = Reg; else DstMI = TRI->getMatchingSuperReg(Reg, - TRI->getSubRegFromChannel(TRI->getHWRegChan(Reg)), + AMDGPURegisterInfo::getSubRegFromChannel(TRI->getHWRegChan(Reg)), &AMDGPU::R600_Reg128RegClass); } if (MO.isUse()) { @@ -318,7 +318,7 @@ SrcMI = Reg; else SrcMI = TRI->getMatchingSuperReg(Reg, - TRI->getSubRegFromChannel(TRI->getHWRegChan(Reg)), + AMDGPURegisterInfo::getSubRegFromChannel(TRI->getHWRegChan(Reg)), &AMDGPU::R600_Reg128RegClass); } } Index: lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp =================================================================== --- lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp +++ lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp @@ -219,13 +219,13 @@ } } if (IsReduction) { - unsigned SubRegIndex = TRI.getSubRegFromChannel(Chan); + unsigned SubRegIndex = AMDGPURegisterInfo::getSubRegFromChannel(Chan); Src0 = TRI.getSubReg(Src0, SubRegIndex); Src1 = TRI.getSubReg(Src1, SubRegIndex); } else if (IsCube) { static const int CubeSrcSwz[] = {2, 2, 0, 1}; - unsigned SubRegIndex0 = TRI.getSubRegFromChannel(CubeSrcSwz[Chan]); - unsigned SubRegIndex1 = TRI.getSubRegFromChannel(CubeSrcSwz[3 - Chan]); + unsigned SubRegIndex0 = AMDGPURegisterInfo::getSubRegFromChannel(CubeSrcSwz[Chan]); + unsigned SubRegIndex1 = AMDGPURegisterInfo::getSubRegFromChannel(CubeSrcSwz[3 - Chan]); Src1 = TRI.getSubReg(Src0, SubRegIndex1); Src0 = TRI.getSubReg(Src0, SubRegIndex0); } @@ -234,7 +234,7 @@ bool Mask = false; bool NotLast = true; if (IsCube) { - unsigned SubRegIndex = TRI.getSubRegFromChannel(Chan); + unsigned SubRegIndex = AMDGPURegisterInfo::getSubRegFromChannel(Chan); DstReg = TRI.getSubReg(DstReg, SubRegIndex); } else { // Mask the write if the original instruction does not write to Index: lib/Target/AMDGPU/R600InstrInfo.cpp =================================================================== --- lib/Target/AMDGPU/R600InstrInfo.cpp +++ lib/Target/AMDGPU/R600InstrInfo.cpp @@ -73,7 +73,7 @@ if (VectorComponents > 0) { for (unsigned I = 0; I < VectorComponents; I++) { - unsigned SubRegIndex = RI.getSubRegFromChannel(I); + unsigned SubRegIndex = AMDGPURegisterInfo::getSubRegFromChannel(I); buildDefaultInstruction(MBB, MI, AMDGPU::MOV, RI.getSubReg(DestReg, SubRegIndex), RI.getSubReg(SrcReg, SubRegIndex))