Index: llvm/trunk/lib/Target/AMDGPU/AMDGPU.h =================================================================== --- llvm/trunk/lib/Target/AMDGPU/AMDGPU.h +++ llvm/trunk/lib/Target/AMDGPU/AMDGPU.h @@ -11,7 +11,6 @@ #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H #define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H -#include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "llvm/Target/TargetMachine.h" namespace llvm { Index: llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp +++ llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp @@ -21,6 +21,7 @@ #include "AMDGPUSubtarget.h" #include "AMDGPUTargetMachine.h" #include "InstPrinter/AMDGPUInstPrinter.h" +#include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "MCTargetDesc/AMDGPUTargetStreamer.h" #include "R600Defines.h" #include "R600MachineFunctionInfo.h" Index: llvm/trunk/lib/Target/AMDGPU/AMDGPUCallLowering.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/AMDGPUCallLowering.cpp +++ llvm/trunk/lib/Target/AMDGPU/AMDGPUCallLowering.cpp @@ -20,6 +20,7 @@ #include "SIISelLowering.h" #include "SIMachineFunctionInfo.h" #include "SIRegisterInfo.h" +#include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "llvm/CodeGen/CallingConvLower.h" #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h" #include "llvm/CodeGen/MachineInstrBuilder.h" Index: llvm/trunk/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp +++ llvm/trunk/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp @@ -24,6 +24,7 @@ #include "SIInstrInfo.h" #include "SIMachineFunctionInfo.h" #include "SIRegisterInfo.h" +#include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "llvm/ADT/APInt.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringRef.h" Index: llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp +++ llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp @@ -29,6 +29,7 @@ #include "R600MachineFunctionInfo.h" #include "SIInstrInfo.h" #include "SIMachineFunctionInfo.h" +#include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "llvm/CodeGen/CallingConvLower.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineRegisterInfo.h" Index: llvm/trunk/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp +++ llvm/trunk/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp @@ -16,6 +16,7 @@ #include "AMDGPUInstrInfo.h" #include "AMDGPURegisterInfo.h" #include "AMDGPUTargetMachine.h" +#include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" Index: llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp +++ llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp @@ -18,6 +18,7 @@ #include "AMDGPURegisterInfo.h" #include "AMDGPUSubtarget.h" #include "AMDGPUTargetMachine.h" +#include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "llvm/CodeGen/GlobalISel/InstructionSelector.h" #include "llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h" #include "llvm/CodeGen/GlobalISel/Utils.h" Index: llvm/trunk/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp +++ llvm/trunk/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp @@ -18,6 +18,7 @@ #include "AMDGPUSubtarget.h" #include "AMDGPUTargetMachine.h" #include "InstPrinter/AMDGPUInstPrinter.h" +#include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "SIInstrInfo.h" #include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineInstr.h" Index: llvm/trunk/lib/Target/AMDGPU/AMDGPUMacroFusion.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/AMDGPUMacroFusion.cpp +++ llvm/trunk/lib/Target/AMDGPU/AMDGPUMacroFusion.cpp @@ -15,6 +15,7 @@ #include "AMDGPUMacroFusion.h" #include "AMDGPUSubtarget.h" #include "SIInstrInfo.h" +#include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "llvm/CodeGen/MacroFusion.h" Index: llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp +++ llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp @@ -14,7 +14,9 @@ #include "AMDGPURegisterBankInfo.h" #include "AMDGPUInstrInfo.h" +#include "SIMachineFunctionInfo.h" #include "SIRegisterInfo.h" +#include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "llvm/CodeGen/GlobalISel/RegisterBank.h" #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h" #include "llvm/CodeGen/TargetRegisterInfo.h" Index: llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterInfo.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterInfo.cpp +++ llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterInfo.cpp @@ -14,7 +14,9 @@ #include "AMDGPURegisterInfo.h" #include "AMDGPUTargetMachine.h" +#include "SIMachineFunctionInfo.h" #include "SIRegisterInfo.h" +#include "MCTargetDesc/AMDGPUMCTargetDesc.h" using namespace llvm; Index: llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h =================================================================== --- llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h +++ llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h @@ -23,7 +23,6 @@ #include "SIFrameLowering.h" #include "SIISelLowering.h" #include "SIInstrInfo.h" -#include "SIMachineFunctionInfo.h" #include "Utils/AMDGPUBaseInfo.h" #include "llvm/ADT/Triple.h" #include "llvm/CodeGen/GlobalISel/InstructionSelector.h" @@ -383,10 +382,7 @@ /// the given LDS memory size is the only constraint. unsigned getOccupancyWithLocalMemSize(uint32_t Bytes, const Function &) const; - unsigned getOccupancyWithLocalMemSize(const MachineFunction &MF) const { - const auto *MFI = MF.getInfo(); - return getOccupancyWithLocalMemSize(MFI->getLDSSize(), MF.getFunction()); - } + unsigned getOccupancyWithLocalMemSize(const MachineFunction &MF) const; bool hasFP16Denormals() const { return FP64FP16Denormals; Index: llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp +++ llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp @@ -20,6 +20,7 @@ #include "AMDGPULegalizerInfo.h" #include "AMDGPURegisterBankInfo.h" #include "SIMachineFunctionInfo.h" +#include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "llvm/ADT/SmallString.h" #include "llvm/CodeGen/MachineScheduler.h" #include "llvm/IR/MDBuilder.h" @@ -205,6 +206,12 @@ return NumWaves; } +unsigned +AMDGPUSubtarget::getOccupancyWithLocalMemSize(const MachineFunction &MF) const { + const auto *MFI = MF.getInfo(); + return getOccupancyWithLocalMemSize(MFI->getLDSSize(), MF.getFunction()); +} + std::pair AMDGPUSubtarget::getDefaultFlatWorkGroupSize(CallingConv::ID CC) const { switch (CC) { Index: llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h =================================================================== --- llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h +++ llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h @@ -21,6 +21,7 @@ #include "AMDGPU.h" #include "AMDGPUSubtarget.h" #include "AMDGPUTargetMachine.h" +#include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "Utils/AMDGPUBaseInfo.h" #include "llvm/ADT/ArrayRef.h" #include "llvm/Analysis/TargetTransformInfo.h" Index: llvm/trunk/lib/Target/AMDGPU/AMDILCFGStructurizer.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/AMDILCFGStructurizer.cpp +++ llvm/trunk/lib/Target/AMDGPU/AMDILCFGStructurizer.cpp @@ -11,6 +11,7 @@ #include "AMDGPUSubtarget.h" #include "R600InstrInfo.h" #include "R600RegisterInfo.h" +#include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "llvm/ADT/DepthFirstIterator.h" #include "llvm/ADT/SCCIterator.h" #include "llvm/ADT/SmallPtrSet.h" Index: llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp +++ llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp @@ -21,6 +21,7 @@ #include "AMDGPU.h" #include "AMDGPURegisterInfo.h" #include "SIDefines.h" +#include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "Utils/AMDGPUBaseInfo.h" #include "llvm-c/Disassembler.h" #include "llvm/ADT/APInt.h" Index: llvm/trunk/lib/Target/AMDGPU/GCNHazardRecognizer.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/GCNHazardRecognizer.cpp +++ llvm/trunk/lib/Target/AMDGPU/GCNHazardRecognizer.cpp @@ -16,6 +16,7 @@ #include "SIDefines.h" #include "SIInstrInfo.h" #include "SIRegisterInfo.h" +#include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "Utils/AMDGPUBaseInfo.h" #include "llvm/ADT/iterator_range.h" #include "llvm/CodeGen/MachineFunction.h" Index: llvm/trunk/lib/Target/AMDGPU/GCNIterativeScheduler.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/GCNIterativeScheduler.cpp +++ llvm/trunk/lib/Target/AMDGPU/GCNIterativeScheduler.cpp @@ -11,6 +11,7 @@ #include "AMDGPUSubtarget.h" #include "GCNRegPressure.h" #include "GCNSchedStrategy.h" +#include "SIMachineFunctionInfo.h" #include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/SmallVector.h" Index: llvm/trunk/lib/Target/AMDGPU/R600ClauseMergePass.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/R600ClauseMergePass.cpp +++ llvm/trunk/lib/Target/AMDGPU/R600ClauseMergePass.cpp @@ -19,6 +19,7 @@ #include "R600InstrInfo.h" #include "R600MachineFunctionInfo.h" #include "R600RegisterInfo.h" +#include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" Index: llvm/trunk/lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp +++ llvm/trunk/lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp @@ -19,6 +19,7 @@ #include "R600InstrInfo.h" #include "R600MachineFunctionInfo.h" #include "R600RegisterInfo.h" +#include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringRef.h" Index: llvm/trunk/lib/Target/AMDGPU/R600EmitClauseMarkers.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/R600EmitClauseMarkers.cpp +++ llvm/trunk/lib/Target/AMDGPU/R600EmitClauseMarkers.cpp @@ -19,6 +19,7 @@ #include "R600Defines.h" #include "R600InstrInfo.h" #include "R600RegisterInfo.h" +#include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringRef.h" #include "llvm/CodeGen/MachineBasicBlock.h" Index: llvm/trunk/lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp +++ llvm/trunk/lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp @@ -21,6 +21,7 @@ #include "R600RegisterInfo.h" #include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineFunction.h" +#include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineInstrBuilder.h" Index: llvm/trunk/lib/Target/AMDGPU/R600ISelLowering.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/R600ISelLowering.cpp +++ llvm/trunk/lib/Target/AMDGPU/R600ISelLowering.cpp @@ -20,6 +20,7 @@ #include "R600FrameLowering.h" #include "R600InstrInfo.h" #include "R600MachineFunctionInfo.h" +#include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "Utils/AMDGPUBaseInfo.h" #include "llvm/ADT/APFloat.h" #include "llvm/ADT/APInt.h" Index: llvm/trunk/lib/Target/AMDGPU/R600InstrInfo.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/R600InstrInfo.cpp +++ llvm/trunk/lib/Target/AMDGPU/R600InstrInfo.cpp @@ -19,6 +19,7 @@ #include "R600Defines.h" #include "R600FrameLowering.h" #include "R600RegisterInfo.h" +#include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "Utils/AMDGPUBaseInfo.h" #include "llvm/ADT/BitVector.h" #include "llvm/ADT/SmallSet.h" Index: llvm/trunk/lib/Target/AMDGPU/R600MachineScheduler.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/R600MachineScheduler.cpp +++ llvm/trunk/lib/Target/AMDGPU/R600MachineScheduler.cpp @@ -15,6 +15,7 @@ #include "R600MachineScheduler.h" #include "AMDGPUSubtarget.h" #include "R600InstrInfo.h" +#include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/IR/LegacyPassManager.h" #include "llvm/Pass.h" Index: llvm/trunk/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp +++ llvm/trunk/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp @@ -31,6 +31,7 @@ #include "AMDGPUSubtarget.h" #include "R600Defines.h" #include "R600InstrInfo.h" +#include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/StringRef.h" Index: llvm/trunk/lib/Target/AMDGPU/R600Packetizer.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/R600Packetizer.cpp +++ llvm/trunk/lib/Target/AMDGPU/R600Packetizer.cpp @@ -17,6 +17,7 @@ #include "AMDGPU.h" #include "AMDGPUSubtarget.h" #include "R600InstrInfo.h" +#include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "llvm/CodeGen/DFAPacketizer.h" #include "llvm/CodeGen/MachineDominators.h" #include "llvm/CodeGen/MachineFunctionPass.h" Index: llvm/trunk/lib/Target/AMDGPU/R600RegisterInfo.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/R600RegisterInfo.cpp +++ llvm/trunk/lib/Target/AMDGPU/R600RegisterInfo.cpp @@ -17,6 +17,7 @@ #include "R600Defines.h" #include "R600InstrInfo.h" #include "R600MachineFunctionInfo.h" +#include "MCTargetDesc/AMDGPUMCTargetDesc.h" using namespace llvm; Index: llvm/trunk/lib/Target/AMDGPU/SIDebuggerInsertNops.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/SIDebuggerInsertNops.cpp +++ llvm/trunk/lib/Target/AMDGPU/SIDebuggerInsertNops.cpp @@ -21,6 +21,7 @@ #include "AMDGPUSubtarget.h" #include "SIInstrInfo.h" +#include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "llvm/ADT/DenseSet.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFunctionPass.h" Index: llvm/trunk/lib/Target/AMDGPU/SIFixSGPRCopies.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/SIFixSGPRCopies.cpp +++ llvm/trunk/lib/Target/AMDGPU/SIFixSGPRCopies.cpp @@ -69,6 +69,7 @@ #include "AMDGPUSubtarget.h" #include "SIInstrInfo.h" #include "SIRegisterInfo.h" +#include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "llvm/ADT/DenseSet.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/SmallSet.h" Index: llvm/trunk/lib/Target/AMDGPU/SIFixVGPRCopies.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/SIFixVGPRCopies.cpp +++ llvm/trunk/lib/Target/AMDGPU/SIFixVGPRCopies.cpp @@ -15,6 +15,7 @@ #include "AMDGPU.h" #include "AMDGPUSubtarget.h" #include "SIInstrInfo.h" +#include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "llvm/CodeGen/MachineFunctionPass.h" using namespace llvm; Index: llvm/trunk/lib/Target/AMDGPU/SIFixWWMLiveness.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/SIFixWWMLiveness.cpp +++ llvm/trunk/lib/Target/AMDGPU/SIFixWWMLiveness.cpp @@ -55,6 +55,7 @@ #include "AMDGPUSubtarget.h" #include "SIInstrInfo.h" #include "SIRegisterInfo.h" +#include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "llvm/ADT/DepthFirstIterator.h" #include "llvm/ADT/SparseBitVector.h" #include "llvm/CodeGen/LiveIntervals.h" Index: llvm/trunk/lib/Target/AMDGPU/SIFoldOperands.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/SIFoldOperands.cpp +++ llvm/trunk/lib/Target/AMDGPU/SIFoldOperands.cpp @@ -13,6 +13,7 @@ #include "AMDGPUSubtarget.h" #include "SIInstrInfo.h" #include "SIMachineFunctionInfo.h" +#include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "llvm/ADT/DepthFirstIterator.h" #include "llvm/CodeGen/LiveIntervals.h" #include "llvm/CodeGen/MachineFunctionPass.h" Index: llvm/trunk/lib/Target/AMDGPU/SIFrameLowering.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/SIFrameLowering.cpp +++ llvm/trunk/lib/Target/AMDGPU/SIFrameLowering.cpp @@ -12,6 +12,7 @@ #include "SIInstrInfo.h" #include "SIMachineFunctionInfo.h" #include "SIRegisterInfo.h" +#include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "llvm/CodeGen/LivePhysRegs.h" #include "llvm/CodeGen/MachineFrameInfo.h" Index: llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp +++ llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp @@ -26,6 +26,7 @@ #include "SIInstrInfo.h" #include "SIMachineFunctionInfo.h" #include "SIRegisterInfo.h" +#include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "Utils/AMDGPUBaseInfo.h" #include "llvm/ADT/APFloat.h" #include "llvm/ADT/APInt.h" Index: llvm/trunk/lib/Target/AMDGPU/SIInsertSkips.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/SIInsertSkips.cpp +++ llvm/trunk/lib/Target/AMDGPU/SIInsertSkips.cpp @@ -18,6 +18,7 @@ #include "AMDGPUSubtarget.h" #include "SIInstrInfo.h" #include "SIMachineFunctionInfo.h" +#include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringRef.h" #include "llvm/CodeGen/MachineBasicBlock.h" Index: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h =================================================================== --- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h +++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h @@ -419,18 +419,7 @@ return get(Opcode).TSFlags & SIInstrFlags::SMRD; } - bool isBufferSMRD(const MachineInstr &MI) const { - if (!isSMRD(MI)) - return false; - - // Check that it is using a buffer resource. - int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sbase); - if (Idx == -1) // e.g. s_memtime - return false; - - const auto RCID = MI.getDesc().OpInfo[Idx].RegClass; - return RCID == AMDGPU::SReg_128RegClassID; - } + bool isBufferSMRD(const MachineInstr &MI) const; static bool isDS(const MachineInstr &MI) { return MI.getDesc().TSFlags & SIInstrFlags::DS; Index: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp +++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -19,6 +19,7 @@ #include "SIDefines.h" #include "SIMachineFunctionInfo.h" #include "SIRegisterInfo.h" +#include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "Utils/AMDGPUBaseInfo.h" #include "llvm/ADT/APInt.h" #include "llvm/ADT/ArrayRef.h" @@ -4918,3 +4919,16 @@ llvm_unreachable("invalid opcode, expected SI_KILL_*_PSEUDO"); } } + +bool SIInstrInfo::isBufferSMRD(const MachineInstr &MI) const { + if (!isSMRD(MI)) + return false; + + // Check that it is using a buffer resource. + int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sbase); + if (Idx == -1) // e.g. s_memtime + return false; + + const auto RCID = MI.getDesc().OpInfo[Idx].RegClass; + return RCID == AMDGPU::SReg_128RegClassID; +} Index: llvm/trunk/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp +++ llvm/trunk/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp @@ -45,6 +45,7 @@ #include "AMDGPUSubtarget.h" #include "SIInstrInfo.h" #include "SIRegisterInfo.h" +#include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "Utils/AMDGPUBaseInfo.h" #include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/SmallVector.h" Index: llvm/trunk/lib/Target/AMDGPU/SILowerControlFlow.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/SILowerControlFlow.cpp +++ llvm/trunk/lib/Target/AMDGPU/SILowerControlFlow.cpp @@ -51,6 +51,7 @@ #include "AMDGPU.h" #include "AMDGPUSubtarget.h" #include "SIInstrInfo.h" +#include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringRef.h" #include "llvm/CodeGen/LiveIntervals.h" Index: llvm/trunk/lib/Target/AMDGPU/SILowerI1Copies.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/SILowerI1Copies.cpp +++ llvm/trunk/lib/Target/AMDGPU/SILowerI1Copies.cpp @@ -17,6 +17,7 @@ #include "AMDGPU.h" #include "AMDGPUSubtarget.h" #include "SIInstrInfo.h" +#include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "Utils/AMDGPULaneDominator.h" #include "llvm/CodeGen/LiveIntervals.h" #include "llvm/CodeGen/MachineFunctionPass.h" Index: llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.h =================================================================== --- llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.h +++ llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.h @@ -16,7 +16,9 @@ #include "AMDGPUArgumentUsageInfo.h" #include "AMDGPUMachineFunction.h" +#include "SIInstrInfo.h" #include "SIRegisterInfo.h" +#include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/Optional.h" @@ -34,7 +36,6 @@ class MachineFrameInfo; class MachineFunction; -class SIInstrInfo; class TargetRegisterClass; class AMDGPUImagePseudoSourceValue : public PseudoSourceValue { @@ -185,25 +186,20 @@ unsigned HighBitsOf32BitAddress; - MCPhysReg getNextUserSGPR() const { - assert(NumSystemSGPRs == 0 && "System SGPRs must be added after user SGPRs"); - return AMDGPU::SGPR0 + NumUserSGPRs; - } + MCPhysReg getNextUserSGPR() const; - MCPhysReg getNextSystemSGPR() const { - return AMDGPU::SGPR0 + NumUserSGPRs + NumSystemSGPRs; - } + MCPhysReg getNextSystemSGPR() const; public: struct SpilledReg { - unsigned VGPR = AMDGPU::NoRegister; + unsigned VGPR = 0; int Lane = -1; SpilledReg() = default; SpilledReg(unsigned R, int L) : VGPR (R), Lane (L) {} bool hasLane() { return Lane != -1;} - bool hasReg() { return VGPR != AMDGPU::NoRegister;} + bool hasReg() { return VGPR != 0;} }; struct SGPRSpillVGPRCSR { @@ -243,8 +239,8 @@ bool allocateSGPRSpillToVGPR(MachineFunction &MF, int FI); void removeSGPRToVGPRFrameIndices(MachineFrameInfo &MFI); - bool hasCalculatedTID() const { return TIDReg != AMDGPU::NoRegister; } - unsigned getTIDReg() const { return TIDReg; } + bool hasCalculatedTID() const { return TIDReg != 0; }; + unsigned getTIDReg() const { return TIDReg; }; void setTIDReg(unsigned Reg) { TIDReg = Reg; } unsigned getBytesInStackArgArea() const { @@ -433,7 +429,7 @@ } void setScratchRSrcReg(unsigned Reg) { - assert(Reg != AMDGPU::NoRegister && "Should never be unset"); + assert(Reg != 0 && "Should never be unset"); ScratchRSrcReg = Reg; } @@ -446,6 +442,7 @@ } void setStackPtrOffsetReg(unsigned Reg) { + assert(Reg != 0 && "Should never be unset"); StackPtrOffsetReg = Reg; } @@ -458,7 +455,7 @@ } void setScratchWaveOffsetReg(unsigned Reg) { - assert(Reg != AMDGPU::NoRegister && "Should never be unset"); + assert(Reg != 0 && "Should never be unset"); ScratchWaveOffsetReg = Reg; if (isEntryFunction()) FrameOffsetReg = ScratchWaveOffsetReg; @@ -621,20 +618,7 @@ } /// \returns VGPR used for \p Dim' work item ID. - unsigned getWorkItemIDVGPR(unsigned Dim) const { - switch (Dim) { - case 0: - assert(hasWorkItemIDX()); - return AMDGPU::VGPR0; - case 1: - assert(hasWorkItemIDY()); - return AMDGPU::VGPR1; - case 2: - assert(hasWorkItemIDZ()); - return AMDGPU::VGPR2; - } - llvm_unreachable("unexpected dimension"); - } + unsigned getWorkItemIDVGPR(unsigned Dim) const; unsigned getLDSWaveSpillSize() const { return LDSWaveSpillSize; Index: llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp +++ llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp @@ -11,6 +11,7 @@ #include "AMDGPUArgumentUsageInfo.h" #include "AMDGPUSubtarget.h" #include "SIRegisterInfo.h" +#include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "Utils/AMDGPUBaseInfo.h" #include "llvm/ADT/Optional.h" #include "llvm/CodeGen/MachineBasicBlock.h" @@ -298,3 +299,29 @@ for (auto &R : SGPRToVGPRSpills) MFI.RemoveStackObject(R.first); } + + +/// \returns VGPR used for \p Dim' work item ID. +unsigned SIMachineFunctionInfo::getWorkItemIDVGPR(unsigned Dim) const { + switch (Dim) { + case 0: + assert(hasWorkItemIDX()); + return AMDGPU::VGPR0; + case 1: + assert(hasWorkItemIDY()); + return AMDGPU::VGPR1; + case 2: + assert(hasWorkItemIDZ()); + return AMDGPU::VGPR2; + } + llvm_unreachable("unexpected dimension"); +} + +MCPhysReg SIMachineFunctionInfo::getNextUserSGPR() const { + assert(NumSystemSGPRs == 0 && "System SGPRs must be added after user SGPRs"); + return AMDGPU::SGPR0 + NumUserSGPRs; +} + +MCPhysReg SIMachineFunctionInfo::getNextSystemSGPR() const { + return AMDGPU::SGPR0 + NumUserSGPRs + NumSystemSGPRs; +} Index: llvm/trunk/lib/Target/AMDGPU/SIMachineScheduler.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/SIMachineScheduler.cpp +++ llvm/trunk/lib/Target/AMDGPU/SIMachineScheduler.cpp @@ -16,6 +16,7 @@ #include "AMDGPU.h" #include "SIInstrInfo.h" #include "SIRegisterInfo.h" +#include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/SmallVector.h" #include "llvm/CodeGen/LiveInterval.h" Index: llvm/trunk/lib/Target/AMDGPU/SIMemoryLegalizer.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/SIMemoryLegalizer.cpp +++ llvm/trunk/lib/Target/AMDGPU/SIMemoryLegalizer.cpp @@ -19,6 +19,7 @@ #include "AMDGPUSubtarget.h" #include "SIDefines.h" #include "SIInstrInfo.h" +#include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "Utils/AMDGPUBaseInfo.h" #include "llvm/ADT/None.h" #include "llvm/ADT/Optional.h" Index: llvm/trunk/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp +++ llvm/trunk/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp @@ -10,6 +10,7 @@ #include "AMDGPU.h" #include "AMDGPUSubtarget.h" #include "SIInstrInfo.h" +#include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "llvm/ADT/SmallSet.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstrBuilder.h" Index: llvm/trunk/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp +++ llvm/trunk/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp @@ -23,6 +23,7 @@ #include "AMDGPU.h" #include "AMDGPUSubtarget.h" #include "SIInstrInfo.h" +#include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "llvm/CodeGen/LiveIntervals.h" #include "llvm/CodeGen/MachineFunctionPass.h" Index: llvm/trunk/lib/Target/AMDGPU/SIPeepholeSDWA.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/SIPeepholeSDWA.cpp +++ llvm/trunk/lib/Target/AMDGPU/SIPeepholeSDWA.cpp @@ -25,6 +25,7 @@ #include "SIDefines.h" #include "SIInstrInfo.h" #include "SIRegisterInfo.h" +#include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "Utils/AMDGPUBaseInfo.h" #include "llvm/ADT/None.h" #include "llvm/ADT/Optional.h" Index: llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.h =================================================================== --- llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.h +++ llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.h @@ -16,7 +16,6 @@ #define LLVM_LIB_TARGET_AMDGPU_SIREGISTERINFO_H #include "AMDGPURegisterInfo.h" -#include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "SIDefines.h" #include "llvm/CodeGen/MachineRegisterInfo.h" @@ -223,10 +222,8 @@ const int *getRegUnitPressureSets(unsigned RegUnit) const override; - unsigned getReturnAddressReg(const MachineFunction &MF) const { - // Not a callee saved register. - return AMDGPU::SGPR30_SGPR31; - } + unsigned getReturnAddressReg(const MachineFunction &MF) const; + const TargetRegisterClass * getConstrainedRegClassForOperand(const MachineOperand &MO, const MachineRegisterInfo &MRI) const override; Index: llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -17,6 +17,7 @@ #include "AMDGPUSubtarget.h" #include "SIInstrInfo.h" #include "SIMachineFunctionInfo.h" +#include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/RegisterScavenging.h" @@ -1564,6 +1565,11 @@ return AMDGPURegisterInfo::getRegUnitPressureSets(RegUnit); } +unsigned SIRegisterInfo::getReturnAddressReg(const MachineFunction &MF) const { + // Not a callee saved register. + return AMDGPU::SGPR30_SGPR31; +} + const TargetRegisterClass * SIRegisterInfo::getConstrainedRegClassForOperand(const MachineOperand &MO, const MachineRegisterInfo &MRI) const { Index: llvm/trunk/lib/Target/AMDGPU/SIShrinkInstructions.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/SIShrinkInstructions.cpp +++ llvm/trunk/lib/Target/AMDGPU/SIShrinkInstructions.cpp @@ -13,6 +13,7 @@ #include "AMDGPUMCInstLower.h" #include "AMDGPUSubtarget.h" #include "SIInstrInfo.h" +#include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "llvm/ADT/Statistic.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstrBuilder.h" Index: llvm/trunk/lib/Target/AMDGPU/SIWholeQuadMode.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/SIWholeQuadMode.cpp +++ llvm/trunk/lib/Target/AMDGPU/SIWholeQuadMode.cpp @@ -60,6 +60,7 @@ #include "AMDGPUSubtarget.h" #include "SIInstrInfo.h" #include "SIMachineFunctionInfo.h" +#include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/PostOrderIterator.h" #include "llvm/ADT/SmallVector.h"