Index: llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td =================================================================== --- llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -263,6 +263,52 @@ defm ST1W_D : sve_mem_cst_ss<0b1011, "st1w", Z_d, ZPR64, GPR64NoXZRshifted32>; defm ST1D : sve_mem_cst_ss<0b1111, "st1d", Z_d, ZPR64, GPR64NoXZRshifted64>; + // Scatters using unscaled 32-bit offsets, e.g. + // st1h z0.s, p0, [x0, z0.s, uxtw] + // and unpacked: + // st1h z0.d, p0, [x0, z0.d, uxtw] + defm SST1B_D : sve_mem_sst_sv_32_unscaled<0b000, "st1b", Z_d, ZPR64, ZPR64ExtSXTW8Only, ZPR64ExtUXTW8Only>; + defm SST1B_S : sve_mem_sst_sv_32_unscaled<0b001, "st1b", Z_s, ZPR32, ZPR32ExtSXTW8Only, ZPR32ExtUXTW8Only>; + defm SST1H_D : sve_mem_sst_sv_32_unscaled<0b010, "st1h", Z_d, ZPR64, ZPR64ExtSXTW8, ZPR64ExtUXTW8>; + defm SST1H_S : sve_mem_sst_sv_32_unscaled<0b011, "st1h", Z_s, ZPR32, ZPR32ExtSXTW8, ZPR32ExtUXTW8>; + defm SST1W_D : sve_mem_sst_sv_32_unscaled<0b100, "st1w", Z_d, ZPR64, ZPR64ExtSXTW8, ZPR64ExtUXTW8>; + defm SST1W : sve_mem_sst_sv_32_unscaled<0b101, "st1w", Z_s, ZPR32, ZPR32ExtSXTW8, ZPR32ExtUXTW8>; + defm SST1D : sve_mem_sst_sv_32_unscaled<0b110, "st1d", Z_d, ZPR64, ZPR64ExtSXTW8, ZPR64ExtUXTW8>; + + // Scatters using scaled 32-bit offsets, e.g. + // st1h z0.s, p0, [x0, z0.s, uxtw #1] + // and unpacked: + // st1h z0.d, p0, [x0, z0.d, uxtw #1] + defm SST1H_D : sve_mem_sst_sv_32_scaled<0b010, "st1h", Z_d, ZPR64, ZPR64ExtSXTW16, ZPR64ExtUXTW16>; + defm SST1H_S : sve_mem_sst_sv_32_scaled<0b011, "st1h", Z_s, ZPR32, ZPR32ExtSXTW16, ZPR32ExtUXTW16>; + defm SST1W_D : sve_mem_sst_sv_32_scaled<0b100, "st1w", Z_d, ZPR64, ZPR64ExtSXTW32, ZPR64ExtUXTW32>; + defm SST1W : sve_mem_sst_sv_32_scaled<0b101, "st1w", Z_s, ZPR32, ZPR32ExtSXTW32, ZPR32ExtUXTW32>; + defm SST1D : sve_mem_sst_sv_32_scaled<0b110, "st1d", Z_d, ZPR64, ZPR64ExtSXTW64, ZPR64ExtUXTW64>; + + // Scatters using 32/64-bit pointers with offset, e.g. + // st1h z0.s, p0, [z0.s, #16] + // st1h z0.d, p0, [z0.d, #16] + defm SST1B_D : sve_mem_sst_vi_ptrs<0b000, "st1b", Z_d, ZPR64, imm0_31>; + defm SST1B_S : sve_mem_sst_vi_ptrs<0b001, "st1b", Z_s, ZPR32, imm0_31>; + defm SST1H_D : sve_mem_sst_vi_ptrs<0b010, "st1h", Z_d, ZPR64, uimm5s2>; + defm SST1H_S : sve_mem_sst_vi_ptrs<0b011, "st1h", Z_s, ZPR32, uimm5s2>; + defm SST1W_D : sve_mem_sst_vi_ptrs<0b100, "st1w", Z_d, ZPR64, uimm5s4>; + defm SST1W : sve_mem_sst_vi_ptrs<0b101, "st1w", Z_s, ZPR32, uimm5s4>; + defm SST1D : sve_mem_sst_vi_ptrs<0b110, "st1d", Z_d, ZPR64, uimm5s8>; + + // Scatters using unscaled 64-bit offsets, e.g. + // st1h z0.d, p0, [x0, z0.d] + defm SST1B_D : sve_mem_sst_sv_64_unscaled<0b00, "st1b">; + defm SST1H_D : sve_mem_sst_sv_64_unscaled<0b01, "st1h">; + defm SST1W_D : sve_mem_sst_sv_64_unscaled<0b10, "st1w">; + defm SST1D : sve_mem_sst_sv_64_unscaled<0b11, "st1d">; + + // Scatters using scaled 64-bit offsets, e.g. + // st1h z0.d, p0, [x0, z0.d, lsl #1] + defm SST1H_D_SCALED : sve_mem_sst_sv_64_scaled<0b01, "st1h", ZPR64ExtLSL16>; + defm SST1W_D_SCALED : sve_mem_sst_sv_64_scaled<0b10, "st1w", ZPR64ExtLSL32>; + defm SST1D_SCALED : sve_mem_sst_sv_64_scaled<0b11, "st1d", ZPR64ExtLSL64>; + // ST{2,3,4}{B,H,W,D} with immediate defm ST2B_IMM : sve_mem_est_si<0b00, 0b01, ZZ_b, "st2b", simm4s2>; defm ST3B_IMM : sve_mem_est_si<0b00, 0b10, ZZZ_b, "st3b", simm4s3>; Index: llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td =================================================================== --- llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td +++ llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td @@ -653,6 +653,132 @@ (!cast(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>; } +class sve_mem_sst_sv opc, bit xs, bit scaled, string asm, + RegisterOperand VecList, RegisterOperand zprext> +: I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm), + asm, "\t$Zt, $Pg, [$Rn, $Zm]", + "", + []>, Sched<[]> { + bits<3> Pg; + bits<5> Rn; + bits<5> Zm; + bits<5> Zt; + let Inst{31-25} = 0b1110010; + let Inst{24-22} = opc; + let Inst{21} = scaled; + let Inst{20-16} = Zm; + let Inst{15} = 0b1; + let Inst{14} = xs; + let Inst{13} = 0; + let Inst{12-10} = Pg; + let Inst{9-5} = Rn; + let Inst{4-0} = Zt; + + let mayStore = 1; +} + +multiclass sve_mem_sst_sv_32_scaled opc, string asm, + RegisterOperand listty, + ZPRRegOp zprty, + RegisterOperand sxtw_opnd, + RegisterOperand uxtw_opnd > { + def _UXTW_SCALED : sve_mem_sst_sv; + def _SXTW_SCALED : sve_mem_sst_sv; + + def : InstAlias(NAME # _UXTW_SCALED) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>; + def : InstAlias(NAME # _SXTW_SCALED) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>; +} + +multiclass sve_mem_sst_sv_32_unscaled opc, string asm, + RegisterOperand listty, + ZPRRegOp zprty, + RegisterOperand sxtw_opnd, + RegisterOperand uxtw_opnd> { + def _UXTW : sve_mem_sst_sv; + def _SXTW : sve_mem_sst_sv; + + def : InstAlias(NAME # _UXTW) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>; + def : InstAlias(NAME # _SXTW) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>; +} + +class sve_mem_sst_sv2 msz, bit scaled, string asm, + RegisterOperand zprext> +: I<(outs), (ins Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm), + asm, "\t$Zt, $Pg, [$Rn, $Zm]", + "", + []>, Sched<[]> { + bits<3> Pg; + bits<5> Rn; + bits<5> Zm; + bits<5> Zt; + let Inst{31-25} = 0b1110010; + let Inst{24-23} = msz; + let Inst{22} = 0b0; + let Inst{21} = scaled; + let Inst{20-16} = Zm; + let Inst{15-13} = 0b101; + let Inst{12-10} = Pg; + let Inst{9-5} = Rn; + let Inst{4-0} = Zt; + + let mayStore = 1; +} + +multiclass sve_mem_sst_sv_64_scaled msz, string asm, + RegisterOperand zprext> { + def "" : sve_mem_sst_sv2; + + def : InstAlias(NAME) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm), 0>; + +} + +multiclass sve_mem_sst_sv_64_unscaled msz, string asm> { + def "" : sve_mem_sst_sv2; + + def : InstAlias(NAME) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, ZPR64ExtLSL8:$Zm), 0>; +} + +class sve_mem_sst_vi opc, string asm, ZPRRegOp zprty, + RegisterOperand VecList, Operand imm_ty> +: I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, zprty:$Zn, imm_ty:$imm5), + asm, "\t$Zt, $Pg, [$Zn, $imm5]", + "", + []>, Sched<[]> { + bits<3> Pg; + bits<5> imm5; + bits<5> Zn; + bits<5> Zt; + let Inst{31-25} = 0b1110010; + let Inst{24-23} = opc{2-1}; + let Inst{22} = 0b1; + let Inst{21} = opc{0}; + let Inst{20-16} = imm5; + let Inst{15-13} = 0b101; + let Inst{12-10} = Pg; + let Inst{9-5} = Zn; + let Inst{4-0} = Zt; + + let mayStore = 1; +} + +multiclass sve_mem_sst_vi_ptrs opc, string asm, RegisterOperand listty, + ZPRRegOp zprty, Operand imm_ty> { + def _IMM : sve_mem_sst_vi; + + def : InstAlias(NAME # _IMM) zprty:$Zt, PPR3bAny:$Pg, zprty:$Zn, 0), 0>; + def : InstAlias(NAME # _IMM) zprty:$Zt, PPR3bAny:$Pg, zprty:$Zn, imm_ty:$imm5), 0>; + def : InstAlias(NAME # _IMM) listty:$Zt, PPR3bAny:$Pg, zprty:$Zn, 0), 1>; +} + //===----------------------------------------------------------------------===// // SVE Permute - Predicates Group //===----------------------------------------------------------------------===// Index: llvm/trunk/test/MC/AArch64/SVE/st1b-diagnostics.s =================================================================== --- llvm/trunk/test/MC/AArch64/SVE/st1b-diagnostics.s +++ llvm/trunk/test/MC/AArch64/SVE/st1b-diagnostics.s @@ -107,3 +107,71 @@ // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift // CHECK-NEXT: st1b z0.b, p0, [x0, w0, uxtw] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid scalar + vector addressing modes + +st1b z0.d, p0, [x0, z0.b] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK-NEXT: st1b z0.d, p0, [x0, z0.b] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1b z0.d, p0, [x0, z0.h] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK-NEXT: st1b z0.d, p0, [x0, z0.h] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1b z0.d, p0, [x0, z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK-NEXT: st1b z0.d, p0, [x0, z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1b z0.s, p0, [x0, z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)' +// CHECK-NEXT: st1b z0.s, p0, [x0, z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1b z0.s, p0, [x0, z0.s, uxtw #1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)' +// CHECK-NEXT: st1b z0.s, p0, [x0, z0.s, uxtw #1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1b z0.s, p0, [x0, z0.s, lsl #0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)' +// CHECK-NEXT: st1b z0.s, p0, [x0, z0.s, lsl #0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1b z0.d, p0, [x0, z0.d, lsl #1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK-NEXT: st1b z0.d, p0, [x0, z0.d, lsl #1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1b z0.d, p0, [x0, z0.d, sxtw #1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK-NEXT: st1b z0.d, p0, [x0, z0.d, sxtw #1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid vector + immediate addressing modes + +st1b z0.s, p0, [z0.s, #-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]. +// CHECK-NEXT: st1b z0.s, p0, [z0.s, #-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1b z0.s, p0, [z0.s, #32] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]. +// CHECK-NEXT: st1b z0.s, p0, [z0.s, #32] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1b z0.d, p0, [z0.d, #-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]. +// CHECK-NEXT: st1b z0.d, p0, [z0.d, #-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1b z0.d, p0, [z0.d, #32] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]. +// CHECK-NEXT: st1b z0.d, p0, [z0.d, #32] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/trunk/test/MC/AArch64/SVE/st1b.s =================================================================== --- llvm/trunk/test/MC/AArch64/SVE/st1b.s +++ llvm/trunk/test/MC/AArch64/SVE/st1b.s @@ -126,3 +126,45 @@ // CHECK-ENCODING: [0x00,0x40,0x60,0xe4] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 00 40 60 e4 + +st1b { z0.s }, p0, [x0, z0.s, uxtw] +// CHECK-INST: st1b { z0.s }, p0, [x0, z0.s, uxtw] +// CHECK-ENCODING: [0x00,0x80,0x40,0xe4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 80 40 e4 + +st1b { z0.s }, p0, [x0, z0.s, sxtw] +// CHECK-INST: st1b { z0.s }, p0, [x0, z0.s, sxtw] +// CHECK-ENCODING: [0x00,0xc0,0x40,0xe4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c0 40 e4 + +st1b { z0.d }, p0, [x0, z0.d, uxtw] +// CHECK-INST: st1b { z0.d }, p0, [x0, z0.d, uxtw] +// CHECK-ENCODING: [0x00,0x80,0x00,0xe4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 80 00 e4 + +st1b { z0.d }, p0, [x0, z0.d, sxtw] +// CHECK-INST: st1b { z0.d }, p0, [x0, z0.d, sxtw] +// CHECK-ENCODING: [0x00,0xc0,0x00,0xe4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c0 00 e4 + +st1b { z0.d }, p0, [x0, z0.d] +// CHECK-INST: st1b { z0.d }, p0, [x0, z0.d] +// CHECK-ENCODING: [0x00,0xa0,0x00,0xe4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 a0 00 e4 + +st1b { z31.s }, p7, [z31.s, #31] +// CHECK-INST: st1b { z31.s }, p7, [z31.s, #31] +// CHECK-ENCODING: [0xff,0xbf,0x7f,0xe4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff bf 7f e4 + +st1b { z31.d }, p7, [z31.d, #31] +// CHECK-INST: st1b { z31.d }, p7, [z31.d, #31] +// CHECK-ENCODING: [0xff,0xbf,0x5f,0xe4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff bf 5f e4 Index: llvm/trunk/test/MC/AArch64/SVE/st1d-diagnostics.s =================================================================== --- llvm/trunk/test/MC/AArch64/SVE/st1d-diagnostics.s +++ llvm/trunk/test/MC/AArch64/SVE/st1d-diagnostics.s @@ -68,3 +68,66 @@ // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' // CHECK-NEXT: st1d z0.d, p0, [x0, w0, uxtw] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid scalar + vector addressing modes + +st1d z0.d, p0, [x0, z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK-NEXT: st1d z0.d, p0, [x0, z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1d z0.d, p0, [x0, z0.d, uxtw #2] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #3' +// CHECK-NEXT: st1d z0.d, p0, [x0, z0.d, uxtw #2] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1d z0.d, p0, [x0, z0.d, lsl #2] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #3' +// CHECK-NEXT: st1d z0.d, p0, [x0, z0.d, lsl #2] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1d z0.d, p0, [x0, z0.d, lsl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected #imm after shift specifier +// CHECK-NEXT: st1d z0.d, p0, [x0, z0.d, lsl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid vector + immediate addressing modes + +st1d z0.s, p0, [z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: st1d z0.s, p0, [z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1d z0.s, p0, [z0.s, #8] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: st1d z0.s, p0, [z0.s, #8] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1d z0.d, p0, [z0.d, #-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248]. +// CHECK-NEXT: st1d z0.d, p0, [z0.d, #-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1d z0.d, p0, [z0.d, #-8] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248]. +// CHECK-NEXT: st1d z0.d, p0, [z0.d, #-8] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1d z0.d, p0, [z0.d, #249] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248]. +// CHECK-NEXT: st1d z0.d, p0, [z0.d, #249] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1d z0.d, p0, [z0.d, #256] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248]. +// CHECK-NEXT: st1d z0.d, p0, [z0.d, #256] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1d z0.d, p0, [z0.d, #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248]. +// CHECK-NEXT: st1d z0.d, p0, [z0.d, #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/trunk/test/MC/AArch64/SVE/st1d.s =================================================================== --- llvm/trunk/test/MC/AArch64/SVE/st1d.s +++ llvm/trunk/test/MC/AArch64/SVE/st1d.s @@ -36,3 +36,45 @@ // CHECK-ENCODING: [0x00,0x40,0xe0,0xe5] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 00 40 e0 e5 + +st1d { z0.d }, p0, [x0, z0.d, uxtw] +// CHECK-INST: st1d { z0.d }, p0, [x0, z0.d, uxtw] +// CHECK-ENCODING: [0x00,0x80,0x80,0xe5] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 80 80 e5 + +st1d { z0.d }, p0, [x0, z0.d, sxtw] +// CHECK-INST: st1d { z0.d }, p0, [x0, z0.d, sxtw] +// CHECK-ENCODING: [0x00,0xc0,0x80,0xe5] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c0 80 e5 + +st1d { z0.d }, p0, [x0, z0.d, uxtw #3] +// CHECK-INST: st1d { z0.d }, p0, [x0, z0.d, uxtw #3] +// CHECK-ENCODING: [0x00,0x80,0xa0,0xe5] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 80 a0 e5 + +st1d { z0.d }, p0, [x0, z0.d, sxtw #3] +// CHECK-INST: st1d { z0.d }, p0, [x0, z0.d, sxtw #3] +// CHECK-ENCODING: [0x00,0xc0,0xa0,0xe5] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c0 a0 e5 + +st1d { z0.d }, p0, [x0, z0.d] +// CHECK-INST: st1d { z0.d }, p0, [x0, z0.d] +// CHECK-ENCODING: [0x00,0xa0,0x80,0xe5] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 a0 80 e5 + +st1d { z0.d }, p0, [x0, z0.d, lsl #3] +// CHECK-INST: st1d { z0.d }, p0, [x0, z0.d, lsl #3] +// CHECK-ENCODING: [0x00,0xa0,0xa0,0xe5] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 a0 a0 e5 + +st1d { z31.d }, p7, [z31.d, #248] +// CHECK-INST: st1d { z31.d }, p7, [z31.d, #248] +// CHECK-ENCODING: [0xff,0xbf,0xdf,0xe5] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff bf df e5 Index: llvm/trunk/test/MC/AArch64/SVE/st1h-diagnostics.s =================================================================== --- llvm/trunk/test/MC/AArch64/SVE/st1h-diagnostics.s +++ llvm/trunk/test/MC/AArch64/SVE/st1h-diagnostics.s @@ -97,3 +97,95 @@ // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' // CHECK-NEXT: st1h z0.h, p0, [x0, w0, uxtw] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid scalar + vector addressing modes + +st1h z0.d, p0, [x0, z0.h] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK-NEXT: st1h z0.d, p0, [x0, z0.h] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1h z0.d, p0, [x0, z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK-NEXT: st1h z0.d, p0, [x0, z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1h z0.s, p0, [x0, z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)' +// CHECK-NEXT: st1h z0.s, p0, [x0, z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1h z0.s, p0, [x0, z0.s, uxtw #2] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #1' +// CHECK-NEXT: st1h z0.s, p0, [x0, z0.s, uxtw #2] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1h z0.s, p0, [x0, z0.s, lsl #1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #1' +// CHECK-NEXT: st1h z0.s, p0, [x0, z0.s, lsl #1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1h z0.d, p0, [x0, z0.d, lsl #2] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1' +// CHECK-NEXT: st1h z0.d, p0, [x0, z0.d, lsl #2] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1h z0.d, p0, [x0, z0.d, sxtw #2] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1' +// CHECK-NEXT: st1h z0.d, p0, [x0, z0.d, sxtw #2] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid vector + immediate addressing modes + +st1h z0.s, p0, [z0.s, #-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62]. +// CHECK-NEXT: st1h z0.s, p0, [z0.s, #-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1h z0.s, p0, [z0.s, #-2] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62]. +// CHECK-NEXT: st1h z0.s, p0, [z0.s, #-2] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1h z0.s, p0, [z0.s, #63] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62]. +// CHECK-NEXT: st1h z0.s, p0, [z0.s, #63] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1h z0.s, p0, [z0.s, #64] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62]. +// CHECK-NEXT: st1h z0.s, p0, [z0.s, #64] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1h z0.s, p0, [z0.s, #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62]. +// CHECK-NEXT: st1h z0.s, p0, [z0.s, #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1h z0.d, p0, [z0.d, #-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62]. +// CHECK-NEXT: st1h z0.d, p0, [z0.d, #-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1h z0.d, p0, [z0.d, #-2] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62]. +// CHECK-NEXT: st1h z0.d, p0, [z0.d, #-2] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1h z0.d, p0, [z0.d, #63] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62]. +// CHECK-NEXT: st1h z0.d, p0, [z0.d, #63] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1h z0.d, p0, [z0.d, #64] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62]. +// CHECK-NEXT: st1h z0.d, p0, [z0.d, #64] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1h z0.d, p0, [z0.d, #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62]. +// CHECK-NEXT: st1h z0.d, p0, [z0.d, #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/trunk/test/MC/AArch64/SVE/st1h.s =================================================================== --- llvm/trunk/test/MC/AArch64/SVE/st1h.s +++ llvm/trunk/test/MC/AArch64/SVE/st1h.s @@ -96,3 +96,75 @@ // CHECK-ENCODING: [0x00,0x40,0xe0,0xe4] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 00 40 e0 e4 + +st1h { z0.s }, p0, [x0, z0.s, uxtw] +// CHECK-INST: st1h { z0.s }, p0, [x0, z0.s, uxtw] +// CHECK-ENCODING: [0x00,0x80,0xc0,0xe4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 80 c0 e4 + +st1h { z0.s }, p0, [x0, z0.s, sxtw] +// CHECK-INST: st1h { z0.s }, p0, [x0, z0.s, sxtw] +// CHECK-ENCODING: [0x00,0xc0,0xc0,0xe4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c0 c0 e4 + +st1h { z0.d }, p0, [x0, z0.d, uxtw] +// CHECK-INST: st1h { z0.d }, p0, [x0, z0.d, uxtw] +// CHECK-ENCODING: [0x00,0x80,0x80,0xe4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 80 80 e4 + +st1h { z0.d }, p0, [x0, z0.d, sxtw] +// CHECK-INST: st1h { z0.d }, p0, [x0, z0.d, sxtw] +// CHECK-ENCODING: [0x00,0xc0,0x80,0xe4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c0 80 e4 + +st1h { z0.s }, p0, [x0, z0.s, uxtw #1] +// CHECK-INST: st1h { z0.s }, p0, [x0, z0.s, uxtw #1] +// CHECK-ENCODING: [0x00,0x80,0xe0,0xe4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 80 e0 e4 + +st1h { z0.s }, p0, [x0, z0.s, sxtw #1] +// CHECK-INST: st1h { z0.s }, p0, [x0, z0.s, sxtw #1] +// CHECK-ENCODING: [0x00,0xc0,0xe0,0xe4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c0 e0 e4 + +st1h { z0.d }, p0, [x0, z0.d, uxtw #1] +// CHECK-INST: st1h { z0.d }, p0, [x0, z0.d, uxtw #1] +// CHECK-ENCODING: [0x00,0x80,0xa0,0xe4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 80 a0 e4 + +st1h { z0.d }, p0, [x0, z0.d, sxtw #1] +// CHECK-INST: st1h { z0.d }, p0, [x0, z0.d, sxtw #1] +// CHECK-ENCODING: [0x00,0xc0,0xa0,0xe4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c0 a0 e4 + +st1h { z0.d }, p0, [x0, z0.d] +// CHECK-INST: st1h { z0.d }, p0, [x0, z0.d] +// CHECK-ENCODING: [0x00,0xa0,0x80,0xe4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 a0 80 e4 + +st1h { z0.d }, p0, [x0, z0.d, lsl #1] +// CHECK-INST: st1h { z0.d }, p0, [x0, z0.d, lsl #1] +// CHECK-ENCODING: [0x00,0xa0,0xa0,0xe4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 a0 a0 e4 + +st1h { z31.s }, p7, [z31.s, #62] +// CHECK-INST: st1h { z31.s }, p7, [z31.s, #62] +// CHECK-ENCODING: [0xff,0xbf,0xff,0xe4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff bf ff e4 + +st1h { z31.d }, p7, [z31.d, #62] +// CHECK-INST: st1h { z31.d }, p7, [z31.d, #62] +// CHECK-ENCODING: [0xff,0xbf,0xdf,0xe4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff bf df e4 Index: llvm/trunk/test/MC/AArch64/SVE/st1w-diagnostics.s =================================================================== --- llvm/trunk/test/MC/AArch64/SVE/st1w-diagnostics.s +++ llvm/trunk/test/MC/AArch64/SVE/st1w-diagnostics.s @@ -85,3 +85,96 @@ // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' // CHECK-NEXT: st1w z0.s, p0, [x0, w0, uxtw] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid scalar + vector addressing modes + +st1w z0.d, p0, [x0, z0.h] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK-NEXT: st1w z0.d, p0, [x0, z0.h] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1w z0.d, p0, [x0, z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)' +// CHECK-NEXT: st1w z0.d, p0, [x0, z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1w z0.s, p0, [x0, z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)' +// CHECK-NEXT: st1w z0.s, p0, [x0, z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1w z0.s, p0, [x0, z0.s, uxtw #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #2' +// CHECK-NEXT: st1w z0.s, p0, [x0, z0.s, uxtw #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1w z0.s, p0, [x0, z0.s, lsl #2] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #2' +// CHECK-NEXT: st1w z0.s, p0, [x0, z0.s, lsl #2] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1w z0.d, p0, [x0, z0.d, lsl #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2' +// CHECK-NEXT: st1w z0.d, p0, [x0, z0.d, lsl #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1w z0.d, p0, [x0, z0.d, sxtw #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2' +// CHECK-NEXT: st1w z0.d, p0, [x0, z0.d, sxtw #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid vector + immediate addressing modes + +st1w z0.s, p0, [z0.s, #-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124]. +// CHECK-NEXT: st1w z0.s, p0, [z0.s, #-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1w z0.s, p0, [z0.s, #-4] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124]. +// CHECK-NEXT: st1w z0.s, p0, [z0.s, #-4] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1w z0.s, p0, [z0.s, #125] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124]. +// CHECK-NEXT: st1w z0.s, p0, [z0.s, #125] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1w z0.s, p0, [z0.s, #128] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124]. +// CHECK-NEXT: st1w z0.s, p0, [z0.s, #128] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1w z0.s, p0, [z0.s, #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124]. +// CHECK-NEXT: st1w z0.s, p0, [z0.s, #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1w z0.d, p0, [z0.d, #-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124]. +// CHECK-NEXT: st1w z0.d, p0, [z0.d, #-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1w z0.d, p0, [z0.d, #-4] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124]. +// CHECK-NEXT: st1w z0.d, p0, [z0.d, #-4] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1w z0.d, p0, [z0.d, #125] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124]. +// CHECK-NEXT: st1w z0.d, p0, [z0.d, #125] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1w z0.d, p0, [z0.d, #128] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124]. +// CHECK-NEXT: st1w z0.d, p0, [z0.d, #128] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1w z0.d, p0, [z0.d, #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124]. +// CHECK-NEXT: st1w z0.d, p0, [z0.d, #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/trunk/test/MC/AArch64/SVE/st1w.s =================================================================== --- llvm/trunk/test/MC/AArch64/SVE/st1w.s +++ llvm/trunk/test/MC/AArch64/SVE/st1w.s @@ -66,3 +66,75 @@ // CHECK-ENCODING: [0x00,0x40,0x60,0xe5] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 00 40 60 e5 + +st1w { z0.s }, p0, [x0, z0.s, uxtw] +// CHECK-INST: st1w { z0.s }, p0, [x0, z0.s, uxtw] +// CHECK-ENCODING: [0x00,0x80,0x40,0xe5] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 80 40 e5 + +st1w { z0.s }, p0, [x0, z0.s, sxtw] +// CHECK-INST: st1w { z0.s }, p0, [x0, z0.s, sxtw] +// CHECK-ENCODING: [0x00,0xc0,0x40,0xe5] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c0 40 e5 + +st1w { z0.d }, p0, [x0, z0.d, uxtw] +// CHECK-INST: st1w { z0.d }, p0, [x0, z0.d, uxtw] +// CHECK-ENCODING: [0x00,0x80,0x00,0xe5] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 80 00 e5 + +st1w { z0.d }, p0, [x0, z0.d, sxtw] +// CHECK-INST: st1w { z0.d }, p0, [x0, z0.d, sxtw] +// CHECK-ENCODING: [0x00,0xc0,0x00,0xe5] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c0 00 e5 + +st1w { z0.s }, p0, [x0, z0.s, uxtw #2] +// CHECK-INST: st1w { z0.s }, p0, [x0, z0.s, uxtw #2] +// CHECK-ENCODING: [0x00,0x80,0x60,0xe5] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 80 60 e5 + +st1w { z0.s }, p0, [x0, z0.s, sxtw #2] +// CHECK-INST: st1w { z0.s }, p0, [x0, z0.s, sxtw #2] +// CHECK-ENCODING: [0x00,0xc0,0x60,0xe5] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c0 60 e5 + +st1w { z0.d }, p0, [x0, z0.d, uxtw #2] +// CHECK-INST: st1w { z0.d }, p0, [x0, z0.d, uxtw #2] +// CHECK-ENCODING: [0x00,0x80,0x20,0xe5] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 80 20 e5 + +st1w { z0.d }, p0, [x0, z0.d, sxtw #2] +// CHECK-INST: st1w { z0.d }, p0, [x0, z0.d, sxtw #2] +// CHECK-ENCODING: [0x00,0xc0,0x20,0xe5] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 c0 20 e5 + +st1w { z0.d }, p0, [x0, z0.d] +// CHECK-INST: st1w { z0.d }, p0, [x0, z0.d] +// CHECK-ENCODING: [0x00,0xa0,0x00,0xe5] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 a0 00 e5 + +st1w { z0.d }, p0, [x0, z0.d, lsl #2] +// CHECK-INST: st1w { z0.d }, p0, [x0, z0.d, lsl #2] +// CHECK-ENCODING: [0x00,0xa0,0x20,0xe5] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 a0 20 e5 + +st1w { z31.s }, p7, [z31.s, #124] +// CHECK-INST: st1w { z31.s }, p7, [z31.s, #124] +// CHECK-ENCODING: [0xff,0xbf,0x7f,0xe5] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff bf 7f e5 + +st1w { z31.d }, p7, [z31.d, #124] +// CHECK-INST: st1w { z31.d }, p7, [z31.d, #124] +// CHECK-ENCODING: [0xff,0xbf,0x5f,0xe5] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff bf 5f e5