Index: include/llvm/CodeGen/PostRASchedulerList.h
===================================================================
--- include/llvm/CodeGen/PostRASchedulerList.h
+++ include/llvm/CodeGen/PostRASchedulerList.h
@@ -1,4 +1,23 @@
-/**/
+//===- PostRaSchedulerList.h - Post RA Scheduling Pass --------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file provides an interface for customizing the standard
+// PostRaSchedulerList pass. Note that the entire pass may be replaced as
+// follows:
+//
+// <Target>TargetMachine::createPassConfig(PassManagerBase &PM) {
+//   PM.substitutePass(&PostRaSchedulerListID, &CustomSchedulerPassID);
+//   ...}
+//
+// This implements a top-down list scheduler, using standard algorithms.
+//
+//===----------------------------------------------------------------------===//
 
 #include "llvm/Analysis/AliasAnalysis.h"
 #include "llvm/CodeGen/LatencyPriorityQueue.h"
@@ -11,51 +30,35 @@
 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
 #include "llvm/CodeGen/SchedulerRegistry.h"
-#include "llvm/CodeGen/TargetInstrInfo.h"
-#include "llvm/CodeGen/TargetLowering.h"
-#include "llvm/CodeGen/TargetPassConfig.h"
-#include "llvm/CodeGen/TargetRegisterInfo.h"
-#include "llvm/CodeGen/TargetSubtargetInfo.h"
 
-#ifndef LLVM_CODEGEN_PostRASchedulerList_H
-#define LLVM_CODEGEN_PostRASchedulerList_H
+#ifndef LLVM_CODEGEN_POSTRASCHEDULERLIST_H
+#define LLVM_CODEGEN_POSTRASCHEDULERLIST_H
 
 namespace llvm {
-	
-  class PostRAScheduler : public MachineFunctionPass {
-    const TargetInstrInfo *TII;
-    RegisterClassInfo RegClassInfo;
-
-  public:
-    static char ID;
-    PostRAScheduler() : MachineFunctionPass(ID) {}
-
-    void getAnalysisUsage(AnalysisUsage &AU) const override {
-      AU.setPreservesCFG();
-      AU.addRequired<AAResultsWrapperPass>();
-      AU.addRequired<TargetPassConfig>();
-      AU.addRequired<MachineDominatorTree>();
-      AU.addPreserved<MachineDominatorTree>();
-      AU.addRequired<MachineLoopInfo>();
-      AU.addPreserved<MachineLoopInfo>();
-      MachineFunctionPass::getAnalysisUsage(AU);
-    }
-
-    MachineFunctionProperties getRequiredProperties() const override {
-      return MachineFunctionProperties().set(
-          MachineFunctionProperties::Property::NoVRegs);
-    }
-
-    bool runOnMachineFunction(MachineFunction &Fn) override;
-
-  private:
-    bool enablePostRAScheduler(
-        const TargetSubtargetInfo &ST, CodeGenOpt::Level OptLevel,
-        TargetSubtargetInfo::AntiDepBreakMode &Mode,
-        TargetSubtargetInfo::RegClassVector &CriticalPathRCs) const;
-  };
-  
-  
+
+class PostRAScheduler : public MachineFunctionPass {
+  const TargetInstrInfo *TII;
+  RegisterClassInfo RegClassInfo;
+
+public:
+  static char ID;
+
+  PostRAScheduler() : MachineFunctionPass(ID) {}
+
+  void getAnalysisUsage(AnalysisUsage &AU) const override;
+
+  MachineFunctionProperties getRequiredProperties() const override;
+
+  bool runOnMachineFunction(MachineFunction &Fn) override;
+
+private:
+  bool enablePostRAScheduler(
+      const TargetSubtargetInfo &ST, CodeGenOpt::Level OptLevel,
+      TargetSubtargetInfo::AntiDepBreakMode &Mode,
+      TargetSubtargetInfo::RegClassVector &CriticalPathRCs) const;
+};
+char PostRAScheduler::ID = 0;
+
 } // end namespace llvm
 
-#endif // LLVM_CODEGEN_PostRASchedulerList_H
\ No newline at end of file
+#endif // LLVM_CODEGEN_POSTRASCHEDULERLIST_H
Index: lib/CodeGen/PostRASchedulerList.cpp
===================================================================
--- lib/CodeGen/PostRASchedulerList.cpp
+++ lib/CodeGen/PostRASchedulerList.cpp
@@ -232,9 +232,24 @@
 }
 #endif
 
+MachineFunctionProperties PostRAScheduler::getRequiredProperties() const {
+  return MachineFunctionProperties().set(
+      MachineFunctionProperties::Property::NoVRegs);
+}
+
+void PostRAScheduler::getAnalysisUsage(AnalysisUsage &AU) const {
+  AU.setPreservesCFG();
+  AU.addRequired<AAResultsWrapperPass>();
+  AU.addRequired<TargetPassConfig>();
+  AU.addRequired<MachineDominatorTree>();
+  AU.addPreserved<MachineDominatorTree>();
+  AU.addRequired<MachineLoopInfo>();
+  AU.addPreserved<MachineLoopInfo>();
+  MachineFunctionPass::getAnalysisUsage(AU);
+}
+
 bool PostRAScheduler::enablePostRAScheduler(
-    const TargetSubtargetInfo &ST,
-    CodeGenOpt::Level OptLevel,
+    const TargetSubtargetInfo &ST, CodeGenOpt::Level OptLevel,
     TargetSubtargetInfo::AntiDepBreakMode &Mode,
     TargetSubtargetInfo::RegClassVector &CriticalPathRCs) const {
   Mode = ST.getAntiDepBreakMode();