Index: lib/Target/SystemZ/SystemZFrameLowering.cpp
===================================================================
--- lib/Target/SystemZ/SystemZFrameLowering.cpp
+++ lib/Target/SystemZ/SystemZFrameLowering.cpp
@@ -97,6 +97,17 @@
   if (MFFrame.hasCalls())
     SavedRegs.set(SystemZ::R14D);
 
+  // With interprocedural register allocation, saving the CSRs may be skipped
+  // by TargetFrameLowering if it is considered safe. Make sure in that case
+  // that the FP and return registers are always restored if clobbered.
+  if (MF.getTarget().Options.EnableIPRA) {
+    const MachineRegisterInfo &MRI = MF.getRegInfo();
+    if (MRI.isPhysRegModified(SystemZ::R11D))
+      SavedRegs.set(SystemZ::R11D);
+    if (MRI.isPhysRegModified(SystemZ::R14D))
+      SavedRegs.set(SystemZ::R14D);
+  }
+
   // If we are saving GPRs other than the stack pointer, we might as well
   // save and restore the stack pointer at the same time, via STMG and LMG.
   // This allows the deallocation to be done by the LMG, rather than needing
Index: test/CodeGen/SystemZ/ipra-02.ll
===================================================================
--- /dev/null
+++ test/CodeGen/SystemZ/ipra-02.ll
@@ -0,0 +1,128 @@
+; Test that the return register is saved and restored even when the saving of
+; Callee Saved Registers is skipped with interprocedural register allocation.
+;
+; RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 -enable-ipra < %s \
+; RUN:   | FileCheck  %s
+;
+; RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 -enable-ipra \
+; RUN:   -debug-only=ip-regalloc 2>&1 < %s | FileCheck --check-prefix=DBG %s
+;
+
+; DBG: fun3 function optimized for not having CSR
+; CHECK-LABEL: fun3
+; CHECK: stmg    %r14, %r15, 112(%r15)
+; CHECK: lr      %r14
+; CHECK: a       %r14
+; CHECK: lmg     %r14, %r15, 112(%r15)
+; CHECK: br      %r14
+
+
+@board = external dso_local local_unnamed_addr global [421 x i8], align 2
+@delta = external dso_local local_unnamed_addr global [8 x i32], align 4
+
+; Function Attrs: nounwind
+define internal fastcc signext i32 @fun0(i32 signext, i32*, i32 signext, i32 signext) unnamed_addr #0 {
+  br i1 undef, label %5, label %6
+
+; <label>:5:                                      ; preds = %4
+  unreachable
+
+; <label>:6:                                      ; preds = %4
+  switch i32 undef, label %10 [
+    i32 1, label %7
+    i32 2, label %8
+    i32 3, label %9
+  ]
+
+; <label>:7:                                      ; preds = %6
+  unreachable
+
+; <label>:8:                                      ; preds = %6
+  unreachable
+
+; <label>:9:                                      ; preds = %6
+  unreachable
+
+; <label>:10:                                     ; preds = %6
+  %11 = call fastcc signext i32 @fun2(i32 signext undef, i32* nonnull undef, i32 signext %2, i32 signext %3)
+  unreachable
+}
+
+; Function Attrs: nounwind
+define dso_local signext i32 @find_defense(i32 signext, i32*) local_unnamed_addr #0 {
+  %3 = call fastcc signext i32 @fun1(i32 signext %0, i32* nonnull undef, i32 signext 0, i32 signext 0)
+  ret i32 undef
+}
+
+; Function Attrs: nounwind
+define internal fastcc signext i32 @fun1(i32 signext, i32*, i32 signext, i32 signext) unnamed_addr #0 {
+  switch i32 undef, label %8 [
+    i32 1, label %5
+    i32 2, label %7
+  ]
+
+; <label>:5:                                      ; preds = %4
+  %6 = call fastcc signext i32 @fun0(i32 signext undef, i32* null, i32 signext undef, i32 signext undef) #2
+  unreachable
+
+; <label>:7:                                      ; preds = %4
+  unreachable
+
+; <label>:8:                                      ; preds = %4
+  unreachable
+}
+
+; Function Attrs: nounwind
+define internal fastcc signext i32 @fun2(i32 signext, i32*, i32 signext, i32 signext) unnamed_addr #0 {
+  %5 = call fastcc signext i32 @fun3(i32 signext %0, i32 signext undef, i32* nonnull undef)
+  unreachable
+}
+
+; Function Attrs: norecurse nounwind
+define internal fastcc signext i32 @fun3(i32 signext, i32 signext, i32* nocapture) unnamed_addr #1 {
+  %4 = load i8, i8* undef, align 1
+  %5 = getelementptr inbounds [8 x i32], [8 x i32]* @delta, i64 0, i64 0
+  %6 = load i32, i32* %5, align 4
+  %7 = load i32, i32* undef, align 4
+  %8 = add nsw i32 %6, %1
+  br label %9
+
+; <label>:9:                                      ; preds = %3
+  %10 = load i8, i8* undef, align 1
+  %11 = icmp eq i8 %10, 0
+  br i1 %11, label %12, label %15
+
+; <label>:12:                                     ; preds = %9
+  %13 = icmp eq i8 undef, %4
+  %14 = or i1 undef, %13
+  br label %17
+
+; <label>:15:                                     ; preds = %9
+  %16 = sub nsw i32 0, %7
+  br label %17
+
+; <label>:17:                                     ; preds = %15, %12
+  %18 = phi i32 [ %16, %15 ], [ %7, %12 ]
+  br label %19
+
+; <label>:19:                                     ; preds = %17
+  %20 = shl nsw i32 %18, 1
+  %21 = add nsw i32 %20, %8
+  %22 = sext i32 %21 to i64
+  %23 = getelementptr inbounds [421 x i8], [421 x i8]* @board, i64 0, i64 %22
+  %24 = load i8, i8* %23, align 1
+  %25 = icmp eq i8 %24, 3
+  br i1 %25, label %28, label %26
+
+; <label>:26:                                     ; preds = %19
+  %27 = add nsw i32 %18, %1
+  store i32 %27, i32* %2, align 4
+  unreachable
+
+; <label>:28:                                     ; preds = %19
+  ret i32 0
+}
+
+attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="z13" "target-features"="+transactional-execution,+vector" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { norecurse nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="z13" "target-features"="+transactional-execution,+vector" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #2 = { nounwind }
Index: test/CodeGen/SystemZ/ipra-03.ll
===================================================================
--- /dev/null
+++ test/CodeGen/SystemZ/ipra-03.ll
@@ -0,0 +1,89 @@
+; Test that the DP (%r11) register is saved and restored even when the saving of
+; Callee Saved Registers is skipped with interprocedural register allocation.
+;
+; RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 -enable-ipra < %s \
+; RUN:   | FileCheck  %s
+;
+; RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 -enable-ipra \
+; RUN:   -debug-only=ip-regalloc 2>&1 < %s | FileCheck --check-prefix=DBG %s
+;
+
+; DBG: fun0 function optimized for not having CSR
+; CHECK-LABEL: fun0
+; CHECK: stmg    %r11, %r15
+; CHECK: llc     %r11
+; CHECK: lmg     %r11, %r15
+; CHECK: br      %r14
+
+%0 = type { i32, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, %1*, %0*, i32, i32, i64, i16, i8, [1 x i8], i8*, i64, i8*, i8*, i8*, i8*, i64, i32, [20 x i8] }
+%1 = type { %1*, %0*, i32 }
+%2 = type { %3*, i32, i32, i32, i32*, i32*, i32*, i32, i32*, i8*, i16*, i8*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [256 x i8], [256 x i8], i32, i32, i32, i32, i32, i32, i32, i32, [258 x i32], [18002 x i8], [18002 x i8], [6 x [258 x i8]], [6 x [258 x i32]], [6 x [258 x i32]], [258 x [4 x i32]] }
+%3 = type { i8*, i32, i32, i32, i8*, i32, i32, i32, i8*, i8* (i8*, i32, i32)*, void (i8*, i8*)*, i8* }
+
+; Function Attrs: nounwind
+define dso_local void @BZ2_blockSort(%2* nocapture) local_unnamed_addr {
+  br label %2
+
+; <label>:2:                                      ; preds = %1
+  br label %3
+
+; <label>:3:                                      ; preds = %4, %2
+  br label %4
+
+; <label>:4:                                      ; preds = %3
+  br i1 undef, label %3, label %5
+
+; <label>:5:                                      ; preds = %4
+  %6 = call fastcc zeroext i8 @fun0(i32 zeroext undef, i32 zeroext undef, i8* undef, i16* undef, i32 zeroext undef, i32* nonnull undef)
+  unreachable
+}
+
+; Function Attrs: norecurse nounwind
+define internal fastcc zeroext i8 @fun0(i32 zeroext, i32 zeroext, i8* readonly, i16* nocapture readonly, i32 zeroext, i32* nocapture) unnamed_addr #4 {
+  br label %7
+
+; <label>:7:                                      ; preds = %29, %6
+  %8 = phi i32 [ undef, %6 ], [ %33, %29 ]
+  %9 = phi i32 [ undef, %6 ], [ %32, %29 ]
+  %10 = phi i32 [ undef, %6 ], [ %34, %29 ]
+  br label %11
+
+; <label>:11:                                     ; preds = %7
+  %12 = add i32 %9, 6
+  %13 = add i32 %8, 6
+  %14 = zext i32 %12 to i64
+  %15 = getelementptr inbounds i8, i8* %2, i64 %14
+  %16 = load i8, i8* %15, align 1
+  %17 = zext i32 %13 to i64
+  %18 = getelementptr inbounds i8, i8* %2, i64 %17
+  %19 = load i8, i8* %18, align 1
+  %20 = icmp eq i8 %16, %19
+  br i1 %20, label %22, label %21
+
+; <label>:21:                                     ; preds = %11
+  ret i8 undef
+
+; <label>:22:                                     ; preds = %11
+  %23 = getelementptr inbounds i16, i16* %3, i64 %14
+  %24 = load i16, i16* %23, align 2
+  %25 = getelementptr inbounds i16, i16* %3, i64 %17
+  %26 = load i16, i16* %25, align 2
+  %27 = icmp eq i16 %24, %26
+  br i1 %27, label %29, label %28
+
+; <label>:28:                                     ; preds = %22
+  unreachable
+
+; <label>:29:                                     ; preds = %22
+  %30 = add i32 %8, 8
+  %31 = select i1 undef, i32 0, i32 %4
+  %32 = sub i32 0, %31
+  %33 = sub i32 %30, 0
+  %34 = add nsw i32 %10, -8
+  store i32 0, i32* %5, align 4
+  %35 = icmp sgt i32 %10, 7
+  br label %7
+}
+
+attributes #4 = { norecurse nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="z13" "target-features"="+transactional-execution,+vector" "unsafe-fp-math"="false" "use-soft-float"="false" }
+