Index: lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
===================================================================
--- lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -916,7 +916,8 @@
     return false;
 
   // Parse first operand
-  if (parseOperand(Operands, Name == "call"))
+  bool ForceImmediate = (Name == "call" || Name == "tail");
+  if (parseOperand(Operands, ForceImmediate))
     return true;
 
   // Parse until end of statement, consuming commas between operands
Index: lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
===================================================================
--- lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
+++ lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
@@ -97,7 +97,7 @@
                                             const MCSubtargetInfo &STI) const {
   MCInst TmpInst;
   MCOperand Func = MI.getOperand(0);
-  unsigned Ra = RISCV::X1;
+  unsigned Ra = (MI.getOpcode() == RISCV::PseudoTAIL) ? RISCV::X6 : RISCV::X1;
   uint32_t Binary;
 
   assert(Func.isExpr() && "Expected expression");
@@ -128,7 +128,8 @@
   // Get byte count of instruction.
   unsigned Size = Desc.getSize();
 
-  if (MI.getOpcode() == RISCV::PseudoCALL) {
+  if (MI.getOpcode() == RISCV::PseudoCALL ||
+      MI.getOpcode() == RISCV::PseudoTAIL) {
     expandFunctionCall(MI, OS, Fixups, STI);
     MCNumEmitted += 2;
     return;
Index: lib/Target/RISCV/RISCVISelLowering.h
===================================================================
--- lib/Target/RISCV/RISCVISelLowering.h
+++ lib/Target/RISCV/RISCVISelLowering.h
@@ -28,7 +28,8 @@
   CALL,
   SELECT_CC,
   BuildPairF64,
-  SplitF64
+  SplitF64,
+  TAIL
 };
 }
 
Index: lib/Target/RISCV/RISCVISelLowering.cpp
===================================================================
--- lib/Target/RISCV/RISCVISelLowering.cpp
+++ lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1420,6 +1420,8 @@
     return "RISCVISD::BuildPairF64";
   case RISCVISD::SplitF64:
     return "RISCVISD::SplitF64";
+  case RISCVISD::TAIL:
+    return "RISCVISD::TAIL";
   }
   return nullptr;
 }
Index: lib/Target/RISCV/RISCVInstrInfo.td
===================================================================
--- lib/Target/RISCV/RISCVInstrInfo.td
+++ lib/Target/RISCV/RISCVInstrInfo.td
@@ -38,6 +38,9 @@
                           [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
 def SelectCC     : SDNode<"RISCVISD::SELECT_CC", SDT_RISCVSelectCC,
                           [SDNPInGlue]>;
+def Tail         : SDNode<"RISCVISD::TAIL", SDT_RISCVCall,
+                          [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
+                           SDNPVariadic]>;
 
 //===----------------------------------------------------------------------===//
 // Operand and SDNode transformation definitions.
@@ -657,6 +660,20 @@
 def PseudoRET : Pseudo<(outs), (ins), [(RetFlag)]>,
                 PseudoInstExpansion<(JALR X0, X1, 0)>;
 
+// PseudoTAIL is a pseudo instruction similar to PseudoCALL and will eventually
+// expand to auipc and jalr while encoding.
+// Define AsmString to print "tail" when compile with -S flag.
+let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [X2],
+    isCodeGenOnly = 0 in
+def PseudoTAIL : Pseudo<(outs), (ins bare_symbol:$dst), []> {
+  let AsmString = "tail\t$dst";
+}
+
+def : Pat<(Tail (iPTR tglobaladdr:$dst)),
+          (PseudoTAIL texternalsym:$dst)>;
+def : Pat<(Tail (iPTR texternalsym:$dst)),
+          (PseudoTAIL texternalsym:$dst)>;
+
 /// Loads
 
 multiclass LdPat<PatFrag LoadOp, RVInst Inst> {
Index: test/MC/RISCV/tail-call-invalid.s
===================================================================
--- /dev/null
+++ test/MC/RISCV/tail-call-invalid.s
@@ -0,0 +1,11 @@
+# RUN: not llvm-mc -triple riscv32 < %s 2>&1 | FileCheck %s
+
+tail 1234 # CHECK: :[[@LINE]]:6: error: operand must be a bare symbol name
+tail %pcrel_hi(1234) # CHECK: :[[@LINE]]:6: error: operand must be a bare symbol name
+tail %pcrel_lo(1234) # CHECK: :[[@LINE]]:6: error: operand must be a bare symbol name
+tail %pcrel_hi(foo) # CHECK: :[[@LINE]]:6: error: operand must be a bare symbol name
+tail %pcrel_lo(foo) # CHECK: :[[@LINE]]:6: error: operand must be a bare symbol name
+tail %hi(1234) # CHECK: :[[@LINE]]:6: error: operand must be a bare symbol name
+tail %lo(1234) # CHECK: :[[@LINE]]:6: error: operand must be a bare symbol name
+tail %hi(foo) # CHECK: :[[@LINE]]:6: error: operand must be a bare symbol name
+tail %lo(foo) # CHECK: :[[@LINE]]:6: error: operand must be a bare symbol name
Index: test/MC/RISCV/tail-call.s
===================================================================
--- /dev/null
+++ test/MC/RISCV/tail-call.s
@@ -0,0 +1,40 @@
+# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
+# RUN:   | llvm-objdump -d - | FileCheck -check-prefix=INSTR %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
+# RUN:   | llvm-readobj -r | FileCheck -check-prefix=RELOC %s
+# RUN: llvm-mc -triple riscv32 < %s -show-encoding \
+# RUN:   | FileCheck -check-prefix=FIXUP %s
+
+.long foo
+
+tail foo
+# RELOC: R_RISCV_CALL foo 0x0
+# INSTR: auipc t1, 0
+# INSTR: jalr  t1
+# FIXUP: fixup A - offset: 0, value: foo, kind:
+tail bar
+# RELOC: R_RISCV_CALL bar 0x0
+# INSTR: auipc t1, 0
+# INSTR: jalr  t1
+# FIXUP: fixup A - offset: 0, value: bar, kind:
+
+# Ensure that tail calls to functions whose names coincide with register names
+# work.
+
+tail zero
+# RELOC: R_RISCV_CALL zero 0x0
+# INSTR: auipc t1, 0
+# INSTR: jalr  t1
+# FIXUP: fixup A - offset: 0, value: zero, kind:
+
+tail f1
+# RELOC: R_RISCV_CALL f1 0x0
+# INSTR: auipc t1, 0
+# INSTR: jalr  t1
+# FIXUP: fixup A - offset: 0, value: f1, kind:
+
+tail ra
+# RELOC: R_RISCV_CALL ra 0x0
+# INSTR: auipc t1, 0
+# INSTR: jalr  t1
+# FIXUP: fixup A - offset: 0, value: ra, kind: