Index: lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
===================================================================
--- lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -916,7 +916,8 @@
     return false;
 
   // Parse first operand
-  if (parseOperand(Operands, Name == "call"))
+  bool ForceImmediate = (Name == "call" || Name == "tail");
+  if (parseOperand(Operands, ForceImmediate))
     return true;
 
   // Parse until end of statement, consuming commas between operands
Index: lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
===================================================================
--- lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
+++ lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
@@ -97,9 +97,28 @@
                                             const MCSubtargetInfo &STI) const {
   MCInst TmpInst;
   MCOperand Func = MI.getOperand(0);
-  unsigned Ra = RISCV::X1;
   uint32_t Binary;
 
+  // For an indirect tail call, emit JALR X0, 0(Reg).
+  // TODO: We had to custom lower this here since for tail calls we cannot
+  // allow JALR with any GPR; we need to restrict the register class to only
+  // caller-saved regs [x5-x7]. Hence we had to create a new regclass GPRTC
+  // which is a subclass of GPR. However, currently tablegen does not support
+  // the use of the registers of a subclass of the allowed regclass for an
+  // instruction. Once this is supported, we can replace the custom lowering
+  // here with a PseudoInstExpansion rule in RISCVInstrInfo.td.
+  if (MI.getOpcode() == RISCV::PseudoTAILIndirect) {
+    TmpInst = MCInstBuilder(RISCV::JALR)
+                .addReg(RISCV::X0)
+                .addReg(Func.getReg())
+                .addImm(0);
+    Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
+    support::endian::Writer<support::little>(OS).write(Binary);
+    return;
+  }
+
+  unsigned Ra = (MI.getOpcode() == RISCV::PseudoTAIL) ? RISCV::X6 : RISCV::X1;
+
   assert(Func.isExpr() && "Expected expression");
 
   const MCExpr *Expr = Func.getExpr();
@@ -128,9 +147,11 @@
   // Get byte count of instruction.
   unsigned Size = Desc.getSize();
 
-  if (MI.getOpcode() == RISCV::PseudoCALL) {
+  if (MI.getOpcode() == RISCV::PseudoCALL ||
+      MI.getOpcode() == RISCV::PseudoTAIL ||
+      MI.getOpcode() == RISCV::PseudoTAILIndirect) {
     expandFunctionCall(MI, OS, Fixups, STI);
-    MCNumEmitted += 2;
+    MCNumEmitted += (MI.getOpcode() == RISCV::PseudoTAILIndirect) ? 1 : 2;
     return;
   }
 
Index: test/MC/RISCV/tail-call-invalid.s
===================================================================
--- /dev/null
+++ test/MC/RISCV/tail-call-invalid.s
@@ -0,0 +1,11 @@
+# RUN: not llvm-mc -triple riscv32 < %s 2>&1 | FileCheck %s
+
+tail 1234 # CHECK: :[[@LINE]]:6: error: operand must be a bare symbol name
+tail %pcrel_hi(1234) # CHECK: :[[@LINE]]:6: error: operand must be a bare symbol name
+tail %pcrel_lo(1234) # CHECK: :[[@LINE]]:6: error: operand must be a bare symbol name
+tail %pcrel_hi(foo) # CHECK: :[[@LINE]]:6: error: operand must be a bare symbol name
+tail %pcrel_lo(foo) # CHECK: :[[@LINE]]:6: error: operand must be a bare symbol name
+tail %hi(1234) # CHECK: :[[@LINE]]:6: error: operand must be a bare symbol name
+tail %lo(1234) # CHECK: :[[@LINE]]:6: error: operand must be a bare symbol name
+tail %hi(foo) # CHECK: :[[@LINE]]:6: error: operand must be a bare symbol name
+tail %lo(foo) # CHECK: :[[@LINE]]:6: error: operand must be a bare symbol name
Index: test/MC/RISCV/tail-call.s
===================================================================
--- /dev/null
+++ test/MC/RISCV/tail-call.s
@@ -0,0 +1,40 @@
+# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
+# RUN:   | llvm-objdump -d - | FileCheck -check-prefix=INSTR %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
+# RUN:   | llvm-readobj -r | FileCheck -check-prefix=RELOC %s
+# RUN: llvm-mc -triple riscv32 < %s -show-encoding \
+# RUN:   | FileCheck -check-prefix=FIXUP %s
+
+.long foo
+
+tail foo
+# RELOC: R_RISCV_CALL foo 0x0
+# INSTR: auipc t1, 0
+# INSTR: jalr  t1
+# FIXUP: fixup A - offset: 0, value: foo, kind:
+tail bar
+# RELOC: R_RISCV_CALL bar 0x0
+# INSTR: auipc t1, 0
+# INSTR: jalr  t1
+# FIXUP: fixup A - offset: 0, value: bar, kind:
+
+# Ensure that tail calls to functions whose names coincide with register names
+# work.
+
+tail zero
+# RELOC: R_RISCV_CALL zero 0x0
+# INSTR: auipc t1, 0
+# INSTR: jalr  t1
+# FIXUP: fixup A - offset: 0, value: zero, kind:
+
+tail f1
+# RELOC: R_RISCV_CALL f1 0x0
+# INSTR: auipc t1, 0
+# INSTR: jalr  t1
+# FIXUP: fixup A - offset: 0, value: f1, kind:
+
+tail ra
+# RELOC: R_RISCV_CALL ra 0x0
+# INSTR: auipc t1, 0
+# INSTR: jalr  t1
+# FIXUP: fixup A - offset: 0, value: ra, kind: