Index: lib/Target/AMDGPU/AMDGPUGISel.td
===================================================================
--- lib/Target/AMDGPU/AMDGPUGISel.td
+++ lib/Target/AMDGPU/AMDGPUGISel.td
@@ -59,6 +59,8 @@
 defm : GISelVOP2DefaultPat <
   int_amdgcn_cvt_pkrtz, V_CVT_PKRTZ_F16_F32_e32, v2f16, f32>;
 
+defm : GISelVOP2DefaultPat <int_maxnum, V_MAX_F32_e32, f32>;
+defm : GISelVOP2DefaultPat <int_minnum, V_MIN_F32_e32, f32>;
 
 def gi_vop3mods0 :
     GIComplexOperandMatcher<s32, "selectVOP3Mods0">,
Index: lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
===================================================================
--- lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -173,6 +173,8 @@
 
   switch (IntrinsicID) {
   default: break;
+  case Intrinsic::maxnum:
+  case Intrinsic::minnum:
   case Intrinsic::amdgcn_cvt_pkrtz:
     return selectImpl(I, CoverageInfo);
   }
Index: test/CodeGen/AMDGPU/GlobalISel/inst-select-maxnum.mir
===================================================================
--- /dev/null
+++ test/CodeGen/AMDGPU/GlobalISel/inst-select-maxnum.mir
@@ -0,0 +1,44 @@
+# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
+
+--- |
+  define void @maxnum(i32 addrspace(1)* %global0) { ret void }
+
+  declare float @llvm.maxnum.f32(float, float)  #0
+
+  attributes #0 = { readnone speculatable }
+...
+---
+
+name:            maxnum
+legalized:       true
+regBankSelected: true
+
+# GCN-LABEL: name: maxnum
+body: |
+  bb.0:
+    liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr3_vgpr4
+    ; GCN: [[SGPR0:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+    ; GCN: [[VGPR0:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; GCN: [[VGPR1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+    %0:sgpr(s32) = COPY $sgpr0
+    %1:vgpr(s32) = COPY $vgpr0
+    %2:vgpr(s32) = COPY $vgpr1
+    %3:vgpr(s64) = COPY $vgpr3_vgpr4
+
+    ; maxnum vs
+    ; GCN: V_MAX_F32_e32 [[SGPR0]], [[VGPR0]]
+    %4:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.maxnum.f32), %1, %0
+
+    ; maxnum sv
+    ; GCN: V_MAX_F32_e32 [[SGPR0]], [[VGPR0]]
+    %5:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.maxnum.f32), %0, %1
+
+    ; maxnum vv
+    ; GCN: V_MAX_F32_e32 [[VGPR0]], [[VGPR1]]
+    %6:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.maxnum.f32), %1, %2
+
+    G_STORE %4, %3 :: (store 4 into %ir.global0)
+    G_STORE %5, %3 :: (store 4 into %ir.global0)
+    G_STORE %6, %3 :: (store 4 into %ir.global0)
+...
+---
Index: test/CodeGen/AMDGPU/GlobalISel/inst-select-minnum.mir
===================================================================
--- /dev/null
+++ test/CodeGen/AMDGPU/GlobalISel/inst-select-minnum.mir
@@ -0,0 +1,44 @@
+# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
+
+--- |
+  define void @minnum(i32 addrspace(1)* %global0) { ret void }
+
+  declare float @llvm.minnum.f32(float, float)  #0
+
+  attributes #0 = { readnone speculatable }
+...
+---
+
+name:            minnum
+legalized:       true
+regBankSelected: true
+
+# GCN-LABEL: name: minnum
+body: |
+  bb.0:
+    liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr3_vgpr4
+    ; GCN: [[SGPR0:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+    ; GCN: [[VGPR0:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; GCN: [[VGPR1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+    %0:sgpr(s32) = COPY $sgpr0
+    %1:vgpr(s32) = COPY $vgpr0
+    %2:vgpr(s32) = COPY $vgpr1
+    %3:vgpr(s64) = COPY $vgpr3_vgpr4
+
+    ; minnum vs
+    ; GCN: V_MIN_F32_e32 [[SGPR0]], [[VGPR0]]
+    %4:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.minnum.f32), %1, %0
+
+    ; minnum sv
+    ; GCN: V_MIN_F32_e32 [[SGPR0]], [[VGPR0]]
+    %5:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.minnum.f32), %0, %1
+
+    ; minnum vv
+    ; GCN: V_MIN_F32_e32 [[VGPR0]], [[VGPR1]]
+    %6:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.minnum.f32), %1, %2
+
+    G_STORE %4, %3 :: (store 4 into %ir.global0)
+    G_STORE %5, %3 :: (store 4 into %ir.global0)
+    G_STORE %6, %3 :: (store 4 into %ir.global0)
+...
+---